KR950700592A - 한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법(circuit for the buffer storage of a bit, and use of the circuit as an address buffer store) - Google Patents

한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법(circuit for the buffer storage of a bit, and use of the circuit as an address buffer store)

Info

Publication number
KR950700592A
KR950700592A KR1019940702870A KR19940702870A KR950700592A KR 950700592 A KR950700592 A KR 950700592A KR 1019940702870 A KR1019940702870 A KR 1019940702870A KR 19940702870 A KR19940702870 A KR 19940702870A KR 950700592 A KR950700592 A KR 950700592A
Authority
KR
South Korea
Prior art keywords
circuit
bit
address
latching
storage element
Prior art date
Application number
KR1019940702870A
Other languages
English (en)
Other versions
KR100255701B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR950700592A publication Critical patent/KR950700592A/ko
Application granted granted Critical
Publication of KR100255701B1 publication Critical patent/KR100255701B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Communication Control (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Transceivers (AREA)
KR1019940702870A 1992-02-21 1993-02-01 한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법 KR100255701B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4205339 1992-02-21
DEP4205339.0 1992-02-21
PCT/DE1993/000076 WO1993017434A1 (de) 1992-02-21 1993-02-01 Schaltungsanordnung zum zwischenspeichern eines bits und deren verwendung als adresszwischenspeicher

Publications (2)

Publication Number Publication Date
KR950700592A true KR950700592A (ko) 1995-01-16
KR100255701B1 KR100255701B1 (ko) 2000-05-01

Family

ID=6452285

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940702870A KR100255701B1 (ko) 1992-02-21 1993-02-01 한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법

Country Status (9)

Country Link
US (1) US5448194A (ko)
EP (1) EP0627117B1 (ko)
JP (1) JP3522751B2 (ko)
KR (1) KR100255701B1 (ko)
AT (1) ATE128572T1 (ko)
DE (1) DE59300689D1 (ko)
HK (1) HK1001178A1 (ko)
TW (1) TW294861B (ko)
WO (1) WO1993017434A1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7094427B2 (en) * 2002-05-29 2006-08-22 Impax Laboratories, Inc. Combination immediate release controlled release levodopa/carbidopa dosage forms

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156940A (en) * 1978-03-27 1979-05-29 Rca Corporation Memory array with bias voltage generator
US4754165A (en) * 1986-07-29 1988-06-28 Hewlett-Packard Company Static MOS super buffer latch
EP0262411A1 (de) * 1986-09-01 1988-04-06 Siemens Aktiengesellschaft Adressdecoder für CMOS-Schaltkreise
EP0361807A3 (en) * 1988-09-30 1990-10-17 Advanced Micro Devices, Inc. Shift register bit apparatus
JPH02141993A (ja) * 1988-11-21 1990-05-31 Toshiba Corp 半導体記憶装置
US5003513A (en) * 1990-04-23 1991-03-26 Motorola, Inc. Latching input buffer for an ATD memory
US5347173A (en) * 1990-07-31 1994-09-13 Texas Instruments Incorporated Dynamic memory, a power up detection circuit, and a level detection circuit
US5128897A (en) * 1990-09-26 1992-07-07 Sgs-Thomson Microelectronics, Inc. Semiconductor memory having improved latched repeaters for memory row line selection
EP0505653A1 (en) * 1991-03-29 1992-09-30 International Business Machines Corporation Combined sense amplifier and latching circuit for high speed ROMs
US5349243A (en) * 1993-06-30 1994-09-20 Sgs-Thomson Microelectronics, Inc. Latch controlled output driver
US5396108A (en) * 1993-09-30 1995-03-07 Sgs-Thomson Microelectronics, Inc. Latch controlled output driver

Also Published As

Publication number Publication date
WO1993017434A1 (de) 1993-09-02
KR100255701B1 (ko) 2000-05-01
EP0627117A1 (de) 1994-12-07
EP0627117B1 (de) 1995-09-27
US5448194A (en) 1995-09-05
DE59300689D1 (de) 1995-11-02
HK1001178A1 (en) 1998-05-29
JP3522751B2 (ja) 2004-04-26
JPH07504289A (ja) 1995-05-11
ATE128572T1 (de) 1995-10-15
TW294861B (ko) 1997-01-01

Similar Documents

Publication Publication Date Title
KR920001539A (ko) 적분 논리 기능을 가진 감지증폭기
JPS5619586A (en) Semiconductor memory unit
KR900008526A (ko) 반도체 기억장치
KR960018901A (ko) 피이드백 래치 및 피이드백 래치의 피이드백 동작 형성 방법
KR870002653A (ko) 래치 엎 현상을 감소시키는 상보형 반도체장치
KR920022293A (ko) 비정기적인 리프레쉬 동작을 실행하는 반도체 메모리 장치
US5901110A (en) Synchronous memory with dual sensing output path each of which is connected to latch circuit
KR950703784A (ko) 잡음 감소형 고속 메모리 감지 증폭기(high speed memory sense amplifier with noise reduction)
KR960038997A (ko) 반도체 메모리장치의 전류센스앰프회로
KR950020704A (ko) 반도체 메모리 장치
KR890013769A (ko) 중간전위생성회로
KR950004271A (ko) 반도체 메모리 장치의 전원전압 감지회로
KR950700592A (ko) 한 비트를 래칭하기 위한 회로와 이를 어드레스 래치로 이용하는 방법(circuit for the buffer storage of a bit, and use of the circuit as an address buffer store)
KR950006300B1 (ko) 반도체 메모리 회로
KR960025776A (ko) 셰어드 센스앰프 방식의 센스 램프로 소비되는 전력을 경감한 반도체 기억 장치
KR950015394A (ko) 스태틱 랜덤 억세스 메모리
KR850008238A (ko) 반도체 기억장치
JPS5677983A (en) Decorder circuit
KR920007187A (ko) 반도체 기억장치
KR950004856B1 (en) Data transmitiing circuit
KR960042746A (ko) 반도체 메모리장치의 다이나믹 레벨 컨버터
KR900010778A (ko) 반도체 메모리장치
US6822885B2 (en) High speed latch and compare function
KR0182011B1 (ko) 출력 데이타 안정화를 위한 라이트 드라이버
KR940026964A (ko) 반도체 메모리 장치

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080128

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee