KR950028151A - Method for forming charge storage electrode of memory device - Google Patents

Method for forming charge storage electrode of memory device Download PDF

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Publication number
KR950028151A
KR950028151A KR1019940005704A KR19940005704A KR950028151A KR 950028151 A KR950028151 A KR 950028151A KR 1019940005704 A KR1019940005704 A KR 1019940005704A KR 19940005704 A KR19940005704 A KR 19940005704A KR 950028151 A KR950028151 A KR 950028151A
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South Korea
Prior art keywords
forming
interlayer insulating
undoped
storage electrode
memory device
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KR1019940005704A
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Korean (ko)
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KR0168121B1 (en
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박영진
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김주용
현대전자산업 주식회사
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Priority to KR1019940005704A priority Critical patent/KR0168121B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 메모리 소자의 전하저장전극 형성방법에 관한 것으로, 언도프 폴리실리콘(Undoped Poly-Si), 도프폴리실리콘(Doped Poly-Si) 및 언도프 폴리실리콘층을 순차적으로 형성시킨후 열처리에 의해 상기 도프 폴리실리콘의 도펀트(dopant)가 상하부 언도프 폴리실리콘의 그레인 바운더리(Grain Boundary)로 확산(Diffusion)되게한 다음 상기 언도프 폴리실리콘층의 도프 그레인 바운더리(Doped Grain Boundary)를 습식식각 하므로써 핀(Fin)형 구조의 날개 양면의 요철형상의 전하저장전극이 형성되어 캐패시터(Capacitor)의 표면적을 증가시킬 수 있도록 한 메모리 소자의 전하저장전극 형성방법에 관해 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a memory device, wherein the undoped polysilicon, the dope polysilicon, and the undoped polysilicon layer are sequentially formed, The dopant of the dope polysilicon is diffused into the grain boundary of the upper and lower undoped polysilicon, and then the pinned by wet etching the doped grain boundary of the undoped polysilicon layer. A method of forming a charge storage electrode of a memory device in which an uneven charge storage electrode on both sides of a wing having a (Fin) structure is formed to increase a surface area of a capacitor is described.

Description

메모리 소자의 전하저장전극 형성방법Method for forming charge storage electrode of memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1F도는 본 발명에 따른 메모리 소자의 전하저장전극 형성방법을 설명하기 위한 소자의 단면도,1A to 1F are cross-sectional views of a device for explaining a method of forming a charge storage electrode of a memory device according to the present invention;

제2도는 본 발명의 다른 실시예.2 is another embodiment of the present invention.

Claims (6)

메모리 소자의 전자저장전극 형성방법에 있어서, 필드 산화막(3), 워드선(1) 및 스페이서 산화막(2)이 형성된 실리콘 기판(10)상에 제1층간 절연막(4), Si3N4막(5) 및 제2층간 절연막(6)을 순차적으로 형성시키는 단계와, 상기 단계로부터 마스크를 사용하여 사진 및 식각공정에 의해 저장노드 콘택홀을 형성시키는 단계와, 상기 단계로부터 제1언도프 폴리실리콘층(7), 인-시투 도프 폴리실리콘층(8) 및 제2 언도프 폴리실리콘층(9)을 순차적으로 형성시키는 단계와, 상기 단계로부터 소정의 크기의 저장노드를 형성하기 위해 상기 언도프 및 도프 폴리실리콘(7,8 및9)의 양측면을 제거하여 패터닝 시키는 단계와, 상기 단계로부터 산화막 습식 에천트를 사용하여 상기 제2층간 절연막(6)을 제거시키는 단계와, 상기 단계로부터 일정온도에서 일정시간동안 열처리 공정을 진행한 후 실리콘 습식 에천트로 언도프 폴리실리콘층(7 및 9)의 그레인 바운더리를 식각하여 요철형상을 만들고, 다시 후속 열처리공정을 진행하여 언도프 폴리실리콘층(7 및 9)에 도펀트가 고르게 도핑되는 단계로 이루어지는 것을 특징으로 하는 메모리 소자의 전하저장전극 형성방법.A method for forming an electron storage electrode of a memory device, comprising: a first interlayer insulating film 4 and a Si 3 N 4 film on a silicon substrate 10 on which a field oxide film 3, a word line 1, and a spacer oxide film 2 are formed. (5) and forming a second interlayer insulating film 6 sequentially; forming a storage node contact hole by a photolithography and etching process using a mask from the step; and from the step, a first undoped poly Sequentially forming a silicon layer (7), an in-situ dope polysilicon layer (8) and a second undoped polysilicon layer (9), and from said step to form a storage node of a predetermined size. Removing and patterning both sides of the dope and dope polysilicon (7, 8, and 9), removing the second interlayer insulating film (6) from the step using an oxide wet etchant, and Heat treatment for a certain time at temperature After the crystallization, the grain boundary of the undoped polysilicon layers 7 and 9 is etched with a silicon wet etchant to form an uneven shape, and then a subsequent heat treatment process is performed to the undoped polysilicon layers 7 and 9. A method of forming a charge storage electrode of a memory device, characterized in that the step of evenly doping. 제1항에 있어서, 상기 제1 및 제2층간 절연막(4 및 6)은 SiO2가 화학기상증착 공정에 의해 증착되는 것을 특징으로 하는 메모리 소자의 전하저장전극 형성방법.In the first and second interlayer insulating films 4 and 6 are formed in the charge storage electrode of the memory element, it characterized in that the SiO 2 is deposited by a chemical vapor deposition process according to claim 1. 제1항에 있어서, 상기 언도프 및 도프 폴리실리콘층(7,8 및 9)은 실리콘 소오스 가스가 그대로유지되는 상태에서 도펀트 가스만 오프/온 시키며 비정질 실리콘을 화학기상증착 공정에 의해 증착시키는 것을 특징으로 하는 메모리 소자의 전하저장전극 형성방법.The method of claim 1, wherein the undoped and dope polysilicon layers 7, 8 and 9 turn off / on only the dopant gas while the silicon source gas is kept intact and depositing amorphous silicon by a chemical vapor deposition process. A charge storage electrode forming method of a memory device characterized in that. 제1항에 있어서, 상기 열처리 공정은 600 내지 700℃의 온도 상태에서 1시간동안 이루어지는 것을 특징으로 하는 메모리 소자의 전하저장전극 형성방법.The method of claim 1, wherein the heat treatment is performed at a temperature of 600 to 700 ° C. for 1 hour. 제3항에 있어서, 상기 언도프 폴리실리콘층(7 및 8)은 300 내지 1000Å 두께로 형성되는 것을 특징으로 하는 메모리 소자의 전하저장전극 형성방법.4. The method of claim 3, wherein the undoped polysilicon layers (7 and 8) are formed to a thickness of 300 to 1000 microns. 메모리 소자의 전하저장전극 형성방법에 있어서, 필드 산화막(3), 워드선(1) 및 스페이서 산화막(2)이 형성된 실리콘 기판(10)상에 제1층간 절연막(4), Si3N4막(5) 및 제2층간 절연막(6)을 형성시킨 다음 언도프 폴리실리콘층(12), 도프 폴리실리콘층(13) 언도프 폴리실리콘층(14) 및 제N층간 절연막(11)을 순차적으로 N번 형성시키는 단계와, 상기 단계로부터 마스크를 사용하여 사진 및 식각공정에 의해 저장 노드 콘택홀을 형성시키는 단계와, 상기 단계로부터 제1언도프 폴리실리콘층(7), 인-시투 도프 폴리실리콘층(8) 및 제2 언도프 폴리실리콘층(9)을 순차적으로 형성시키는 단계와, 상기 단계로부터 소정크기의 저장노드를 형성하기 위해 상기 언도프 및 도프 폴리실리콘(7, 8, 9, 12, 13 및 14) 및 층간 절연막(11)의 양측면을 제거하여 패터닝 시키는 단계와, 상기 단계로부터 산화막 습식 에천트를 사용하여 제2 및 제N층간 절연막(6 및 11)을 제거시키는 단계와, 상기 단계로부터 일정온도에서 일정시간동안 열처리 공정을 진행한 후 다시 후속 열처리 공정을 진행하는 단계로 이루어지는 것을 특징으로 하는 메모리 소자의 전하저장전극 형성방법.In the charge storage electrode formation method of the memory device, the first interlayer insulating film 4 and the Si 3 N 4 film on the silicon substrate 10 on which the field oxide film 3, the word line 1 and the spacer oxide film 2 are formed. (5) and the second interlayer insulating film 6, and then the undoped polysilicon layer 12, the dope polysilicon layer 13, the undoped polysilicon layer 14, and the Nth interlayer insulating film 11 are sequentially Forming N times, forming a storage node contact hole by a photo and etching process using a mask from the step; and from the step, the first undoped polysilicon layer (7), an in-situ dope polysilicon Sequentially forming the layer 8 and the second undoped polysilicon layer 9, and the undoped and dope polysilicon 7, 8, 9, 12 to form a storage node of a predetermined size from the step. 13 and 14) and removing and patterning both sides of the interlayer insulating film 11; Removing the second and Nth interlayer insulating films 6 and 11 by using an oxide wet etchant from the system, and then performing a subsequent heat treatment process for a predetermined time at a predetermined temperature from the step. The charge storage electrode forming method of the memory device, characterized in that consisting of. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940005704A 1994-03-22 1994-03-22 Storage electrode fabrication method of memory device KR0168121B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100228420B1 (en) * 1995-12-02 1999-11-01 김영환 Capacitor electrode fabrication method of semiconductor device
KR20010059998A (en) * 1999-12-31 2001-07-06 박종섭 Forming method for capacitor of semiconductor device
KR100334960B1 (en) * 1998-12-26 2002-06-20 박종섭 Method for forming charge storage electrode of capacitor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100228420B1 (en) * 1995-12-02 1999-11-01 김영환 Capacitor electrode fabrication method of semiconductor device
KR100334960B1 (en) * 1998-12-26 2002-06-20 박종섭 Method for forming charge storage electrode of capacitor
KR20010059998A (en) * 1999-12-31 2001-07-06 박종섭 Forming method for capacitor of semiconductor device

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KR0168121B1 (en) 1998-12-15

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