KR970003844A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR970003844A
KR970003844A KR1019950017489A KR19950017489A KR970003844A KR 970003844 A KR970003844 A KR 970003844A KR 1019950017489 A KR1019950017489 A KR 1019950017489A KR 19950017489 A KR19950017489 A KR 19950017489A KR 970003844 A KR970003844 A KR 970003844A
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KR
South Korea
Prior art keywords
forming
film
high temperature
doped
low temperature
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Application number
KR1019950017489A
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Korean (ko)
Inventor
김현수
이석규
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950017489A priority Critical patent/KR970003844A/en
Publication of KR970003844A publication Critical patent/KR970003844A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자 제조방법에 관한 것으로, 반도체기판 상부에 게이트산화막, 제1저온증착 도핑된 다결정실리콘막, 제1고온증착 도핑된 다결정실리콘막 및 제1실리사이드막을 순차적으로 형성하고 워드라인마스크를 이용한 식각공정으로 워드라인을 형성한 다음, 상기 워드라인의 측벽에 절연막 스페이서를 형성하고 불순물 주입공정으로 불순물 접합영역을 형성한 다음, 전체표면상부에 내부절연막을 형성하고 콘택마스크를 이용한 식각공정으로 상기 불순물 접합영역을 노출시키는 콘택홀을 형성한 다음, 전체표면상부에 제2저온증착 도핑된 다결정실리콘막, 제2고온증착 도핑된 다결정실리콘막 및 제2실리사이드막을 순차적으로 형성하여 상기 제1,2저온증착 도핑된 다결정실리콘막을 비정질구조로 형성함으로써 상기 다결정실리콘막에 도핑된 불순물이 상기 다결정실리콘막 하부의 게이트산화막이나 반도체기판으로 확산되어 반도체소자의 특성 및 신뢰성이 저하되는 것을 방지하여 상기 특성 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, and sequentially forming a gate oxide film, a first low temperature doped polycrystalline silicon film, a first high temperature doped polycrystalline silicon film, and a first silicide film on a semiconductor substrate, and forming a word line mask. After the word line is formed by using the etching process, an insulating film spacer is formed on the sidewall of the word line, and an impurity junction region is formed by the impurity implantation process. Then, an internal insulation layer is formed on the entire surface, and the etching process is performed by using a contact mask. After forming a contact hole exposing the impurity junction region, a second low temperature doped polycrystalline silicon film, a second high temperature evaporated doped polycrystalline silicon film, and a second silicide film are sequentially formed on the entire surface of the first, 2) doping the polysilicon film by forming a low temperature deposition doped polysilicon film in an amorphous structure The impurity is prevented from being diffused into the gate oxide film or the semiconductor substrate under the polysilicon film to reduce the characteristics and the reliability of the semiconductor device, thereby improving the characteristics and the reliability and enabling high integration of the semiconductor device.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1C도는 본 발명의 실시예에 따른 반도체소자 제조방법을 도시한 단면도.1C is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Claims (4)

반도체기판 상부에 소자분리절연막을 형성하는 공정과, 전체표면상부에 게이트산화막을 형성하는 공정과, 전체표면상부에 제1저온증착 도핑된 다결정실리콘막과 제1고온증착 도핑된 다결정실리콘막을 형성하는 공정과, 상기 제1고온증착 도핑된 다결정실리콘막 상부에 제1실리사이드막을 형성하는 공정과, 워드라인마스크를 이용한 식각공정으로 워드라인을 형성하는 공정과 상기 워드라인의 측벽에 절연막 스페이서를 형성하는 공정과, 상기 반도체기판 상부에 형성된 구조물을 마스크로하여 상기 반도체기판의 예정된 부분에 불순물 접합영역을 형성하는 공정과, 전체표면상부에 내부절연막을 형성하는 공정과, 콘택마스크를 이용한 식각공정으로 콘택홀을 형성하는 공정과, 전체표면상부에 제2저온증착 도핑된 다결정실리콘막과 제2고온증착 도핑된 다결정 실리콘막을 형성하는 공정과, 상기 제1고온증착 도핑된 다결정실리콘막 상부에 제2실리사이드막을 형성하는 공정과, 비트라인마스크를 이용한 식각공정으로 비트라인을 형성하는 공정으로 포함하는 반도체소자 제조방법.Forming a device isolation insulating film over the semiconductor substrate, forming a gate oxide film over the entire surface, and forming a first low temperature doped polycrystalline silicon film and a first high temperature evaporated doped polysilicon film on the entire surface. Forming a word line by a process, forming a first silicide layer on the first high temperature evaporated doped polysilicon layer, etching by using a word line mask, and forming insulating film spacers on sidewalls of the word line. A process of forming an impurity junction region in a predetermined portion of the semiconductor substrate using the process, a structure formed on the semiconductor substrate as a mask, a process of forming an internal insulating film over the entire surface, and an etching process using a contact mask A process of forming a hole, a polysilicon film and a second high temperature deposition doped with a second low temperature deposition doping on the entire surface A semiconductor device manufacturing method comprising: forming a doped polycrystalline silicon film, forming a second silicide film on the first high temperature-doped doped polysilicon film, and forming a bit line by an etching process using a bit line mask. Way. 제1항에 있어서, 상기 제1,2저온증착 도핑된 다결정실리콘막은 500 내지 600℃의 온도에서 증착되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the first and second low temperature doped polysilicon films are deposited at a temperature of 500 to 600 ° C. 6. 제1항에 있어서, 상기 제1,2고온증착 도핑된 다결정실리콘막은 650 내지 1000℃의 온도에서 증착되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the first and second high temperature doped polysilicon films are deposited at a temperature of 650 to 1000 ° C. 7. 제1항에 있어서, 상기 제1,2저온증착 도핑된 다결정실리콘막과 상기 제1,2고온증착 도핑된 다결정실리콘막 그리고 상기 제1,2실리사이드막은 인쉬트 공정으로 형성되는 것을 특징으로 하는 반도체소자 제조방법.The semiconductor of claim 1, wherein the first and second low temperature doped polysilicon layers, the first and second high temperature doped polysilicon layers, and the first and second silicide layers are formed by an in-situ process. Device manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017489A 1995-06-26 1995-06-26 Semiconductor device manufacturing method KR970003844A (en)

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KR1019950017489A KR970003844A (en) 1995-06-26 1995-06-26 Semiconductor device manufacturing method

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KR1019950017489A KR970003844A (en) 1995-06-26 1995-06-26 Semiconductor device manufacturing method

Publications (1)

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KR970003844A true KR970003844A (en) 1997-01-29

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KR1019950017489A KR970003844A (en) 1995-06-26 1995-06-26 Semiconductor device manufacturing method

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