KR930008074B1 - Method of fabricating for memory cell - Google Patents

Method of fabricating for memory cell Download PDF

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KR930008074B1
KR930008074B1 KR1019910000895A KR910000895A KR930008074B1 KR 930008074 B1 KR930008074 B1 KR 930008074B1 KR 1019910000895 A KR1019910000895 A KR 1019910000895A KR 910000895 A KR910000895 A KR 910000895A KR 930008074 B1 KR930008074 B1 KR 930008074B1
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forming
film
polysilicon film
polysilicon
gate
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KR1019910000895A
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Korean (ko)
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KR920015573A (en
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김익년
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

A memory cell, which comprises a gate having an expanded effective channel length and a large capacitance capacitor, is prepared by (1) forming a block oxide film by photo-etching, (2) depositing a thin polysilicon film for a transistor channel, (3) eliminating the polysilicon on a field region, (4) annealing for recrystallization, (5) depositing a thick polysilicon film, forming a side wall polysilicon film by etching and annealing, (6) forming a gate oxide film over all region and forming a source/drain region by ion-implaning on the side wall polysilicon film, (7) forming a gate polysilicon film on an activated region and a field region and forming a contact between gates by photo-etching, and (8) forming a polysilicon film for stack structure and a polysilicon film for storage node, and forming a capacitor dielectric film and a plate polysilicon film in turn.

Description

메모리 셀 제조 방법Memory Cell Manufacturing Method

제 1 도는 종래의 제조공정단면도.1 is a cross-sectional view of a conventional manufacturing process.

제 2 도는 본 발명의 제조공정단면도.2 is a cross-sectional view of the manufacturing process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : P형기판 2 : P 형 웰1: P type substrate 2: P type well

3 : 블록산화막 4 : 얇은 폴리실리콘막3: block oxide film 4: thin polysilicon film

5 : 두꺼운 폴리실리콘막 6 : 측벽폴리실리콘막5: thick polysilicon film 6: sidewall polysilicon film

7 : 게이트산화막 8 : 게이트폴리실리콘막7: gate oxide film 8: gate polysilicon film

9 : 절연용 HTO막 10 : 스택구조용폴리실리콘막9: HTO film for insulation 10: Polysilicon film for stack structure

11 : 스토리지노드폴리실리콘막 12 : 커패시터유전체막11: storage node polysilicon film 12: capacitor dielectric film

13 : 플레이트 폴리실리콘막13: plate polysilicon film

본 발명은 메모리 셀(Momory cell) 제조방법에 관한 것으로, 특히 산화막블럭(Block)을 이용하여 게이트부분의 유효 채널 길이의 확장과 공정감소 및 커패시터 용량증대에 적합하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a memory cell, and is particularly suitable for extending an effective channel length of a gate portion, reducing a process, and increasing a capacitor capacity by using an oxide block.

종래의 메모리 셀 제조공정을 첨부된 제 1a 도 내지 제 1e 도를 참조하여 상술하면 다음과 같다.A conventional memory cell manufacturing process will be described below with reference to FIGS. 1A through 1E.

먼저 제 1a 도와 같이 P형 기판(20)위에 P형 웰(21)을 형성하고 필드산화막(22)을 형성한 다음 제 1b 도와 같이 통상의 방법으로 액티브영역과 필드산화막(22)상에 게이트산화막(23)과 게이트폴리실리콘막(24)과 게이트캡산화막(25)으로 이루어진 게이트를 형성한다.First, the P-type well 21 is formed on the P-type substrate 20 as shown in FIG. 1A, and the field oxide film 22 is formed. Then, the gate oxide film is formed on the active region and the field oxide film 22 in the usual manner as in FIG. 1B. A gate formed of the 23, the gate polysilicon film 24, and the gate cap oxide film 25 is formed.

그리고 제 1c 도와 같이 N-형 이온을 주입하여 N-형 소오스 및 드레인 영역(S, D)을 형성하고 전체적으로 HTO(High Temperature Oxide)막을 형성하고 이를 에치하여 게이트측벽산화막(26)을 형성한 다음 N+형 이온을 주입하여 N+형 소오스 및 드레인 영역(S1, D1)을 형성하므로써 LDD(Lightly Doped Drain)구조의 트랜지스터를 완성한다.N - type source and drain regions (S, D) are formed by implanting N - type ions as shown in FIG. 1C, and a high temperature oxide (HTO) film is formed as a whole and etched to form a gate sidewall oxide layer 26. By implanting N + -type ions to form N + -type source and drain regions S 1 and D 1 , a transistor having a LDD (Lightly Doped Drain) structure is completed.

이어 제 1d 도와 같이 절연용 HTO막(27)을 전체적으로 증착하고 이 절연용 HTO막(27)위의 사진석판술로 콘택영역을 정의하고 HTO막(27)을 선택적으로 제지하고 콘택트를 형성한 다음 전체적으로 스택(Stack)구조용 폴리실리콘막(20)을 증착하고 이위에 커패시터 면적확장을 위한 사진석판술 및 에치 공정을 실시한다.Subsequently, as shown in FIG. 1D, the insulating HTO film 27 is entirely deposited, the contact area is defined by photolithography on the insulating HTO film 27, and the HTO film 27 is selectively restrained and the contact is formed. The stack (polysilicon film) 20 for the stack (Stack) structure is deposited as a whole, and photolithography and etch processes are performed to expand the capacitor area.

그리고 전체적으로 스토리지노드(Storagenode) 폴리실리콘막(29)을 형성한다.The storage node polysilicon layer 29 is formed as a whole.

이어 제 1e 도와 같이 커패시터 유전체막으로서의 ONO(Oxide-Nitride-Oxide)막(30)과 플레이트(Palate)폴리실리콘막(31)을 차례로 증착하므로써 커패시터를 완성한다.Subsequently, the capacitor is completed by sequentially depositing an oxide-nitride-oxide (ONO) film 30 and a plate polysilicon film 31 as the capacitor dielectric film, as shown in FIG.

그러나 상기 종래기술은 다음과 같은 단점이 있었다.However, the prior art has the following disadvantages.

첫째, 소자가 고집적화됨에 따라 기존의 게이트구조를 사용할 경우 효율적인 채널길이를 확보하기 위해 많은 공정 스텝이 필요하였다. 그럼에도 불구하고 효율적인 채널길이의 확보에는 한계가 있었다.First, as the device is highly integrated, many process steps are required to secure an efficient channel length when using a conventional gate structure. Nevertheless, there was a limit to securing effective channel length.

둘째, 커패시터 면적확대에 한계가 있었다.Second, there was a limit to the capacitor area enlargement.

셋째, 필드산화시 발생되는 버즈 비크(Bird's Beak)로 인해 내로우 위드 효과(Narrow Width Effect)가 발생하였다.Third, a narrow width effect was generated due to Bird's Beak generated during field oxidation.

본 발명은 상기 단점을 제거키위한 것으로 이를 첨부된 제 2a 도 내지 제 2e 도를 참조하여 상술하면 다음과 같다.The present invention is to eliminate the above disadvantages and will be described with reference to the accompanying drawings 2a to 2e as follows.

먼저 제 2a 도와 같이 P형기판(1)위에 P형웰(2)을 형성하고 CVD(Chemical Vapour Deposition)법으로 HTO(또는 LTO)막을 증착하고 이위에 사진석판술 및 에치 공정을 실시하여 불필요한 부분을 제거하므로써 블럭산화막(3)을 형성한다. 그리고 제 2 b 도와 같이 트랜지스터의 채널로 이용될 얇은 폴리실리콘막(4)을 약 300Å 이하의 두께로 증착하고 사진석판술로 필드영역을 정의하여 필드영역의 것을 제거한 다음 상기 얇은 폴리실리콘막(4)의 재결정화를 위해 어닐링(Annealing)을 실시한다.First, as shown in FIG. 2a, P-type wells 2 are formed on P-type substrates 1, HTO (or LTO) films are deposited by chemical vapor deposition (CVD), and photolithography and etch processes are performed thereon. By removing, the block oxide film 3 is formed. Then, as shown in FIG. 2B, a thin polysilicon film 4 to be used as a channel of the transistor is deposited to a thickness of about 300 m 3 or less, and a field region is defined by photolithography to remove the field region, and then the thin polysilicon film 4 Annealing is carried out for recrystallization.

그리고 전체적으로 두꺼운 폴리실리콘막(5)을 증착한 다음 제 2c 도와 같이 에치하여 블록산화막(3)에 측벽폴리실리콘막(6)을 형성하고 다시 어닐링을 실시한다. 이어 게이트산화막(7)을 전체적으로 형성하고 상기 측벽폴리실리콘막(6)에 N+형 이온 주입을 실시하여 N+형 소오스 및 드레인 영역(S, D)을 형성한다. 그리고 제 2d 도와 같이 액티브영역과 필드영역의 각 블럭산화막(3)상에 게이트폴리실리콘막(8)을 형성한 다음 전체적으로 절연용 HTO막(9)을 형성하고 이 HTO막(9)위에 사진석판술 및 에치 공정을 실시하여 액티브영역과 필드영역상의 게이트사이에 콘택트를 형성한다.Then, the entire thick polysilicon film 5 is deposited and etched as shown in FIG. 2C to form the sidewall polysilicon film 6 on the block oxide film 3 and then annealed again. Subsequently, the gate oxide film 7 is formed as a whole, and N + -type ion implantation is performed on the sidewall polysilicon film 6 to form N + -type source and drain regions S and D. Then, as shown in FIG. 2D, a gate polysilicon film 8 is formed on each block oxide film 3 in the active region and the field region, and then an insulating HTO film 9 is formed as a whole. Tassel and etch processes are performed to form contacts between the gates on the active and field regions.

이어 스택구조용 폴리실리콘막(10)을 형성하고 이 폴리실리콘막(10)위에 사진석판술 및 에치 공정을 실시하여 각 게이트상의 일부만을 남기고 나머지는 제거한다.Then, a polysilicon film 10 for a stack structure is formed, and photolithography and etch processes are performed on the polysilicon film 10 to leave only a part of each gate and remove the rest.

이어 그위에 폴리실리콘막을 증착하고 사진석판술로 스토리지노드영역을 정의하여 불필요한 부분을 제거하므로써 스토리지노드 폴리실리콘막(11)을 형성한다.Subsequently, the polysilicon film is deposited thereon and the storage node region is defined by photolithography to remove unnecessary portions to form the storage node polysilicon film 11.

마지막으로 제 2e 도와 같이 전체적으로 커패시터 유전체막(12)을 형성하고 그위에 플레이트폴리실리콘막(13)을 형성하므로써 공정이 완료된다.Finally, the process is completed by forming the capacitor dielectric film 12 as a whole and the plate polysilicon film 13 thereon as shown in FIG.

이상과 같이 본 발명에 의하면 다음과 같은 효과가 있다.As described above, the present invention has the following effects.

첫째, 기존의 공정에 비해 폴리실리콘막 산화공정과 측벽산화막 형성 공정 및 측벽 형성을 위한 에치공정시의 기판결함을 보상해 주기 위한 포스트 어닐링(Post Annealing)공정 그리고 LDD 구조를 위한 N-형 이온 주입 공정을 생략할 수 있으므로 공정단측의 효과가 있다.First, post annealing process to compensate substrate defects during polysilicon film oxidation process, sidewall oxide film formation process and etch process for sidewall formation and N - type ion implantation for LDD structure Since the step can be omitted, there is an effect on the step side.

둘째, 게이트에 있어서 효율적인 채널길이를 기존의 것보다 길게할 수 있을 뿐만 아니라 블록산화막의 높이 만큼 커패시터 면적을 증대시킬 수 있다.Second, the effective channel length in the gate can be made longer than the conventional one, and the capacitor area can be increased by the height of the block oxide film.

셋째, 격리영역으로서 블록산화막을 이용하므로 버즈비크의 발생을 방지할 수 있으므로 내로우 위드 효과(Narrow Width Effect)를 방지할 수 있다.Third, since the block oxide film is used as the isolation region, it is possible to prevent the occurrence of the buzz beak to prevent the narrow width effect.

Claims (2)

기판위에 기판과 동형의 웰을 형성하고 산화막을 전체적으로 형성한 다음 사진석판술 및 에치 공정을 거쳐 소정 갯수의 블럭산화막을 형성하는 단계, 트랜지스터 채널용 얇은 폴리실리콘막을 증착하고 설정된 필드영역의 블록산화막상에 증착된 것을 제거한 다음 재결정화를 위해 어닐닝 시키는 단계, 두꺼운 폴리실리콘막을 증착하고 에치 공정을 거쳐 블럭산화막 측벽폴리실리콘막을 형성한 다음 어닐링시키는 단계, 전체적으로 게이트 산화막을 형성하고 상기 블럭산화막 측벽폴리실리콘막에 이온 주입을 실시하여 소오스 및 드레인을 형성하는 단계, 액티브영역과 필드영역의 블럭산화막상의 게이트산화막위에 게이트 폴리실리콘막을 형성하고 전체적으로 절연산화막을 형성한 다음 사진석판술 및 에치 공정을 실시하여 각 영역상의 게이트사이에 콘택트를 형성하는 단계, 상기 콘택트상에 스택구조용 폴리실리콘막과 스토리지노드용 폴리실리콘막을 형성한 다음 그위에 커패시터 유전체막과 플레이트 폴리실리콘막을 형성하는 단계가 차례로 포함됨을 특징으로 하는 메모리 셀 제조방법.Forming a well of the same type as the substrate on the substrate, forming an oxide film as a whole, and then forming a predetermined number of block oxide films through photolithography and etching processes, depositing a thin polysilicon film for the transistor channel, and forming a block oxide film on the set field region. Removing the deposited material and then annealing for recrystallization; depositing a thick polysilicon film and etching the block oxide sidewall polysilicon film and then annealing; forming a gate oxide film as a whole and forming the gate oxide sidewall polysilicon Forming a source and a drain by ion implantation into the film; forming a gate polysilicon film on the gate oxide film on the block oxide film in the active and field regions; forming an insulating oxide film as a whole; and performing photolithography and etching processes. Between gates in the area Forming a contact on the contact, forming a polysilicon layer for a stack structure and a polysilicon layer for a storage node on the contact, and then forming a capacitor dielectric layer and a plate polysilicon layer thereon. . 제 1 항에 있어서, 스택구조용 폴리실리콘막은 전체적으로 폴리실리콘막을 형성하고 사진석판술 및 에치 공정을 거쳐 액티브영역과 필드영역상의 게이트 위에 증착된 일부만을 남긴 상태 임을 특징으로 하는 메모리 셀 제조방법.The method of claim 1, wherein the polysilicon film for the stack structure is a polysilicon film as a whole and leaves only a portion of the polysilicon film deposited on the gate in the active region and the field region through photolithography and etching processes.
KR1019910000895A 1991-01-19 1991-01-19 Method of fabricating for memory cell KR930008074B1 (en)

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