KR20010059998A - Forming method for capacitor of semiconductor device - Google Patents
Forming method for capacitor of semiconductor device Download PDFInfo
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- KR20010059998A KR20010059998A KR1019990067994A KR19990067994A KR20010059998A KR 20010059998 A KR20010059998 A KR 20010059998A KR 1019990067994 A KR1019990067994 A KR 1019990067994A KR 19990067994 A KR19990067994 A KR 19990067994A KR 20010059998 A KR20010059998 A KR 20010059998A
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- Prior art keywords
- polysilicon
- storage electrode
- semiconductor device
- capacitor
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000003990 capacitor Substances 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- 238000005137 deposition process Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 21
- 230000010354 integration Effects 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 208000012868 Overgrowth Diseases 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로, 특히 삼차원적구조를 갖는 저장전극을 형성하고 상기 저장전극의 표면에 반구형 폴리 실리콘 ( metastable poly silicon, 이하에서 MPS 라 함 )을 성장시키는 경우 유발될 수 있는 오동작을 방지하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor of a semiconductor device, and in particular, to form a storage electrode having a three-dimensional structure and to be caused when growing hemispherical polysilicon (MPS) on the surface of the storage electrode. The present invention relates to a technique for preventing a malfunction.
반도체소자가 고집적화되어 셀 크기가 감소됨에따라 저장전극의 표면적에 비례하는 정전용량을 충분히 확보하기가 어려워지고 있다.As semiconductor devices are highly integrated and cell size is reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.
특히, 단위셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게하면서, 면적을 줄이는 것이 디램 소자의 고집적화에 중요한 요인이 된다.In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor that occupies a large area on a chip, which is an important factor for high integration of the DRAM device.
그래서, ( εo × εr × A ) / T ( 단, 상기 εo 는 진공유전율, 상기 εr 은 유전막의 유전율, 상기 A 는 캐패시터의 면적 그리고 상기 T 는 유전막의 두께 ) 로 표시되는 캐패시터의 정전용량 C 를 증가시키기 위하여, 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막을 얇게 형성하거나 또는 저장전극의 표면적을 증가시키는 등의 방법을 사용하였다.Thus, εo × εr × A) / T (where, εo is the vacuum dielectric constant, εr is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) of the capacitor C In order to increase, a method of using a material having a high dielectric constant as a dielectric film, forming a thin dielectric film, or increasing the surface area of a storage electrode has been used.
그리고, 상기 저장전극의 표면적을 증가시키기 위하여 삼차원적인 구조를 갖는 저장전극을 형성하였다.In addition, a storage electrode having a three-dimensional structure was formed to increase the surface area of the storage electrode.
그리고, 가장 보편적으로 사용하는 형상이 실린더형 저장전극이다.The most commonly used shape is a cylindrical storage electrode.
도시되진않았으나, 종래기술에 따른 반도체소자의 캐패시터 형성방법을 설명한 것으로서, 자기정렬적인 듀얼 다마신 ( self aligned dual damascene, 이하에서 SADD 라 함 ) 방법을 이용하여 설명한 것이다.Although not shown, as a method of forming a capacitor of a semiconductor device according to the prior art, it is described using a self aligned dual damascene (hereinafter referred to as SADD) method.
먼저, 반도체기판 상부에 하부절연층을 형성한다. 이때, 상기 하부절연층은 소자분리막, 워드라인 및 비트라인 등의 단위소자들이 형성된 것이다.First, a lower insulating layer is formed on the semiconductor substrate. In this case, the lower insulating layer is formed of unit devices such as an isolation layer, a word line, and a bit line.
그리고, 상기 하부절연층은 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BSPG 라 함 ) 절연막이나 피.에스.지. ( phospho silicate glass, 이하에서 PSG 라 함 ) 절연막과 같이 유동성이 우수한 절연물질로 형성한다.The lower insulating layer is made of B.S.G. boro phospho silicate glass, hereinafter referred to as BSPG. (phospho silicate glass, hereinafter referred to as PSG) It is formed of an insulating material with excellent fluidity such as an insulating film.
그리고, 상기 하부절연층 상부에 질화막과 버퍼산화막을 각각 일정두께 증착한다.A nitride film and a buffer oxide film are respectively deposited on the lower insulating layer at a predetermined thickness.
그리고, 콘택마스크를 이용한 사진식각공정으로 상기 버퍼산화막, 질화막 및 하부절연층을 식각하여 상기 반도체기판을 노출시키는 콘택홀을 형성한다.The buffer oxide layer, the nitride layer, and the lower insulating layer are etched by a photolithography process using a contact mask to form a contact hole exposing the semiconductor substrate.
그리고, 상기 콘택홀을 매립하는 희생절연막을 형성하고 상기 질화막을 식각장벽으로 하여 저장전극 예정 영역의 상기 희생절연막을 식각한다.A sacrificial insulating film filling the contact hole is formed, and the sacrificial insulating film of the predetermined region of the storage electrode is etched using the nitride film as an etch barrier.
이때, 상기 콘택홀 내부의 희생절연막도 제거한다.At this time, the sacrificial insulating film inside the contact hole is also removed.
그 다음, 전체표면상부에 폴리실리콘을 일정두께 형성한다.Then, polysilicon is formed on the entire surface at a constant thickness.
그리고, 전체표면상부를 평탄화시키는 감광막을 형성한다.Then, a photosensitive film for flattening the entire upper surface portion is formed.
그 다음, 상기 희생절연막이 노출될때까지 평탄화식각한다.Next, planar etching is performed until the sacrificial insulating film is exposed.
이때, 상기 평탄화식각공정은 에치백공정이나 화학기계연마 ( chemical mechanical polishing, 이하에서 CMP 라 함 ) 공정으로 실시한다.At this time, the planarization etching process is performed by an etch back process or a chemical mechanical polishing (hereinafter referred to as CMP) process.
그 다음, 상기 감광막과 희생절연막을 제거하여 실린더형 저장전극을 형성한다.Next, the photosensitive layer and the sacrificial insulating layer are removed to form a cylindrical storage electrode.
그리고, 상기 실린더형 저장전극 표면에 MPS를 형성하여 상기 저장전극의 표면적을 증가시킨다.Then, MPS is formed on the cylindrical storage electrode surface to increase the surface area of the storage electrode.
그러나, 상기 실린더형 저장전극의 측벽 상부에 형성되는 반구형 MPS 가 저장전극 사이에 떨어져 소자의 오동작을 유발시킬 수 있는 문제점이 있다.However, there is a problem in that the hemispherical MPS formed on the sidewall of the cylindrical storage electrode may fall between the storage electrodes and cause malfunction of the device.
상기한 바와같이 종래기술에 따른 반도체소자의 캐패시터 형성방법은, 삼차원적구조인 실린더형 저장전극의 표면적을 증가시키기 위한 MPS 가 실린더형 저장전극 측벽 상부에서 떨어져 브릿지 ( bridge )를 유발하고 그에 따라 소자가 오동작 됨으로써 반도체소자의 특성 및 신뢰성을 저하시키고 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method of forming a capacitor of a semiconductor device according to the prior art, an MPS for increasing the surface area of a cylindrical storage electrode having a three-dimensional structure is caused to fall off the upper sidewall of the cylindrical storage electrode, thereby causing a bridge. By malfunctioning, there is a problem in that the characteristics and reliability of the semiconductor device are degraded and the integration of the semiconductor device is difficult.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 실린더형 저장전극의 측벽이 구부러 지거나 MPS 가 떨어지는 현상을 방지하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the semiconductor storage electrode prevents the sidewalls from bending or the MPS falls, thereby improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device. It is an object of the present invention to provide a method for forming a capacitor of a device.
도 1a 및 도 1b 는 본 발명의 실시예에 따른 반도체소자의 캐패시터 형성방법을 나타낸 단면도.1A and 1B are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
〈 도면의 주요주분에 대한 부호의 설명 〉<Description of the code | symbol about the main part of drawing>
11 : 하부절연층 13 : 저장전극 콘택플러그11: lower insulating layer 13: storage electrode contact plug
15 : 층간절연막 17 : 폴리실리콘15: interlayer insulating film 17: polysilicon
19 : MPS 21 : 플레이트전극19: MPS 21: plate electrode
상기한 목적 달성을 위해 본 발명에 따른 반도체소자의 캐패시터 형성방법은,Capacitor forming method of a semiconductor device according to the present invention for achieving the above object,
저장전극 콘택플러그가 구비되는 하부절연층을 반도체기판 상부에 형성하는 공정과,Forming a lower insulating layer provided with the storage electrode contact plug on the semiconductor substrate;
상기 콘택플러그에 접속되는 실린더형 저장전극을 폴리실리콘으로 형성하되, 상기 폴리실리콘은 3단계 증착공정으로 형성하는 공정과,Forming a cylindrical storage electrode connected to the contact plug with polysilicon, wherein the polysilicon is formed by a three-step deposition process;
상기 실린더형 저장전극 표면에 MPS 를 형성하되, 상기 저장전극의 측벽에만 구비되는 공정을 포함하는 것을 특징으로한다.Forming MPS on the surface of the cylindrical storage electrode, characterized in that it comprises a process provided only on the sidewall of the storage electrode.
그리고, 상기 폴리실리콘의 3단계 증착공정은, 500 ∼ 530 ℃ 온도로 언도프드 비정질 폴리실리콘을 증착하는 제1단계와, 550 ∼ 570 ℃ 에서 인 ( P ) 의 농도가 3.0 ∼ 5.0 E20 정도인 도프드 폴리실리콘을 증착하는 제2단계와, 500 ∼ 530 ℃ 온도로 언도프드 비정질 폴리실리콘을 증착하는 제3단계로 실시하는 것과,In addition, the three-step deposition process of the polysilicon, the first step of depositing the undoped amorphous polysilicon at a temperature of 500 ~ 530 ℃, and the concentration of phosphorus (P) at 550 ~ 570 ℃ about 3.0 to 5.0 E20 Performing a second step of depositing de-polysilicon; and a third step of depositing undoped amorphous polysilicon at a temperature of 500 to 530 ° C.,
상기 도프드 폴리실리콘은, 실리사이드로 대신 형성하는 것과,The doped polysilicon is, instead of being formed of silicide,
상기 실리사이드는, 150 ∼ 200 Å 두께로 형성하는 것과,The silicide is formed with a thickness of 150 to 200 GPa,
상기 폴리실리콘의 3단계 증착공정은, 각 단계별로 150 ∼ 200 Å 두께만큼의 폴리실리콘을 형성하는 것을 특징으로 한다.The three-step deposition process of the polysilicon, characterized in that for each step to form a polysilicon of 150 to 200 Å thickness.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는,On the other hand, the principle of the present invention for achieving the above object,
저장전극 물질인 폴리실리콘 증착공정을 3단계로 실시하여 종래기술의 문제점인 저장전극이 구부러지거나 MPS 가 떨어지는 것을 방지하는 것이다.By performing the polysilicon deposition process of the storage electrode material in three steps, the storage electrode, which is a problem of the prior art, is prevented from bending or falling of the MPS.
다시말하면, MPS 성장이 되는 부분으로 500 ∼ 530 ℃ 온도인 언도프드 비정질 폴리실리콘을 증착하고, 550 ∼ 570 ℃ 에서 인 ( P ) 의 농도가 3.0 ∼ 5.0 E20 정도인 도프드 폴리실리콘을 증착한 다음, 500 ∼ 530 ℃ 온도인 언도프드 비정질 폴리실리콘을 증착한다. 이로인하여, MPS 성장시 삼차원적 저장전극의 안쪽 및 바깥쪽, 즉 측벽부분에는 MPS 가 성장하고 중앙부분에는 자라지 않아 캐패시터가 구부러 지거나 과도성장으로 인한 MPS 의 떨어짐 현상을 방지한다.In other words, undoped amorphous polysilicon is deposited at a temperature of 500 to 530 ° C., and doped polysilicon having a concentration of phosphorus (P) of about 3.0 to 5.0 E20 is deposited at 550 to 570 ° C. And undoped amorphous polysilicon at a temperature of 500 to 530 ° C. As a result, MPS grows inside and outside of the three-dimensional storage electrode, that is, sidewall portion, and does not grow in the center portion during MPS growth, thereby preventing the dropping of the MPS due to bending of the capacitor or overgrowth.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 및 도 1b 는 본 발명의 실시예에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(도시안됨) 상부에 하부절연층(11)을 형성한다.First, a lower insulating layer 11 is formed on a semiconductor substrate (not shown).
이때, 상기 하부절연층(11)은 소자분리막, 워드라인 및 비트라인 등의 단위소자들이 형성된 것이다.In this case, the lower insulating layer 11 is formed of unit devices such as an isolation layer, a word line and a bit line.
그리고, 상기 하부절연층(11)은 비.피.에스.지. ( boro phospho silicateglass, 이하에서 BSPG 라 함 ) 절연막이나 피.에스.지. ( phospho silicate glass, 이하에서 PSG 라 함 ) 절연막과 같이 유동성이 우수한 절연물질로 형성한다.The lower insulating layer 11 is made of B.S.G. boro phospho silicateglass, hereinafter referred to as BSPG. (phospho silicate glass, hereinafter referred to as PSG) It is formed of an insulating material with excellent fluidity such as an insulating film.
그 다음, 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 상기 하부절연층(11)을 식각하여 상기 반도체기판을 노출시키는 저장전극 콘택홀(도시안됨)을 형성한다.Next, the lower insulating layer 11 is etched by a photolithography process using a contact mask (not shown) to form a storage electrode contact hole (not shown) that exposes the semiconductor substrate.
그리고, 상기 저장전극 콘태홀을 매립하는 콘택플러그(13)를 형성한다.A contact plug 13 is formed to fill the storage electrode contact hole.
이때, 상기 콘택플러그(13)는 상기 반도체기판에 접속되도록 전체표면상부에 텅스텐을 증착하고 이를 평탄화식각하여 형성한 것이다.In this case, the contact plug 13 is formed by depositing tungsten on the entire surface to be connected to the semiconductor substrate and flattening it.
그 다음, 전체표면상부에 층간절연막인 질화막(15)을 일정두께 형성한다.Next, a nitride film 15, which is an interlayer insulating film, is formed on the entire surface.
그리고, 상기 질화막(15) 상부에 희생산화막(도시안됨)을 형성하고 저장전극이 형성될 영역의 상기 희생산화막을 식각한다.In addition, a sacrificial oxide layer (not shown) is formed on the nitride layer 15 and the sacrificial oxide layer in the region where the storage electrode is to be formed is etched.
이때, 상기 희생산화막 식각공정은 저장전극 마스크(도시안됨)를 이용한 사진식각공정으로 실시한다.In this case, the sacrificial oxide etching process is performed by a photolithography process using a storage electrode mask (not shown).
그 다음, 상기 콘택플러그(13)에 접속되는 저장전극용 폴리실리콘(17)을 전체표면상부에 일정두께 형성한다.Then, a polysilicon 17 for a storage electrode connected to the contact plug 13 is formed to have a predetermined thickness on the entire surface.
이때, 상기 폴리실리콘(17)은 3단계로 증착한다.At this time, the polysilicon 17 is deposited in three steps.
여기서, 상기 폴리실리콘(17)의 3단계 증착 공정은, 500 ∼ 530 ℃ 온도인 언도프드 비정질 폴리실리콘을 증착하고, 550 ∼ 570 ℃ 에서 인 ( P ) 의 농도가 3.0 ∼ 5.0 E20 정도인 도프드 폴리실리콘을 증착한 다음, 500 ∼ 530 ℃ 온도인 언도프드 비정질 폴리실리콘을 증착한다. 그리고, 상기 도프드 폴리실리콘은 티타늄실리사이드로 형성할 수도 있다.Here, in the three-step deposition process of the polysilicon 17, undoped amorphous polysilicon is deposited at a temperature of 500 ~ 530 ℃, doped with a phosphorus (P) concentration of about 3.0 to 5.0 E20 at 550 to 570 ℃ After depositing polysilicon, undoped amorphous polysilicon is deposited at a temperature of 500-530 ° C. The doped polysilicon may be formed of titanium silicide.
그 다음, 전체표면상부를 감광막으로 도포하여 평탄화시킨다.Then, the entire upper surface portion is coated with a photosensitive film to planarize it.
그리고, 상기 희생산화막이 노출될때가지 평탄화식각하고 상기 남아있는 감광막과 희생산화막을 제거함으로써 실린더형 저장전극을 형성한다. (도 1a)The cylindrical storage electrode is formed by planarization etching until the sacrificial oxide film is exposed and removing the remaining photoresist layer and the sacrificial oxide film. (FIG. 1A)
그 다음, 상기 실린더형 저장전극 표면에 MPS (19)를 성장시킨다. 이때, 상기 MPS (19)는 상기 3단계 증착공정으로 형성된 폴리실리콘(17)으로 인하여 상기 실린더형 저장전극의 측벽에만 형성된다.Then, the MPS 19 is grown on the cylindrical storage electrode surface. At this time, the MPS 19 is formed only on the sidewall of the cylindrical storage electrode due to the polysilicon 17 formed by the three-step deposition process.
그리고, 상기 저장전극 측벽에 유전체막(도시안됨) 및 플레이트전극(21)을 형성함으로써 반도체소자의 고집적화에 충분한 정전용량을 확보할 수 있는 캐패시터를 형성한다. (도 2b)In addition, by forming a dielectric film (not shown) and a plate electrode 21 on the sidewall of the storage electrode, a capacitor capable of securing a capacitance sufficient for high integration of the semiconductor device is formed. (FIG. 2B)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, 3단계 증착공정으로 삼차원적 저장전극의 측벽에만 MPS 를 형성하여 후속공정시 유발될 수 있는 저장전극 구조의 손실을 방지하여 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 반도체소자의 수율 및 생산성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, in the method of forming a capacitor of a semiconductor device according to the present invention, the MPS is formed only on the sidewalls of the three-dimensional storage electrode by a three-step deposition process, thereby preventing the loss of the storage electrode structure that may be caused in a subsequent process. It improves the characteristics and reliability of the semiconductor device, improves the yield and productivity of the semiconductor device of the semiconductor device and thereby provides an effect of enabling high integration of the semiconductor device.
Claims (5)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100818076B1 (en) * | 2001-12-28 | 2008-03-31 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| KR100927785B1 (en) * | 2002-11-20 | 2009-11-20 | 매그나칩 반도체 유한회사 | Capacitor Formation Method for Semiconductor Device |
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|---|---|---|---|---|
| KR950028151A (en) * | 1994-03-22 | 1995-10-18 | 김주용 | Method for forming charge storage electrode of memory device |
| US5608247A (en) * | 1994-06-14 | 1997-03-04 | Micron Technology Inc. | Storage capacitor structures using CVD tin on hemispherical grain silicon |
| JPH11145389A (en) * | 1997-11-11 | 1999-05-28 | Nec Corp | Manufacture of capacitor |
| US5913119A (en) * | 1998-06-26 | 1999-06-15 | Vanguard Int Semiconduct Corp | Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950028151A (en) * | 1994-03-22 | 1995-10-18 | 김주용 | Method for forming charge storage electrode of memory device |
| US5608247A (en) * | 1994-06-14 | 1997-03-04 | Micron Technology Inc. | Storage capacitor structures using CVD tin on hemispherical grain silicon |
| JPH11145389A (en) * | 1997-11-11 | 1999-05-28 | Nec Corp | Manufacture of capacitor |
| JPH11214661A (en) * | 1997-11-11 | 1999-08-06 | Nec Corp | Manufacture of hsg-containing capacitor |
| US5913119A (en) * | 1998-06-26 | 1999-06-15 | Vanguard Int Semiconduct Corp | Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100818076B1 (en) * | 2001-12-28 | 2008-03-31 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| KR100927785B1 (en) * | 2002-11-20 | 2009-11-20 | 매그나칩 반도체 유한회사 | Capacitor Formation Method for Semiconductor Device |
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