KR100334960B1 - Method for forming charge storage electrode of capacitor - Google Patents
Method for forming charge storage electrode of capacitor Download PDFInfo
- Publication number
- KR100334960B1 KR100334960B1 KR1019980058886A KR19980058886A KR100334960B1 KR 100334960 B1 KR100334960 B1 KR 100334960B1 KR 1019980058886 A KR1019980058886 A KR 1019980058886A KR 19980058886 A KR19980058886 A KR 19980058886A KR 100334960 B1 KR100334960 B1 KR 100334960B1
- Authority
- KR
- South Korea
- Prior art keywords
- charge storage
- amorphous silicon
- storage electrode
- silicon layer
- capacitor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 커패시터의 전하저장전극을 형성하는 방법에서, 반도체기판상의 절연막에 폴리실리콘층 및 코어산화막을 적층한 후 상기 결과물 상에 도핑이 된 제1비정질실리콘을 적층하는 단계와; 상기 단계 후 상기 제1비정질 실리콘층 상에 도핑이 되지 않은 제2비정질실리콘층을 적층하는 단계와; 상기 단계 후 상부로 노출된 코어산화막을 제거한 후 형성된 전하저장전극의 표면에 실리콘원자를 도포하여 성장시켜서 내,외벽면에 그레인을 성장시키는 단계로 이루어진 커패시터의 전하저장전극 형성방법인 바, 전하저장전극의 내,외벽면에 형성되는 그레인의 사이즈를 동일하게 형성하여 전하저장 효율을 증대시키도록 하는 매우 유용하고 효과적인 발명이다.The present invention provides a method of forming a charge storage electrode of a capacitor, comprising: laminating a polysilicon layer and a core oxide layer on an insulating film on a semiconductor substrate and then laminating doped first amorphous silicon on the resultant; Stacking an undoped second amorphous silicon layer on the first amorphous silicon layer after the step; After removing the core oxide film exposed to the upper part after the step, by growing a silicon atom on the surface of the formed charge storage electrode by growing a grain on the inner and outer walls, the charge storage electrode forming method of the capacitor, the charge storage It is a very useful and effective invention to increase the charge storage efficiency by forming the same grain size formed on the inner and outer walls of the electrode.
Description
본 발명은 커패시터에 관한 것으로서, 특히, 제1비정질실리콘층 상에 인이 도핑 되지 않은 제2비정질실리콘층을 적층한 후 전하저장전극을 형성하고, 연속하여 실리콘원자를 전하저장전극의 표면에 도포하여 성장시키므로 내,외벽면에 형성되는 그레인의 사이즈를 동일하게 형성하여 전하저장 효율을 증대시키도록 하는 커패시터의 전하저장전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor, and more particularly, to form a charge storage electrode after laminating a second amorphous silicon layer which is not doped with phosphorus on a first amorphous silicon layer, and subsequently applying silicon atoms to the surface of the charge storage electrode. The present invention relates to a method for forming a charge storage electrode of a capacitor which increases the charge storage efficiency by forming the same grain size formed on the inner and outer wall surfaces.
일반적으로, 커패시터는 전하를 저장하고, 반도체소자의 동작에 필요한 전하를 공급하는 부분으로서, 반도체소자가 고집적화 되어짐에 따라 단위 셀(Cell)의 크기는 작아지면서 소자의 동작에 필요한 정전용량(Capacitance)은 약간 씩 증가하는 것이 일반적인 경향다.In general, a capacitor stores electric charges and supplies electric charges necessary for the operation of the semiconductor device. As the semiconductor device becomes highly integrated, the size of the unit cell becomes smaller and the capacitance required for the operation of the device is reduced. Is a general trend.
이와 같이, 반도체소자의 고집적화가 이루어짐에 따라 커패시터 역시 소형화될 것을 요구 되어지고 있으나 전하를 저장하는 데 한계에 부딪히게 되어 커패시터는 셀의 크기에 비하여 고집적화시킨 데 어려움이 표출되었다.As the semiconductor device is highly integrated, the capacitor is also required to be miniaturized. However, the capacitor has a limitation in storing electric charges, and thus the capacitor is difficult to be highly integrated in comparison with the size of the cell.
이러한 점을 감안하여 각 업체에서 커패시터의 전하를 저장하기 위한 구조를 다양하게 변화하기에 이르렀으며, 커패시터의 전하를 증가시키는 방법에는 유전상수가 큰 물질을 사용하는 방법, 유전물질의 두께를 낮추는 방법 및 커패시터의 표면적을 늘리는 방법등이 있으며, 최근에는 커패시터의 표면적을 증대시키는 방법이 주로 이용되고 있다.In consideration of this, each company has changed the structure to store the charge of the capacitor in various ways, and the method of increasing the charge of the capacitor using a material having a high dielectric constant, a method of reducing the thickness of the dielectric material And a method of increasing the surface area of a capacitor, and in recent years, a method of increasing the surface area of a capacitor is mainly used.
즉, 커패시터의 전하저장전극의 구조를 보면, 크게 전하를 저장하는 전극은 좁은 평면적 위에 여러층을 쌓아서 넓은 커패시터의 면적을 얻고자 하는 적층구조(Stacked Structure)와, 반도체기판에 일정한 깊이의 홈을 형성한 후에 그 부위에 커패시터를 형성하여 전하를 저장하도록 하는 홈 구조(Trench Structure)등으로 크게 대별되어지고 있다.That is, in the structure of the charge storage electrode of the capacitor, the electrode that stores the charge largely has a stacked structure to obtain a large capacitor area by stacking several layers on a narrow plane and a groove having a constant depth in the semiconductor substrate. After the formation, it is largely classified into a trench structure for forming a capacitor at the site and storing charge.
특히, 상기 적층구조(Stacked Structure)는 핀 형상으로 형성된 핀(Fin)타입과, 실린더와 같이 원통형상으로 형성되는 실린더(Cylinder)타입 및 캐비티(Cavity)타입에 변형을 가미한 HSG(Hemispherical Shaped Grains) 및 벨로즈(Bellows) 등과 같은 변형 커패시터구조등으로 구성되어 커패시터의 충전용량을 증가시키는 노력이 이루어지고 있다.In particular, the stacked structure has a finned type formed in a pin shape, and a HSG (Hemispherical Shaped Grains) in which a deformation is applied to a cylinder type and a cavity type formed in a cylindrical shape such as a cylinder. And a modified capacitor structure such as bellows, etc., have been made to increase the charging capacity of the capacitor.
상기한 구조중에서 캐비티를 갖는 HSG타입은 커패시터의 전하저장전극에 전하저장홀을 형성하고, 그 전하저장홀의 주변에 실리콘을 원형의 돌기형상으로 형성하여 전하를 저장하기 위한 전극의 면적을 증가시키는 구조로서, 하부저장전극을 형성하기 위하여 폴리실리콘층의 상부면을 포토에칭공정으로 식각한 후 그 상부면에 입자의 성장 핵역할을 하는 씨드(Seed, 실리콘 원자임)를 형성하고, 그 후 어닐링공정으로 비정질폴리실리콘층의 실리콘을 표면으로 이동하도록 하여 실린더 형상의 전하저장홀의 벽면에 작은 그레인돌기를 형성하여 전하저장전극의 표면적을 증대시키도록 하였다.In the above-described structure, the HSG type having a cavity has a structure in which a charge storage hole is formed in the charge storage electrode of the capacitor, and silicon is formed in a circular protrusion shape around the charge storage hole to increase the area of the electrode for storing charge. As an example, in order to form a lower storage electrode, an upper surface of the polysilicon layer is etched by a photoetching process, and a seed (seed (silicon atom)), which serves as a growth nucleus of particles, is formed on the upper surface, and then an annealing process In order to move the silicon of the amorphous polysilicon layer to the surface to form a small grain projection on the wall surface of the cylindrical charge storage hole to increase the surface area of the charge storage electrode.
그런데, 상기한 종래의 방식은 코어산화막 상부면과 측면부분에 비정질실리콘층을 적층하여 식각으로 측벽부분의 전하저장전극(Side Wall Storage Electrode)을 형성하고 내부에 있는 코어산화막을 제거하므로 전하저장전극을 형성하게 되지만 전하저장전극의 내측벽 부분은 전하저장용 인-시튜(In-Situ) 도프트된 비정질실리콘 증착시 증착이 시작되는 박막 지역으로서 증착이 완료되는 박막 지역인 전하저장전극의 외측벽 부분보다 포스포러스 농도가 낮기 때문에 전하저장전극 표면에 씨드인 실리콘 원자를 흡착시켜 그레인돌기를 형성할 때 내벽면의 그레인 사이즈는 외벽면보다 크게 되어 양벽면의 그레인 사이즈가 균질하지 못하므로 전하의 저장용량을 극대화하지 못하는 문제점을 지니고 있었다.However, in the conventional method, a charge storage electrode is formed by stacking an amorphous silicon layer on an upper surface and a side portion of the core oxide film to form a side wall storage electrode by etching and removing the core oxide film therein. However, the inner wall portion of the charge storage electrode is a thin film region where deposition starts when the in-situ doped amorphous silicon is deposited, and the outer wall portion of the charge storage electrode, which is a thin film region where the deposition is completed, is formed. Since the phosphor concentration is lower, the grain size of the inner wall surface is larger than the outer wall surface when the seed particles are adsorbed on the surface of the charge storage electrode to form grain protrusions, so the grain size of both walls is not homogeneous. It had a problem that could not be maximized.
본 발명의 목적은 폴리실리콘층 및 코어산화막 상에 도핑된 제1비정질실리콘층을 통상적인 적층 두께보다 얇은 두께로 적층하고, 그 결과물 상에 도핑이 되지 않은 제2비정질실리콘층을 적층한 후 코어산화막을 식각으로 제거하여 전하저장전극을 형성하고, 연속하여 실리콘원자를 전하저장전극의 표면에 도포하여 성장시키므로 내,외벽면에 형성되는 그레인의 사이즈를 동일하게 형성하여 전하저장 효율을 증대시키는 것이 목적이다.An object of the present invention is to laminate the first amorphous silicon layer doped on the polysilicon layer and the core oxide layer to a thickness thinner than the conventional lamination thickness, and the second amorphous silicon layer which is not doped on the resultant is laminated Since the oxide film is removed by etching to form a charge storage electrode, and the silicon atoms are successively coated on the surface of the charge storage electrode to grow, forming the same grain size on the inner and outer walls to increase the charge storage efficiency. Purpose.
도 1 내지 도 6는 본 발명에 따른 커패시터의 전하저장전극 형성방법을 순차적으로 보인 도면이다.1 to 6 are views sequentially showing a method for forming a charge storage electrode of a capacitor according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 20 : 절연막10 semiconductor substrate 20 insulating film
30 : 폴리실리콘층 40 : 코어산화막30 polysilicon layer 40 core oxide film
50 : 제1비정질실리콘층 60 : 제2비정질실리콘층50: first amorphous silicon layer 60: second amorphous silicon layer
70 : 전하저장전극 80,85 : 내,외벽그레인70: charge storage electrode 80,85: inner and outer wall grain
이러한 목적은 커패시터의 전하저장전극을 형성하는 방법에서, 반도체기판상의 절연막에 폴리실리콘층 및 코어산화막을 적층한 후 상기 결과물 상에 인이 도핑된 제1비정질실리콘을 적층하는 단계와; 상기 단계 후 상기 제1비정질 실리콘층 상에 인이 도핑 되지 않은 제2비정질실리콘층을 적층하는 단계와; 상기 단계 후 상부로 노출된 코어산화막을 제거한 후 형성된 전하저장전극의 표면에 실리콘원자를 도포하여 내,외벽면에 그레인을 성장시키는 단계로 이루어진 커패시터의 전하저장전극 형성방법을 제공함으로써 달성된다.The object of the present invention is to provide a method for forming a charge storage electrode of a capacitor, comprising: laminating a polysilicon layer and a core oxide layer on an insulating film on a semiconductor substrate, and then laminating first amorphous silicon doped with phosphorus on the resultant; Depositing a second amorphous silicon layer that is not doped with phosphorus on the first amorphous silicon layer after the step; It is achieved by providing a method for forming a charge storage electrode of a capacitor consisting of growing a grain on the inner and outer walls by applying a silicon atom on the surface of the charge storage electrode formed after removing the core oxide film exposed to the upper part after the step.
그리고, 상기 제1비정질실리콘층을 증착할 때 저압화학기상증착법으로 530℃이하의 온도를 유지하여 SiH4또는 Si2H6가스와 동시에 PH3가스를 함께 주입하여 통상적인 적층 두께보다 50Å이상 얇게 증착하도록 한다.In addition, when depositing the first amorphous silicon layer by maintaining a temperature of less than 530 ℃ by a low-pressure chemical vapor deposition method by injecting PH 3 gas with SiH 4 or Si 2 H 6 gas at the same time thinner than the conventional thickness of 50Å thinner than To be deposited.
또한, 상기 제2비정질실리콘층은 PH3가스의 주입을 중단하고, SiH4또는 Si2H6가스만을 주입하도록 하여 상기 제1비정질실리콘층을 통상적인 적층 두께보다 50Å이상 얇게 증착한 부분을 보충하는 두께로 적층하도록 한다.In addition, the second amorphous silicon layer stops the injection of PH 3 gas and injects only SiH 4 or Si 2 H 6 gas to supplement a portion in which the first amorphous silicon layer is deposited at a thickness of 50 kPa or more or less than a normal lamination thickness. Laminate to thickness.
한편, 상기 도핑된 제1비정질실리콘층의 인의 도핑 농도를 1.5×1020atoms/cm2이하로 조절하도록 한다.Meanwhile, the doping concentration of phosphorus in the doped first amorphous silicon layer is adjusted to 1.5 × 10 20 atoms / cm 2 or less.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 1은 반도체기판(10)상의 절연막(20)에 폴리실리콘층(30) 및 코어산화막(40)을 적층한 후 식각으로 전하저장전극의 형성부위를 제외한 부위의 나머지 부분을 제거하는 상태를 도시하고 있다.FIG. 1 illustrates a state in which a polysilicon layer 30 and a core oxide film 40 are stacked on an insulating film 20 on a semiconductor substrate 10, and then the remaining portions of portions except for the formation of charge storage electrodes are removed by etching. Doing.
도 2는 상기 상기 결과물 상에 도핑이 된 제1비정질실리콘을 적층하는 상태를 도시하고 있는 것으로서, 상기 제1비정질실리콘층을 증착할 때 저압화학기상증착법(Low Pressure Chemical Vapor Deposition; LPCVD)으로 530℃이하의 온도를 유지하여 SiH4또는 Si2H6가스와 동시에 PH3가스를 함께 주입하여 통상적인 적층 두께보다 50Å이상 얇게 증착하도록 한다.FIG. 2 illustrates a state in which a doped first amorphous silicon is laminated on the resultant, and is 530 by Low Pressure Chemical Vapor Deposition (LPCVD) when the first amorphous silicon layer is deposited. Maintaining the temperature below ℃ to inject the PH 3 gas together with SiH 4 or Si 2 H 6 gas at the same time to deposit more than 50Å thinner than the conventional lamination thickness.
이때, 제1비정질실리콘층(50)의 인의 체적농도를 1.5×1020atoms/cm3이하로 조절하도록 한다.At this time, the volume concentration of phosphorus in the first amorphous silicon layer 50 is adjusted to 1.5 × 10 20 atoms / cm 3 or less.
그리고, 도 3은 상기 단계 후 상기 제1비정질 실리콘층 상에 도핑이 되지 않은 제2비정질실리콘층을 적층하는 상태를 도시한 것으로서, 제2비정질실리콘층은 PH3가스의 주입을 중단하고, SiH4또는 Si2H6가스만을 주입하도록 하여 상기 제1비정질실리콘층을 통상적인 적층 두께보다 50Å이상 얇게 증착한 부분을 보충하는 두께로 적층하도록 한다.3 illustrates a state in which a second doped non-doped silicon layer is deposited on the first amorphous silicon layer after the step, in which the second amorphous silicon layer stops the injection of PH 3 gas, and the SiH Only the 4 or Si 2 H 6 gas is injected to stack the first amorphous silicon layer to a thickness that supplements the deposited portion that is 50 Å thinner than the conventional stacking thickness.
도 4는 상기 제1,제2비정질실리콘층(50)(60)을 식각하여서 상부면을 노출하도록 하는 상태를 도시하고 있는 도면이다.FIG. 4 illustrates a state in which the first and second amorphous silicon layers 50 and 60 are etched to expose the upper surface.
도 5는 상기 단계 후 상부로 노출된 코어산화막(40)을 제거한 상태를 도시하는 도면이다.5 is a view showing a state in which the core oxide film 40 exposed to the upper part after the step is removed.
도 6은 상기 전하저장전극(70)의 표면에 실리콘(Si)원자를 도포하여 어닐링공정으로 비정질실리콘층(50)(60)에 있는 실리콘을 표면으로 이동시켜, 전하저장전극(70)의 내,외벽면에 그레인(Grain)을 성장시키는 상태를 도시하고 있다.FIG. 6 shows that silicon (Si) atoms are applied to the surface of the charge storage electrode 70 to transfer silicon in the amorphous silicon layers 50 and 60 to the surface of the charge storage electrode 70 by annealing. The state which grows grain on the outer wall surface is shown.
이때, 상기 전하저장전극(70)은 제1비정질실리콘층(50)의 외측면에 제2비정질실리콘층(60)이 겹쳐 형성되는 것으로, 제1비정질실리콘층(50)에 많이 함유되어진 인(Phosphorous)이 별로 함유되지 않은 제2비정질실리콘층(60)에서 차단하는 역할을 하므로 결국에는 전하저장전극(70)의 내,외벽면의 인의 농도를 거의 같도록 하게 되어 내,외벽면에 형성되는 내,외벽그레인(80)(85)의 사이즈를 동일하게 유지하도록 한다.At this time, the charge storage electrode 70 is formed by overlapping the second amorphous silicon layer 60 on the outer surface of the first amorphous silicon layer 50, the phosphorus (a large amount of phosphorus (1) Phosphorous) serves to block in the second amorphous silicon layer 60, which does not contain much, so that the concentration of phosphorus in the inner and outer walls of the charge storage electrode 70 is almost the same, which is formed on the inner and outer walls. The size of the inner and outer wall grains 80 and 85 is kept the same.
상기한 바와 같이, 본 발명에 따른 커패시터 전하저장전극형성방법을 이용하게 되면, 폴리실리콘층 및 코어산화막 상에 도핑된 제1비정질실리콘층을 통상적인 적층 두께보다 얇은 두께로 적층하고, 그 결과물 상에 도핑이 되지 않은 제2비정질실리콘층을 적층한 후 코어산화막을 식각으로 제거하여 전하저장전극을 형성하고, 연속하여 실리콘원자를 전하저장전극의 표면에 도포하여 성장시키므로 내,외벽면의 인의 농도를 내,외벽면에 형성되는 그레인의 사이즈를 거의 동일하게 형성하여 전하저장 효율을 증대시키도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the capacitor charge storage electrode forming method according to the present invention is used, the first amorphous silicon layer doped on the polysilicon layer and the core oxide layer is laminated to a thickness thinner than the conventional lamination thickness, and the resultant phase After stacking the second amorphous silicon layer which is not doped, the core oxide film is etched to form a charge storage electrode, and silicon atoms are successively coated on the surface of the charge storage electrode to grow. It is a very useful and effective invention to increase the charge storage efficiency by forming almost the same size of the grains formed on the inner, outer wall surface.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980058886A KR100334960B1 (en) | 1998-12-26 | 1998-12-26 | Method for forming charge storage electrode of capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980058886A KR100334960B1 (en) | 1998-12-26 | 1998-12-26 | Method for forming charge storage electrode of capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010008411A KR20010008411A (en) | 2001-02-05 |
| KR100334960B1 true KR100334960B1 (en) | 2002-06-20 |
Family
ID=19565892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980058886A KR100334960B1 (en) | 1998-12-26 | 1998-12-26 | Method for forming charge storage electrode of capacitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100334960B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100713901B1 (en) * | 2001-06-27 | 2007-05-07 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505441B1 (en) | 2003-04-04 | 2005-08-05 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950028151A (en) * | 1994-03-22 | 1995-10-18 | 김주용 | Method for forming charge storage electrode of memory device |
| KR970024150A (en) * | 1995-10-24 | 1997-05-30 | 김광호 | Capacitor Manufacturing Method of Semiconductor Device |
| JPH1022474A (en) * | 1996-07-05 | 1998-01-23 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| KR19980048860A (en) * | 1996-12-18 | 1998-09-15 | 김광호 | Capacitor Manufacturing Method of Semiconductor Device |
| JPH10335607A (en) * | 1997-06-05 | 1998-12-18 | Nec Corp | Manufacture of semiconductor device |
-
1998
- 1998-12-26 KR KR1019980058886A patent/KR100334960B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950028151A (en) * | 1994-03-22 | 1995-10-18 | 김주용 | Method for forming charge storage electrode of memory device |
| KR970024150A (en) * | 1995-10-24 | 1997-05-30 | 김광호 | Capacitor Manufacturing Method of Semiconductor Device |
| JPH1022474A (en) * | 1996-07-05 | 1998-01-23 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| KR19980048860A (en) * | 1996-12-18 | 1998-09-15 | 김광호 | Capacitor Manufacturing Method of Semiconductor Device |
| JPH10335607A (en) * | 1997-06-05 | 1998-12-18 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100713901B1 (en) * | 2001-06-27 | 2007-05-07 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010008411A (en) | 2001-02-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6103570A (en) | Method of forming capacitors having an amorphous electrically conductive layer | |
| EP1306889B1 (en) | Electronic device with electrode and its manufacture | |
| US7741671B2 (en) | Capacitor for a semiconductor device and manufacturing method thereof | |
| US6165837A (en) | Semiconductor integrated memory manufacturing method and device | |
| WO1999004434A2 (en) | Hemispherical grained polysilicon semiconductor capacitor structure and method | |
| KR100400246B1 (en) | Method for forming of capacitor the cell used high-integrated DRAM | |
| KR100323832B1 (en) | Method for manufacturing capacitor having high storage capacitance and method for fabricating semiconductor device using the same | |
| EP0521676A1 (en) | Thin-film capacitor in semiconductor integrated circuit device, and method of manufacture thereof | |
| US5104821A (en) | Method for fabricating stacked capacitors in a DRAM cell | |
| US7030442B2 (en) | Stack-film trench capacitor and method for manufacturing the same | |
| KR100334960B1 (en) | Method for forming charge storage electrode of capacitor | |
| KR100213189B1 (en) | Semiconductor memory device and its fabrication method | |
| US6653185B2 (en) | Method of providing trench walls by using two-step etching processes | |
| US6162680A (en) | Method for forming a DRAM capacitor | |
| CN1773710A (en) | Stacked capacitor and producing method thereof | |
| TW526609B (en) | Electrode-arrangement for charge-storage and its production method | |
| KR100331268B1 (en) | Method For Forming The Charge Storage Electrode Of Capacitor | |
| US6204121B1 (en) | Method for bottom electrode of capacitor | |
| TW417291B (en) | Manufacture method of crown-type DRAM capacitor | |
| KR910002306B1 (en) | Method for production of dram | |
| KR20010008409A (en) | Method for forming lower electrode of capacitor | |
| KR100224693B1 (en) | Capacitor manufacturing method of semiconductor memory device | |
| JPH03278566A (en) | Manufacture of semiconductor device | |
| KR100269607B1 (en) | Capacitor Formation Method | |
| KR960005565B1 (en) | Semiconductor memory device and the manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100325 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |