KR950015070A - 메모리어레이를 사용한 병렬연산장치 - Google Patents

메모리어레이를 사용한 병렬연산장치 Download PDF

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KR950015070A
KR950015070A KR1019940029042A KR19940029042A KR950015070A KR 950015070 A KR950015070 A KR 950015070A KR 1019940029042 A KR1019940029042 A KR 1019940029042A KR 19940029042 A KR19940029042 A KR 19940029042A KR 950015070 A KR950015070 A KR 950015070A
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parallel
data
memory array
dimensional memory
arithmetic
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KR1019940029042A
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KR100330604B1 (ko
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다까오 와따나베
데쯔야 나까가와
요시노부 나까고메
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가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Computing Systems (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)

Abstract

메모리어레이를 사용한 병렬연산장치에 관한 것으로써, 병렬연산장치가 문제에 따서 SIMD동작 또는 MIMD동작을 전환해서 병렬연산을 고속으로 실행하고, 또 SIMD동작과 MIMD동작이 혼재한 처리를 실행하는 경우에도 동작의 전환에 따르는 시간적인 손실을 없애서 고속의 처리를 실행할 수 있게 하기, 연산을 위한 데이타를 기억하는 2차원 메모리어레이 MAR, 2차원 메모리어레이에서 병렬로 리드한 워드선상의 메모리셀의 데이타를 연산회로군으로 전송하는 전송네트워크TN, 전송된 데이타를 사용해서 연산처리를 병렬로 실행하는 연산회로군PEI∼PEn, SIMD동작시의 명령OP-5를 전달하는 신호선LS, MIMD동작시의 명령 OP-m을 축적하여 병렬로 전달하는 명령버퍼 BAF 및 SIMD동작과 MIMD동작을 전환하기 위한 스위치군SW-OP를 구비한다. 이러한 장치를 이용하는 것에 의해, 병렬연산을 고속으로 실행할 수 있다.

Description

메모리어레이를 사용한 병렬연산장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1의 실시예를 도시한 메모리베이스의 병렬연산칩의 구성도.

Claims (3)

  1. 반도체기판상에 형성된 병렬연산장치에 있어서, 연산을 위한 데이타를 기억하는 2차원 메모리어레이와 상기 2차원 메모리어레이에서 병렬로 리드한 워드선상의 메모리셀의 데이타를 전송하는 전송네트워크, 다른곳에서 전송된 데이타를 사용해서 연산처리를 병렬로 실행하는 연산회로군 및 상기 연산회로군을 공통의 명령으로 병렬로 동작시키는 제1의 동작모드와 각각의 연산회로마다 다른 명령으로 병렬로 동작시키는 제2의 동작모드를 전환하는 신호에 의해 상기 양 명령을 고속으로 전환하는 전환수단을 포함하는 병렬 연산장치.
  2. 제1항에 있어서, 상기 제2의 동작모드중에 상기 연산회로군으로 병렬로 공급하는 동일 또는 다른 명령을 다수 기억하는 명령버퍼를 또 포함하며, 상기 명령버퍼는 상기 제1의 동작모드중에 상기 다수의 명령을 라이트하는 병렬연산장치.
  3. 반도체기판상에 형성된 병렬연산장치에 있어서, 연산을 위한 데이타를 기억하는 2차원 메모리어레이, 상기 2차원 메모리어레이에서 병렬로 리드한 워드선산의 메모리셀의 데이타를 전송하는 전송네트워크 및 상기 데이타와 다른 곳에서 전송된 데이타를 사용해서 연산터리를 병렬로 실행하는 연산회로군 을 포함하며, 상기 2차원 메모리어레이는 적어도 1화면이상의 화상데이타를 기억할 수 있고, 상기 연산회로는 상기 화상데이타와 다른 곳에서 전송된 화상데이타에 대해서 α블랜딩처리를 실행하는 기능 및 상기 화상데이타의 Z값과 다른 곳에서 전송된 화상데이타의 Z값의 비교를 실행하는 기능을 구비한 병렬 연산장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940029042A 1993-11-19 1994-11-07 메모리어레이를사용한병렬연산장치 KR100330604B1 (ko)

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JP29046893A JP3199205B2 (ja) 1993-11-19 1993-11-19 並列演算装置
JP93-290468 1993-11-19

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US5535410A (en) 1996-07-09
JP3199205B2 (ja) 2001-08-13
KR100330604B1 (ko) 2002-08-24

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