KR950012716A - 집적회로 제조방법 및 반도체 집적회로 - Google Patents

집적회로 제조방법 및 반도체 집적회로 Download PDF

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Publication number
KR950012716A
KR950012716A KR1019940027825A KR19940027825A KR950012716A KR 950012716 A KR950012716 A KR 950012716A KR 1019940027825 A KR1019940027825 A KR 1019940027825A KR 19940027825 A KR19940027825 A KR 19940027825A KR 950012716 A KR950012716 A KR 950012716A
Authority
KR
South Korea
Prior art keywords
tub
integrated circuit
conductor
gates
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1019940027825A
Other languages
English (en)
Korean (ko)
Inventor
리 쿠오-후아
린 호릉-다르
얀 랜-홍
더그라스 유 첸-후아
Original Assignee
제이.티. 레흐버그
에이 티 앤드 티 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 제이.티. 레흐버그, 에이 티 앤드 티 코포레이션 filed Critical 제이.티. 레흐버그
Publication of KR950012716A publication Critical patent/KR950012716A/ko
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1019940027825A 1993-10-29 1994-10-28 집적회로 제조방법 및 반도체 집적회로 Ceased KR950012716A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US145,272 1993-10-29
US08/145,272 US5468669A (en) 1993-10-29 1993-10-29 Integrated circuit fabrication

Publications (1)

Publication Number Publication Date
KR950012716A true KR950012716A (ko) 1995-05-16

Family

ID=22512350

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940027825A Ceased KR950012716A (ko) 1993-10-29 1994-10-28 집적회로 제조방법 및 반도체 집적회로

Country Status (5)

Country Link
US (1) US5468669A (cg-RX-API-DMAC7.html)
EP (1) EP0660394A1 (cg-RX-API-DMAC7.html)
JP (1) JPH07176626A (cg-RX-API-DMAC7.html)
KR (1) KR950012716A (cg-RX-API-DMAC7.html)
TW (1) TW286424B (cg-RX-API-DMAC7.html)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550079A (en) * 1995-06-15 1996-08-27 Top Team/Microelectronics Corp. Method for fabricating silicide shunt of dual-gate CMOS device
DE19525069C1 (de) * 1995-07-10 1996-10-24 Siemens Ag Verfahren zur Herstellung einer integrierten CMOS-Schaltung
DE19535629C1 (de) * 1995-09-25 1996-09-12 Siemens Ag Verfahren zur Herstellung einer integrierten CMOS-Schaltung
US5759886A (en) * 1995-09-28 1998-06-02 National Semiconductor Corporation Method for forming a layer of metal silicide over the gates of a surface-channel CMOS device
US6150247A (en) * 1996-03-19 2000-11-21 Vanguard International Semiconductor Corporation Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits
KR100240615B1 (ko) 1997-03-13 2000-01-15 김영환 반도체장치의제조방법
KR100268920B1 (ko) * 1997-04-21 2000-12-01 김영환 반도체소자의제조방법
JP3606515B2 (ja) 2000-09-05 2005-01-05 沖電気工業株式会社 デュアルゲート型ｃｍｏｓ半導体装置及びその製造方法
JP2002217310A (ja) * 2001-01-18 2002-08-02 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2005167116A (ja) * 2003-12-05 2005-06-23 Nec Electronics Corp 半導体装置及びその製造方法
US7737500B2 (en) * 2006-04-26 2010-06-15 International Business Machines Corporation CMOS diodes with dual gate conductors, and methods for forming the same
JP4996890B2 (ja) * 2006-07-31 2012-08-08 富士通セミコンダクター株式会社 半導体装置の製造方法
CN104103588B (zh) * 2013-04-10 2017-02-15 上海华虹宏力半导体制造有限公司 Cmos器件的制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582068A (ja) * 1981-06-26 1983-01-07 Toshiba Corp 半導体装置およびその製造方法
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
US4463491A (en) * 1982-04-23 1984-08-07 Gte Laboratories Incorporated Method of fabricating a monolithic integrated circuit structure
US4555842A (en) * 1984-03-19 1985-12-03 At&T Bell Laboratories Method of fabricating VLSI CMOS devices having complementary threshold voltages
US4931411A (en) * 1985-05-01 1990-06-05 Texas Instruments Incorporated Integrated circuit process with TiN-gate transistor
JPH0666437B2 (ja) * 1987-11-17 1994-08-24 富士通株式会社 半導体記憶装置及びその製造方法
JPH01265542A (ja) * 1988-04-15 1989-10-23 Toshiba Corp 半導体装置
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
JPH0613472A (ja) * 1992-06-29 1994-01-21 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
TW286424B (cg-RX-API-DMAC7.html) 1996-09-21
JPH07176626A (ja) 1995-07-14
US5468669A (en) 1995-11-21
EP0660394A1 (en) 1995-06-28

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