KR940016921A - 포토 레지스트를 이용한 엘디디(ldd) 구조 형성 공정 - Google Patents
포토 레지스트를 이용한 엘디디(ldd) 구조 형성 공정 Download PDFInfo
- Publication number
- KR940016921A KR940016921A KR1019920026875A KR920026875A KR940016921A KR 940016921 A KR940016921 A KR 940016921A KR 1019920026875 A KR1019920026875 A KR 1019920026875A KR 920026875 A KR920026875 A KR 920026875A KR 940016921 A KR940016921 A KR 940016921A
- Authority
- KR
- South Korea
- Prior art keywords
- photoresist
- low concentration
- impurity region
- impurity
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 title claims abstract 21
- 230000015572 biosynthetic process Effects 0.000 title abstract 2
- 239000012535 impurity Substances 0.000 claims abstract 16
- 239000000758 substrate Substances 0.000 claims abstract 3
- 238000002513 implantation Methods 0.000 abstract 2
- 230000007547 defect Effects 0.000 abstract 1
- 239000010419 fine particle Substances 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (2)
- 포토 레지스트를 이용한 LDD(Lightly-doped Drain) 구조 형성 공정에 있어서, MOS 패턴 형성을 위해, 기판(11)에 필드 산화막(12)과 게이트 산화막(13)을 형성하고, 그위에 게이트 전극(14)을 형성하는 제 1 단계와, 포토 레지스트를 도포한 다음, 마스크를 사용하여, 게이트 전극(14) 주위로 저농도(N-) 불순물 영역이 형성될 부분될 부분을 제외한 나머지 부분의 포토 레지스트(15)가 남게 하도록 현상하는 제 2 단계와, 저농도(N-) 불순물 영역(16)을 형성하기 위해, N-불순물을 주입하는 제 3 단계와, 상기 포토 레지스트(15)를 제거하는 제 4 단계와, 포토 레지스트를 전체에 걸쳐 도포한 후 마스크를 사용하여 저농도(N-) 불순물 영역(16)과 게이트 전극(14) 상의 포토 레지스트만 남도록 현상하는 제 5 단계와, 상기 저농도 불순물 영역(16) 주위에 고농도(N+) 불순물 영역(18)을 형성하기 위해, N+ 불순물을 주입하는 제 6 단계 및, 포토레지스트(17)을 제거하는 제 7 단계를 포함하는 것을 특징으로 하는 LDD 구조 형성 공정.
- 제 1 항에 있어서, 포지티브 포토 레지스트 또는 네가티브 포토 레지스트를 선택적으로 사용하여, 상기 제 2 단계 및 제 5 단계를 하나의 마스크를 이용하여 수행하는 것을 특징으로 하는 LDD 구조 형성 공정.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920026875A KR960000228B1 (ko) | 1992-12-30 | 1992-12-30 | 포토 레지스트를 이용한 엘디디(ldd) 구조 형성 공정 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920026875A KR960000228B1 (ko) | 1992-12-30 | 1992-12-30 | 포토 레지스트를 이용한 엘디디(ldd) 구조 형성 공정 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940016921A true KR940016921A (ko) | 1994-07-25 |
KR960000228B1 KR960000228B1 (ko) | 1996-01-03 |
Family
ID=19348026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920026875A Expired - Fee Related KR960000228B1 (ko) | 1992-12-30 | 1992-12-30 | 포토 레지스트를 이용한 엘디디(ldd) 구조 형성 공정 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960000228B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8004023B2 (en) | 2007-01-26 | 2011-08-23 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
-
1992
- 1992-12-30 KR KR1019920026875A patent/KR960000228B1/ko not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8004023B2 (en) | 2007-01-26 | 2011-08-23 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
KR960000228B1 (ko) | 1996-01-03 |
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Comment text: Decision on Publication of Application Patent event code: PG16051S01I Patent event date: 19951129 |
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Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19960329 |
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Comment text: Registration of Establishment Patent event date: 19960531 Patent event code: PR07011E01D |
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