KR920015604A - 반도체장치의 소자격리방법 - Google Patents

반도체장치의 소자격리방법 Download PDF

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Publication number
KR920015604A
KR920015604A KR1019910000641A KR910000641A KR920015604A KR 920015604 A KR920015604 A KR 920015604A KR 1019910000641 A KR1019910000641 A KR 1019910000641A KR 910000641 A KR910000641 A KR 910000641A KR 920015604 A KR920015604 A KR 920015604A
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KR
South Korea
Prior art keywords
nitride film
isolation method
semiconductor device
forming
sidewall
Prior art date
Application number
KR1019910000641A
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English (en)
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KR950007397B1 (ko
Inventor
박준영
김영기
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000641A priority Critical patent/KR950007397B1/ko
Publication of KR920015604A publication Critical patent/KR920015604A/ko
Application granted granted Critical
Publication of KR950007397B1 publication Critical patent/KR950007397B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

내용 없음

Description

반도체장치의 소자격리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 (a)-(d)는 본 발명의 1실시예 따른 제조공정도이다.

Claims (2)

  1. 반도체 기판상에 산화막, 질화막을 차례로 도포하고 필드영역의 질화막만 제거하는 공정과, 상기 질화막의 측면에 산화막으로 완충용 측벽을 형성한 후 노출된 상기 산화막 양단의 제한된 부분에 고농도 불순물을 이온주입하는 공정과, 상기 완충용 측벽상에 질화막으로된 질화막 측벽을 형성하는 공정과, 필드영역에 필드산화막을 형성하는 공정으로 이루어진 반도체 장치의 소자격리방법.
  2. 제1항에 있어서, 상기이온주입공정은 n+형 불순물, 20-30KeV의 에너지, e16/㎠까지의 도즈량으로 실행함을 특징으로 하는 반도체 장치의 소자격리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910000641A 1991-01-16 1991-01-16 반도체 장치의 소자격리 방법 KR950007397B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000641A KR950007397B1 (ko) 1991-01-16 1991-01-16 반도체 장치의 소자격리 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000641A KR950007397B1 (ko) 1991-01-16 1991-01-16 반도체 장치의 소자격리 방법

Publications (2)

Publication Number Publication Date
KR920015604A true KR920015604A (ko) 1992-08-27
KR950007397B1 KR950007397B1 (ko) 1995-07-10

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ID=19309896

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000641A KR950007397B1 (ko) 1991-01-16 1991-01-16 반도체 장치의 소자격리 방법

Country Status (1)

Country Link
KR (1) KR950007397B1 (ko)

Also Published As

Publication number Publication date
KR950007397B1 (ko) 1995-07-10

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