KR940016879A - Method for forming self-aligned contact of semiconductor device - Google Patents

Method for forming self-aligned contact of semiconductor device Download PDF

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Publication number
KR940016879A
KR940016879A KR1019920026717A KR920026717A KR940016879A KR 940016879 A KR940016879 A KR 940016879A KR 1019920026717 A KR1019920026717 A KR 1019920026717A KR 920026717 A KR920026717 A KR 920026717A KR 940016879 A KR940016879 A KR 940016879A
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KR
South Korea
Prior art keywords
forming
etching
wet etching
semiconductor device
film
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Application number
KR1019920026717A
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Korean (ko)
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KR960004086B1 (en
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박해성
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR92026717A priority Critical patent/KR960004086B1/en
Publication of KR940016879A publication Critical patent/KR940016879A/en
Application granted granted Critical
Publication of KR960004086B1 publication Critical patent/KR960004086B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 자기정렬콘택 형성방법에 관한 것으로 습식식각과 건식식각으로 콘택홀을 형성할 경우 습식식각의 언더컷으로 인하여 발생하는 누설전류를 방지하기 위하여 식각해야 하는 산화막을 2회에 나누어서 건식식각과 습식식각방법을 적용하여 먼저 건식식각후에 건식식각으로 형성된 측벽에 질화막을 구성하여 후속산화막 습식식각시 언더컷을 방지하여 소자의 신뢰성을 증가시키는 반도체 소자의 자기정렬콘택 형성방법이다.The present invention relates to a method of forming a self-aligned contact of a semiconductor device, when forming a contact hole by wet etching and dry etching, dry the oxide film to be etched in two times to prevent leakage current caused by undercut of wet etching. It is a method of forming a self-aligned contact of a semiconductor device to increase the reliability of the device by preventing the undercut during the subsequent oxide wet etching by forming a nitride film on the sidewall formed by dry etching after the dry etching by applying the etching and wet etching method.

Description

반도체 소자의 자기정렬콘택 형성방법Method for forming self-aligned contact of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2F도는 본 발명에 의한 자기정렬콘택 형성방법을 나타낸 단면도.2A to 2F are cross-sectional views showing a method for forming a self-aligned contact according to the present invention.

Claims (4)

반도체 소자의 자기정렬콘택 형성방법에 있어서, 실리콘기판에 게이트전극을 형성한후 그 상부에 제 1 질화막, 산화막, 폴리실리콘막을 적층하고 콘택마스크를 형성하는 단계와, 콘택마스크를 이용하여 폴리실리콘과 산화막을 식각하되 게이트전극 사이의 콘택홀이 형성되는 단차부분의 산화막의 일부분이 남도록하고 마스크를 제거한후 다시 그 상부에 제 2 질화막을 적층하는 단계와, 블랭킷 식각으로 제 2 질화막을 산화막 측벽에만 남긴후 습식식각으로 단차부분의 남아있는 산화막을 제거하는 단계와, 다시 습식식각으로 제 1 질화막과 제 2 질화막을 제거하여 콘택홀을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 자기정렬 콘택 형성방법.A method of forming a self-aligned contact of a semiconductor device, comprising: forming a gate electrode on a silicon substrate, and then laminating a first nitride film, an oxide film, and a polysilicon film on the silicon substrate, and forming a contact mask; Etching the oxide layer, leaving a portion of the oxide layer in the stepped portion where the contact hole is formed between the gate electrodes, removing the mask, and stacking the second nitride layer on top of the oxide layer; and leaving the second nitride layer only on the oxide sidewall by blanket etching. And removing the remaining oxide film of the stepped portion by wet etching, and then removing the first nitride film and the second nitride film by wet etching to form contact holes. . 제 1 항에 있어서, 콘택홀 형성시 습식식각으로 남아있는 산화막 제거로 건식식각으로 제 1 질화막을 제거하는 것을 포함하는 반도체 소자의 자기정렬콘택 형성방법.The method of claim 1, further comprising removing the first nitride layer by dry etching by removing the oxide layer remaining by wet etching when forming the contact hole. 제 1 항에 있어서, 제 2 질화막 두께는 500Å 이하가 되도록 하는 것을 특징으로 하는 반도체소자의 자기정렬콘택 형성방법.The method of claim 1, wherein the thickness of the second nitride film is 500 kPa or less. 제 1 항에 있어서, 제 2 질화막 대신 폴리실리콘을 적층하는 것을 특징으로 하는 반도체 소자의 자기정렬콘택 형성방법.2. The method of claim 1, wherein polysilicon is laminated instead of the second nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR92026717A 1992-12-30 1992-12-30 Forming method of self aligned contact for semiconductor device KR960004086B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92026717A KR960004086B1 (en) 1992-12-30 1992-12-30 Forming method of self aligned contact for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92026717A KR960004086B1 (en) 1992-12-30 1992-12-30 Forming method of self aligned contact for semiconductor device

Publications (2)

Publication Number Publication Date
KR940016879A true KR940016879A (en) 1994-07-25
KR960004086B1 KR960004086B1 (en) 1996-03-26

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KR92026717A KR960004086B1 (en) 1992-12-30 1992-12-30 Forming method of self aligned contact for semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100400298B1 (en) * 1999-06-11 2003-10-04 주식회사 하이닉스반도체 A method of manufacturing self align contact of semiconductor device
US7199433B2 (en) 1995-07-18 2007-04-03 Renesas Technology Corp. Method of manufacturing semiconductor integrated circuit device having capacitor element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7199433B2 (en) 1995-07-18 2007-04-03 Renesas Technology Corp. Method of manufacturing semiconductor integrated circuit device having capacitor element
US7323735B2 (en) 1995-07-18 2008-01-29 Renesas Technology Corp. Method of manufacturing semiconductor integrated circuit device having capacitor element
US7598558B2 (en) 1995-07-18 2009-10-06 Renesas Technology Corp. Method of manufacturing semiconductor integrated circuit device having capacitor element
KR100400298B1 (en) * 1999-06-11 2003-10-04 주식회사 하이닉스반도체 A method of manufacturing self align contact of semiconductor device

Also Published As

Publication number Publication date
KR960004086B1 (en) 1996-03-26

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