KR940016832A

KR940016832A - New capacitor manufacturing method of semiconductor device

Info

Publication number: KR940016832A
Application number: KR1019920026901A
Authority: KR
Inventors: 최양규
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1992-12-30
Filing date: 1992-12-30
Publication date: 1994-07-25

Abstract

본 발명은 반도체 소자의 새로운 축전기 제조 방법에 관한 것으로, 축전기 콘택홀(4)을 형성하고 도전체 다결정 실리콘(9)을 입힌 후 습식 식각비가 차이가 많이 나는 산화절연막(3)을 적층하는 제 1 공정, 상기 제 1 공정 후, 축전기 콘택홀(4) 마스크를 이용하여 습식식각비가 차이가 많이 나는 산화절연막(3)을 건식식각으로 형성하는 제 2 공정, 상기 제 2 공정 후, 습식식각으로 서로 다른 식각비를 이용하여 요철 패턴을 형성하는 제 3 공정, 상기 제 3 공정 후, 도전체 다결정 실리콘(9)을 입힌 후, 축전기 마스크를 이용하여 도전체 다결정 실리콘(9)을 건식 식각하고 차례차례 적층 산화절연막(3)을 건식 식각하고 축전기 콘택홀(4)을 채우고 있는 도전체 다결정 실리콘(9)을 식각하는 제 4 공정, 상기 제 4 공정 후, 형성되어 있는 패턴에 습식식각으로 적층 산화막(7, 8)을 습식식각한 후 축전기 유전체를 형성하고 축전기 플레이트(11)를 입히는 제 5 공정으로 이루어지는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a new capacitor of a semiconductor device, comprising: forming a capacitor contact hole (4), coating a conductive polycrystalline silicon (9), and stacking an oxide insulating film (3) having a large wet etching ratio After the first step, the second step of forming a dry etching of the oxide insulating film (3) having a large difference in wet etching ratio by using the capacitor contact hole (4) mask, and after the second step, each other by wet etching After the third process and the third process of forming the uneven pattern using different etching ratios, the conductor polycrystalline silicon 9 is coated, and then the conductor polycrystalline silicon 9 is dry-etched using a capacitor mask and sequentially A fourth step of dry etching the laminated oxide insulating film 3 and etching the conductor polycrystalline silicon 9 filling the capacitor contact hole 4, and after the fourth step, the stacked acid is wet-etched on the formed pattern. A membrane (7, 8) characterized by comprising a fifth step to form a wet etch after the capacitor dielectric and a capacitor plate coated 11.

Description

New capacitor manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명인 축전기 소자의 단면도, 제 2 도는 본 발명에 따른 실시예시 단면도.1 is a cross-sectional view of a capacitor element of the present invention, 2 is a cross-sectional view of an embodiment according to the present invention.

Claims

A first step of forming a capacitor contact hole 4 and coating a conductive polycrystalline silicon 9 and then stacking an oxide insulating film 3 having a large wet etching ratio, and after the first step, the capacitor contact hole 4 A second process of forming an oxide insulating film 3 having a large wet etching ratio by dry etching using a mask, and a third process of forming an uneven pattern by using different etching ratios by wet etching after the second process After the third process, the conductive polycrystalline silicon 9 is coated, followed by dry etching of the conductive polycrystalline silicon 9 using a capacitor mask, followed by dry etching of the laminated oxide insulating film 3, and then the capacitor contact hole ( 4) After the fourth process of etching the conductive polycrystalline silicon (9) filled, after the fourth process, wet etching the laminated oxide films (7, 8) by wet etching on the formed pattern, and then forming a capacitor dielectric Capacitor play A new capacitor manufacturing method of a semiconductor device, characterized by comprising a fifth step of coating the sheet (11).

The method of manufacturing a new capacitor of a semiconductor device according to claim 1, further comprising a third step of forming said capacitor polycrystalline silicon (5) after said second step to make said capacitor polycrystalline silicon (6).

※ Note: The disclosure is based on the initial application.