KR930006943A - Double Capacitor Manufacturing Method - Google Patents

Double Capacitor Manufacturing Method Download PDF

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Publication number
KR930006943A
KR930006943A KR1019910016076A KR910016076A KR930006943A KR 930006943 A KR930006943 A KR 930006943A KR 1019910016076 A KR1019910016076 A KR 1019910016076A KR 910016076 A KR910016076 A KR 910016076A KR 930006943 A KR930006943 A KR 930006943A
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KR
South Korea
Prior art keywords
forming
node
capacitor
polysilicon
depositing
Prior art date
Application number
KR1019910016076A
Other languages
Korean (ko)
Other versions
KR940009618B1 (en
Inventor
김홍선
Original Assignee
문정환
금성일렉트론 주식회사
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910016076A priority Critical patent/KR940009618B1/en
Publication of KR930006943A publication Critical patent/KR930006943A/en
Application granted granted Critical
Publication of KR940009618B1 publication Critical patent/KR940009618B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 이중 캐패시터 제조방법에 관한 것으로, 특히 스택 셀에서 캐패시터 면적을 증가시키며 안정된 공정으로 셀 구조를 형성시킬 수 있도록 한 캐패시터 제조방법에 관한 것이다. 이를 위하여 본 발명에서는, 이중 캐패시터 제조방법에 있어서, 실리콘 기판위에 필드 산화막 및 게이트를 형성한 다음 비트라인, 비트라인 절연막을 형성하는 단계와, 제1플레이트 폴리 실리콘을 입힌 후 평탄화 작업을 하고 산화막을 증착시키는 단계와, 제1노드 콘택을 형성하고 제1캐패시터 유전체를 형성시키는 단계와, 제2노드 폴리 실리콘을 증착시켜 제1노드 폴리실리콘과 연결시키는 단계와, 포토 레지스트로 평탄화시키고 상기 제1노드 폴리 실리콘 및 제2노드 폴리실리콘을 식각하는 단계와, 포토 레지스트를 스트립한 후 제2캐패시터 유전체를 형성하고 캐패시터 플레이트를 증착시키는 단계를 구비하여 이루어지는 이중 캐패시터 제조방법.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double capacitor manufacturing method, and more particularly, to a capacitor manufacturing method for increasing a capacitor area in a stack cell and forming a cell structure in a stable process. To this end, in the present invention, in the method of manufacturing a double capacitor, a step of forming a field oxide film and a gate on a silicon substrate, and then forming a bit line and a bit line insulating film; Depositing, forming a first node contact and forming a first capacitor dielectric, depositing a second node polysilicon and connecting it with the first node polysilicon, planarizing with photoresist and the first node Etching the polysilicon and the second node polysilicon; and forming a second capacitor dielectric and depositing a capacitor plate after stripping the photoresist.

Description

이중 캐패시터 제조방법.Double capacitor manufacturing method.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 이중 캐패시터 제조 방법을 도시한 도면, 제3도는 본 발명의 이중 캐패시터 등가 회로도.2 is a diagram illustrating a method of manufacturing a double capacitor of the present invention, and FIG. 3 is an equivalent circuit diagram of a double capacitor of the present invention.

Claims (1)

이중 캐패시터 제조 방법에 있어서, 실리콘 기판위에 필드 산화막 및 게이트를 형성한 다음 비트라인, 비트라인 절연막을 형성하는 단계와, 제1플레이트 폴리 실리콘을 입힌후 평탄화 작업을 하고 산화막을 증착시키는 단계와, 제1노드 콘택을 형성하고 제1캐패시터 유전체를 형성시키는 단계와, 제2노드 폴리 실리콘을 증착시켜 제1노드 폴리실리콘과 연결시키는 단계와, 포토 레지스트로 평탄화시키고 상기 제1노드 폴리 실리콘 및 제2노드 폴리실리콘을 식각하는 단계와, 포토 레지스트를 스트립한 후 제2캐패시터 유전체를 형성하고 캐패시터 플레이트를 증착시키는 단계를 구비하여 이루어지는 이중 캐패시터 제조방법.A method of manufacturing a double capacitor, comprising: forming a field oxide film and a gate on a silicon substrate, and then forming a bit line and a bit line insulating film, applying a first plate polysilicon to planarization, and depositing an oxide film; Forming a one-node contact and forming a first capacitor dielectric, depositing a second node polysilicon to connect with the first node polysilicon, planarizing with a photoresist and forming the first node polysilicon and the second node. Etching the polysilicon; and forming a second capacitor dielectric and depositing a capacitor plate after stripping the photo resist. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910016076A 1991-09-16 1991-09-16 Manufacturing method of double capacitor KR940009618B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910016076A KR940009618B1 (en) 1991-09-16 1991-09-16 Manufacturing method of double capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910016076A KR940009618B1 (en) 1991-09-16 1991-09-16 Manufacturing method of double capacitor

Publications (2)

Publication Number Publication Date
KR930006943A true KR930006943A (en) 1993-04-22
KR940009618B1 KR940009618B1 (en) 1994-10-15

Family

ID=19319963

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910016076A KR940009618B1 (en) 1991-09-16 1991-09-16 Manufacturing method of double capacitor

Country Status (1)

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KR (1) KR940009618B1 (en)

Also Published As

Publication number Publication date
KR940009618B1 (en) 1994-10-15

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