KR930008882B1 - Mahufacturing method of double stack capacitor - Google Patents

Abstract

A semiconductor memory device having a double stacked capacitor is prepared for VLSI or DRAM. The production method comprises; (A) forming an oxide film (5) on the semiconductor substrate having a transistor; (B) forming a 1st contact on a side of source/drain (4) region of the transistor; (C) forming a lower storage poly (6) connected with source/drain (4) of the 1st buried contact by depositing a polysilicon, and patterning it; (D) forming a lower dielectric layer (7) on (6); (E) forming a lower plate poly (8) of polysilicon and a dielectric layer (19) and forming a 2nd buried contact on the side of (4); (F) forming an upper storage poly (11) connected with (4) of the 2nd buried contact by forming a side wall spacer (10) on the side face of 2nd buried contact, depositing a polysilicon and patterning with the same width of (6), and (G) forming an upper dielectric layer (12) on (11) an the upper plate poly (13) of polysilicon on all surface of it.

Description

Method for manufacturing double stack capacitor of semiconductor memory device

1 (a)-(e) is a manufacturing process diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

1 substrate 2 field oxide film

3: gate 4: source and drain region

5: oxide film 6: lower layer storage poly

7: Lower Dielectric Layer 8: Lower Plate Poly

9 Insulation layer 10 Side wall spacer

11: upper storage poly 12: upper dielectric layer

13: upper plate poly 14: bit line

15: wordline

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a method for manufacturing a double stack capacitor of a semiconductor memory device, which can be applied to an ultra large scale integrated circuit (ULSI) DRAM.

At present, studies are being actively conducted to solve the problem of miniaturization of an effective part that can be used as a capacitor according to the trend of high integration of semiconductor devices.

The present invention is one of the studies in response to this trend, and an object of the present invention is to provide a semiconductor memory device using a double stack structure to maximize the capacitance by maintaining the area of the storage poly by two times or more than the conventional stack capacitor structure. It is to provide a method of manufacturing a double stack capacitor.

In order to achieve the above object, the present invention provides a process for forming an oxide film 5 on a semiconductor substrate on which a transistor is formed and forming a first buried contact in one of the source / drain regions 4 of the transistor; Depositing polysilicon on the entire surface of the resultant and patterning it in a predetermined pattern to form a lower storage poly (6) connected to the source / drain (4) through the first barrier contact, and on the lower storage poly (6) Forming a lower dielectric layer (7) on the substrate, and forming a lower layer poly (8) made of polysilicon on the entire surface of the resultant, forming an insulating layer (19), and then the other region of the source / drain region (4) Forming a second buried contact, forming a sidewall spacer 10 on the side of the second buried contact, depositing polysilicon, and patterning the same width as that of the lower layer storage poly Forming an upper sporridge poly 11 connected to the source / drain 4 through a second buried contact, and forming an upper dielectric layer 12 on the upper storage poly 11 and using polysilicon on the entire surface. It provides a method for manufacturing a double stack capacitor of a semiconductor memory device comprising the step of forming the upper plate poly (13).

Hereinafter, the present invention will be described in detail by the accompanying drawings.

(A)-(e) is a manufacturing process diagram according to the present invention, in which a field oxide film 2, a gate 3, a source and a drain region 4 are formed on a substrate 1 as shown in FIG. 1a. After forming the transistors in order, as shown in FIG. 1B, the oxide film 5 is deposited on the entire surface, and the first buried contact is formed on one of the source and drain regions 4, and then the polysilicon is formed on the entire surface. Is deposited and patterned in a predetermined pattern to form the lower layer storage poly (6).

Subsequently, as shown in FIG. 1C, after forming the lower dielectric layer 7 on the lower storage poly 6, polysilicon is deposited on the entire surface to form the lower plate poly 8, followed by the insulating layer 9 Is formed and then a second buried contact is formed in the other of the source and drain regions (4). The sidewall spacer 10 is formed of an insulating material on the side of the second buried contact in which the storage poly 6, the lower dielectric layer 7, and the lower plate poly 8 are exposed as shown in FIG. 1D, and then polysilicon is deposited. After patterning the same width as the lower storage poly (6) to form the upper storage poly (11), the upper dielectric layer (12) is formed on the upper storage poly (11) and polysilicon is deposited on the entire upper plate poly ( 13).

Thereafter, as shown in FIG. 1E, when the bit line 14 and the word line 15 are sequentially formed in the predetermined region, the double stack capacitor according to the present invention is completed.

Here, it should be noted that the present invention uses only dry etching when forming the poly layer.

As described above, according to the present invention, when the same size cell is used, the existing stack capacitor increases the effective area of the storage poly by more than two times to obtain an increase in capacitance, and also has a flat structure in areas other than the bit line. There is an effect that the post-process becomes easy.

Moreover, only dry etching is used to form the poly layer, thus maintaining the process accurately.

Claims (1)

Forming an oxide film 5 on a semiconductor substrate on which a transistor is formed, and forming a first buried contact in one of the source / drain regions 4 of the transistor, depositing polysilicon on the entire surface of the resultant, and forming a predetermined pattern Forming a lower layer poly (6) connected to the source / drain (4) through the first buried contact, and forming a lower dielectric layer (7) on the lower storage poly (6). Forming a polysilicon lower layer plate poly (8) on the entire surface of the resultant, forming an insulating layer (19), and then forming a second buried contact in the other one of the source / drain regions (4). After forming the sidewall spacer 10 on the side of the second buried contact, polysilicon is deposited and patterned to the same width as the lower storage poly (6), so that the source / drain is formed through the second buried contact (4). ) Forming an upper dielectric layer 12 on the upper storage poly 11 and forming an upper plate poly 13 made of polysilicon on its entire surface. A method for manufacturing a double stack capacitor of a semiconductor memory device.

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