KR920015528A - Method for manufacturing double stack capacitor of semiconductor memory device - Google Patents

Method for manufacturing double stack capacitor of semiconductor memory device Download PDF

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Publication number
KR920015528A
KR920015528A KR1019910000108A KR910000108A KR920015528A KR 920015528 A KR920015528 A KR 920015528A KR 1019910000108 A KR1019910000108 A KR 1019910000108A KR 910000108 A KR910000108 A KR 910000108A KR 920015528 A KR920015528 A KR 920015528A
Authority
KR
South Korea
Prior art keywords
forming
polysilicon
applying
memory device
semiconductor memory
Prior art date
Application number
KR1019910000108A
Other languages
Korean (ko)
Other versions
KR930008882B1 (en
Inventor
박승현
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000108A priority Critical patent/KR930008882B1/en
Publication of KR920015528A publication Critical patent/KR920015528A/en
Application granted granted Critical
Publication of KR930008882B1 publication Critical patent/KR930008882B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

반도체 메모리 소자의 더블스택 커패시터 제조방법Method for manufacturing double stack capacitor of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 (a)∼(e)는 본 발명에 따른 제조공정도이다.1 (a) to (e) are manufacturing process diagrams according to the present invention.

Claims (1)

소오스 및 드레인영역의 형성공정이 완료된 반도체메모리소자에 있어서, 전면에 산화막을 도포하고 상기 소오스 및 드레인영역중 한쪽에 배리드 콘택을 형성한후 전면에 폴리실리콘을 도포하고 소정의 부분으로 제한하여 하층스토리지폴리를 형성하는 공정과, 상기 하층스토리지 폴리상에 하층유전체층을 도포한 후 전면에 폴리실리콘으로된 하층플레이트폴리를 형성하고 절연층을 도포한 다음 상기 소오스 및 드레인영역 중 다른 한쪽에 배리드 콘택을 형성하는 공정과, 상기 배리드 콘택의 측면에 측벽 스페이서를 형성한 후 폴리실리콘을 도포하고 하층스토리지폴리와 동일 넓이로 제한하여 상층 스토리지폴리를 형성한 다음, 상층 스토리지폴리상에 상층 유전체층을 도포하고 전면에 폴리실리콘으로된 상층 플레이트를 형성하는 공정과, 그위에 비트라인과 워드라인을 차례로 형성하는 공정으로 이루어진 반도체 메모리소자의 더블스택 커패시터 제조방법.In a semiconductor memory device in which a source and drain region forming process is completed, an oxide film is coated on the entire surface, a buried contact is formed on one of the source and drain regions, and then polysilicon is coated on the entire surface, and then limited to a predetermined portion. Forming a storage poly, and applying a lower dielectric layer on the lower storage poly, forming a polysilicon underlayer polysilicon on the front surface, applying an insulating layer, and then applying a buried contact to the other of the source and drain regions. Forming a sidewall spacer on the side of the buried contact and then applying polysilicon and forming the upper storage poly by limiting it to the same width as the lower storage poly, and then applying the upper dielectric layer on the upper storage poly. And forming an upper plate of polysilicon on the front side, A method for manufacturing a double stack capacitor of a semiconductor memory device, comprising a step of sequentially forming bit lines and word lines. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910000108A 1991-01-07 1991-01-07 Mahufacturing method of double stack capacitor KR930008882B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000108A KR930008882B1 (en) 1991-01-07 1991-01-07 Mahufacturing method of double stack capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000108A KR930008882B1 (en) 1991-01-07 1991-01-07 Mahufacturing method of double stack capacitor

Publications (2)

Publication Number Publication Date
KR920015528A true KR920015528A (en) 1992-08-27
KR930008882B1 KR930008882B1 (en) 1993-09-16

Family

ID=19309491

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000108A KR930008882B1 (en) 1991-01-07 1991-01-07 Mahufacturing method of double stack capacitor

Country Status (1)

Country Link
KR (1) KR930008882B1 (en)

Also Published As

Publication number Publication date
KR930008882B1 (en) 1993-09-16

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