KR950024351A - EPROM semiconductor device and forming method thereof - Google Patents

EPROM semiconductor device and forming method thereof Download PDF

Info

Publication number
KR950024351A
KR950024351A KR1019940000312A KR19940000312A KR950024351A KR 950024351 A KR950024351 A KR 950024351A KR 1019940000312 A KR1019940000312 A KR 1019940000312A KR 19940000312 A KR19940000312 A KR 19940000312A KR 950024351 A KR950024351 A KR 950024351A
Authority
KR
South Korea
Prior art keywords
floating gate
gate
forming
layer
semiconductor device
Prior art date
Application number
KR1019940000312A
Other languages
Korean (ko)
Other versions
KR0123782B1 (en
Inventor
김호현
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940000312A priority Critical patent/KR0123782B1/en
Publication of KR950024351A publication Critical patent/KR950024351A/en
Application granted granted Critical
Publication of KR0123782B1 publication Critical patent/KR0123782B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)

Abstract

EPROM반도체 기억장치 및 이의 제조방법에 있어서, 게이트전극의 형성시 플로팅게이트전극의 측면상에 측벽을 형성하여 콘트롤 게이트의 프로파일을 양호하게 하며, 또한 에치공정을 단순화시키도록, 반도체 기판상에 형성한 게이트절연층 위에 제1폴리실리콘층을 적층하고 사진식각방법으로 플로팅 게이트를 형성하는 공정과, 플로팅 게이트 측면상에 소정의 두께로 측벽을 형성하는 공정과, 기판전면에 절연층을 형성하고 제2의 폴리실리콘층을 형성한 후 패터닝하여 콘트롤 게이트를 형성하는 공정으로 형성하며, 게이트전극 구조는 플로팅게이트와, 플로팅게이트의 측면상에 형성된 측벽과, 플로팅게이트 상에 형성한 유전층과, 상기 플로팅 게이트전곡상에 상기 유전층을 사이에 두고 형성한 콘트롤 게이트로 구성된다.In an EPROM semiconductor memory device and a method for manufacturing the same, a sidewall is formed on the side surface of the floating gate electrode when the gate electrode is formed so as to improve the profile of the control gate and to simplify the etch process. Stacking a first polysilicon layer on the gate insulating layer and forming a floating gate by a photolithography method; forming a sidewall with a predetermined thickness on a side of the floating gate; forming an insulating layer on the front surface of the substrate; A polysilicon layer is formed and patterned to form a control gate. The gate electrode structure includes a floating gate, sidewalls formed on side surfaces of the floating gate, a dielectric layer formed on the floating gate, and the floating gate. It is composed of a control gate formed by sandwiching the dielectric layer on the whole grain.

Description

EPROM반도체 장치 및 이의 형성방법EPROM semiconductor device and forming method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(a), (b)는 본 발명에 따른 EPROM 반도체 기억장치의 게이트 전극 형성고정수순을 보인 공정도.2 (a) and 2 (b) are process drawings showing a fixed procedure for forming gate electrodes of the EPROM semiconductor memory device according to the present invention.

Claims (3)

반도체 기판상에 헝썽한 게이트절연층 위에 제1폴리실리콘층을 적충하고 사진식각방법으로 플로팅 게이트를 형성하는 공정과, 플로팅 게이트 측면상에 소정의 두께로 측벽을 형성하는 공정과, 기판전면에 절연층을 형성하고 제2의 폴리 실리콘층을 형성한 후 패터닝하여 콘트롤 게이트를 형성하는 공정으로 이루어지는 것을 특징으로 하는 EPROM 반도체 장치 형성방법.Forming a floating gate by filling a first polysilicon layer on a difficult gate insulating layer on a semiconductor substrate by a photolithography method, forming a sidewall with a predetermined thickness on the side of the floating gate, and insulating the front surface of the substrate. And forming a layer, forming a second polysilicon layer, and then patterning the control gate to form a control gate. 제1항에 있어서, 상기 측벽의 두께는 제2의 폴리실리콘층의 패턴형성시 공경여유보다 크게 하여 형성됨을 특징으로 하는 EPROM 반도체 장치 형성방법.The method of claim 1, wherein the thickness of the sidewalls is greater than the pore size margin when forming the second polysilicon layer. EPROM 반도체 장치에 있어서, 게이트전극 구조는 플로팅게이트와, 폴로팅게이트의 측면상에 형성된 측벽과, 플로팅게이트 상에 형성한 유전층과, 상기 플로팅게이트전곡상에 상기 유전층을 사이에 두고 형성한 콘트롤게이트로 구성됨을 특징으로 하는 EPROM 반도체 장치.In the EPROM semiconductor device, the gate electrode structure has a floating gate, sidewalls formed on the side of the floating gate, a dielectric layer formed on the floating gate, and a control gate formed with the dielectric layer interposed on the floating gate curve. EPROM semiconductor device, characterized in that consisting of. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940000312A 1994-01-10 1994-01-10 Eprom semiconductor device and fabricating method thereof KR0123782B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940000312A KR0123782B1 (en) 1994-01-10 1994-01-10 Eprom semiconductor device and fabricating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940000312A KR0123782B1 (en) 1994-01-10 1994-01-10 Eprom semiconductor device and fabricating method thereof

Publications (2)

Publication Number Publication Date
KR950024351A true KR950024351A (en) 1995-08-21
KR0123782B1 KR0123782B1 (en) 1997-11-25

Family

ID=19375451

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940000312A KR0123782B1 (en) 1994-01-10 1994-01-10 Eprom semiconductor device and fabricating method thereof

Country Status (1)

Country Link
KR (1) KR0123782B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020044261A (en) * 2000-12-05 2002-06-15 박종섭 Method of manufacturing a flash memory cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020044261A (en) * 2000-12-05 2002-06-15 박종섭 Method of manufacturing a flash memory cell

Also Published As

Publication number Publication date
KR0123782B1 (en) 1997-11-25

Similar Documents

Publication Publication Date Title
KR920022525A (en) Method for manufacturing capacitor of DRAM cell and its structure
KR920018951A (en) Highly Integrated Semiconductor Memory Device and Manufacturing Method Thereof
KR980005441A (en) Manufacturing Method of Semiconductor Device
KR920008938A (en) Stack Capacitor and Manufacturing Method
KR950024351A (en) EPROM semiconductor device and forming method thereof
KR920013728A (en) Semiconductor Memory and Manufacturing Method
KR980005589A (en) Method of forming a contact of a semiconductor device
KR970054088A (en) Method for manufacturing charge storage electrode of semiconductor device
KR940008072A (en) Capacitor manufacturing method having high storage capacity of semiconductor device
KR970054158A (en) Capacitor Formation Method of Semiconductor Device
KR960026836A (en) Capacitor Formation Method
KR950002039A (en) Semiconductor device and manufacturing method
KR970054078A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970054130A (en) Method of forming pad layer in semiconductor memory device
KR950021548A (en) Capacitor of Semiconductor Memory Device and Manufacturing Method Thereof
KR940016769A (en) Method for manufacturing charge storage electrode of highly integrated semiconductor memory device
KR970077218A (en) Contact formation method to improve refresh characteristics
KR950034630A (en) Method for forming storage electrode of semiconductor device
KR960026657A (en) Capacitor Formation Method
KR900017086A (en) Semiconductor memory device having double stacked capacitor structure and manufacturing method thereof
KR940016775A (en) Manufacturing method of charge preservation electrode of fence structure
KR970018694A (en) Thin Film Transistor and Manufacturing Method Thereof
KR970054060A (en) Capacitor Manufacturing Method of Semiconductor Memory Device
KR970054002A (en) Manufacturing Method of Semiconductor Memory Device
KR960026966A (en) Gate structure of transistor and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060818

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee