KR960026836A - Capacitor Formation Method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor memory device, and to sufficiently secure the capacitance of a cell by maximizing the surface area of the capacitor by releasing the capacitor through a plurality of polysilicon film forming processes, an insulating film forming process, and an etching process. The self-aligned contact ensures a capacitor contact process margin, thereby improving the reliability of the device.

Description

Capacitor Formation Method

Since this is an open matter, no full text was included.

2A through 2I are capacitor formation process diagrams according to one embodiment of the present invention.

Claims (2)

Sequentially filling the first conductive film for the capacitor plate electrode, the first dielectric film, and the second conductive film for the capacitor charge storage electrode on the planarized first insulating film formed on the predetermined contact portion of the capacitor: the second conductive film on the contact portion Etching the first dielectric layer and the first conductive layer in order, and then etching the exposed first insulating layer only a part of the entire thickness to form a recessed portion: forming a second insulating layer spacer on the sidewall of the recessed portion; Forming a capacitor contact hole by etching the first insulating layer having the remaining thickness using the second conductive layer and the second insulating layer spacer as an etch mask; Forming a third conductive film for the charge storage nation on the entire structure: patterning a third insulating film having a predetermined portion around the contact hole open on the third conductive film; Forming the fourth conductive film for the storage electrode: determining the size of the charge storage electrode, the center portion of which is the width of the contact hole until the first conductive film and the third insulating film are exposed by using an open etching mask material. Etching the intermediate films in sequence and removing the third insulating layer: forming a second dielectric layer and a fifth conductive layer for the plate electrode at a predetermined thickness along the upper surface of the entire structure: an etching mask larger than the size of the charge storage electrode Etching the fifth conductive film and the second dielectric film using a material; And forming a sixth conductive film for plate electrodes on top of the entire structure. The method of claim 1, wherein the first to sixth conductive films are doped polysilicon films. ※ Note: The disclosure is based on the initial application.