KR960026966A - Gate structure of transistor and manufacturing method thereof - Google Patents

Gate structure of transistor and manufacturing method thereof Download PDF

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Publication number
KR960026966A
KR960026966A KR1019940035442A KR19940035442A KR960026966A KR 960026966 A KR960026966 A KR 960026966A KR 1019940035442 A KR1019940035442 A KR 1019940035442A KR 19940035442 A KR19940035442 A KR 19940035442A KR 960026966 A KR960026966 A KR 960026966A
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KR
South Korea
Prior art keywords
gate
insulating layer
layer
gate electrode
gate insulating
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KR1019940035442A
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Korean (ko)
Inventor
엄금용
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940035442A priority Critical patent/KR960026966A/en
Publication of KR960026966A publication Critical patent/KR960026966A/en

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자 제조공정 중 게이트절연층/게이트전극층으로 이루어지는 트랜지스터의 게이트 구조 및 그 제조방법에 관한 것으로, 특히 게이트절연층의 열화를 방지하기 위해 게이트절연층(26), 제1게이트전극(27), 제2게이트전극(277)이 적층되되, 게이트절연층(26)의 하부 가장자리 일부분이 식각되어 T형 구조를 이루며, 사이 게이트절연층의 식각부위를 매우면서 전체표면을 따라 제2게이트전극(277)이 형성된 구조를 포함하여 이루어지는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate structure of a transistor comprising a gate insulating layer / gate electrode layer and a method of manufacturing the same. In particular, the gate insulating layer 26 and the first gate electrode ( 27) the second gate electrode 277 is stacked, and a portion of the lower edge of the gate insulating layer 26 is etched to form a T-type structure, and the second gate is formed along the entire surface while forming an etched portion of the gate insulating layer 26. It characterized in that it comprises a structure in which the electrode 277 is formed.

Description

트랜지스터의 게이트 구조 및 그 제조방법Gate structure of transistor and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 일실시예에 따른 게이트의 구조를 나타내는 단면도, 제3A도 내지 제3C도는 본 발명의 일실시예에 따른 게이트 형성 공정 단면도.2 is a cross-sectional view illustrating a structure of a gate according to an embodiment of the present invention, and FIGS. 3A to 3C are cross-sectional views of a gate forming process according to an embodiment of the present invention.

Claims (6)

게비트절연층(26), 제1게이트전극(27),제2게이트전극(277)이 적층되되, 게이트절연층(26)의 하부 가장자리 일부분이 식각되어 T형 구조를 이루며, 상기 게이트절연층의 식각부위를 매우면서 전체 표면을 따라 제2게이트전극(277)이 형성된 구조를 포함하여 이루어지는 것을 특징으로 하는 트랜지스터의 게이트 구조.A gebbit insulating layer 26, a first gate electrode 27, and a second gate electrode 277 are stacked, and a portion of the lower edge of the gate insulating layer 26 is etched to form a T-type structure. The gate structure of the transistor comprising a structure in which the second gate electrode (277) is formed along the entire surface while the etching portion of the. 반도체 소자의 제조공정 중 예정된 게이트 형성층에 게이트절연층, 제1게이트전극층을 패턴형성 하는 제1단계; 상기 게이트절연층 하부 가장자리를 일부 식각하는 제2단계; 상기 게이트절연층의 식각부위를 매우면서 제2게이트전극층을 형성하는 제3단계를 포함하여 이루어지는 것을 특징으로 하는 트랜지스터의 게이트 형성방법.A first step of patterning a gate insulating layer and a first gate electrode layer on a predetermined gate forming layer during a semiconductor device manufacturing process; A second step of partially etching the lower edge of the gate insulating layer; And forming a second gate electrode layer while forming an etching portion of the gate insulating layer. 제2항에 있어서, 상기 게이트절연층은 산화층으로 이루어지는 것을 특징으로 하는 트랜지스터의 게이트 형성방법.The method of claim 2, wherein the gate insulating layer is formed of an oxide layer. 제2항에 또는 제3항에 있어서, 상기 제1 및 제2게이트전극층은 폴리실리콘층으로 이루어지는 것을 특징으로 하는 트랜지스터의 게이트 형성방법.4. The method of claim 2 or 3, wherein the first and second gate electrode layers are made of a polysilicon layer. 제4항에 있어서, 상기 제1게이트폴리실리콘층은 1200 내지 2000A 두께로 형성되는 것을 특징으로 하는 트랜지스터의 게이트 형성방법.The method of claim 4, wherein the first gate polysilicon layer is formed to a thickness of 1200 to 2000 A. 6. 제5항에 있어서, 상기 제2게이트폴리실리콘층은 200 내지 700A 두께로 형성되는 것을 특징으로 하는 트랜지스터의 게이트 형성방법.The method of claim 5, wherein the second gate polysilicon layer is formed to a thickness of 200 to 700 A. 7. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035442A 1994-12-20 1994-12-20 Gate structure of transistor and manufacturing method thereof KR960026966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940035442A KR960026966A (en) 1994-12-20 1994-12-20 Gate structure of transistor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940035442A KR960026966A (en) 1994-12-20 1994-12-20 Gate structure of transistor and manufacturing method thereof

Publications (1)

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KR960026966A true KR960026966A (en) 1996-07-22

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KR1019940035442A KR960026966A (en) 1994-12-20 1994-12-20 Gate structure of transistor and manufacturing method thereof

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