KR970018553A - Capacitor Manufacturing Method of Semiconductor Memory Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Memory Device Download PDF

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Publication number
KR970018553A
KR970018553A KR1019950029327A KR19950029327A KR970018553A KR 970018553 A KR970018553 A KR 970018553A KR 1019950029327 A KR1019950029327 A KR 1019950029327A KR 19950029327 A KR19950029327 A KR 19950029327A KR 970018553 A KR970018553 A KR 970018553A
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KR
South Korea
Prior art keywords
forming
wet etching
insulating layer
memory device
depositing
Prior art date
Application number
KR1019950029327A
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Korean (ko)
Inventor
김민
박선후
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950029327A priority Critical patent/KR970018553A/en
Publication of KR970018553A publication Critical patent/KR970018553A/en

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Abstract

핀 구조의 스택형 캐패시터의 제조 방법에 대해 기재되어 있다. 이는 반도체기판 상에 식각방지층을 형성하는 공정, 습식식각 속도가 다른 두 절연층을 교대로 2층 이상 증착하는 공정, 상기 절연층들을 이방성식각하여 콘택홀을 형성하는 공정, 상기 콘택홀을 통해 노출된 상기 절연층을 습식식각함으로서, 핀구조를 형성하는 공정, 결과물 상에 도전물질을 증착한 후 패터닝함으로써 핀 형태의 스토리지전극을 형성하는 공정, 및 상기 스토리지전극 상에 유전체막 및 플레이트 전극을 형성하는 공정을 포함하는 것을 특징으로 한다. 따라서, 단순화할 수 있고 공정시간을 단축할 수 있다.A method of manufacturing a finned stacked capacitor is described. This method includes forming an etch stop layer on a semiconductor substrate, depositing two or more layers having different wet etching rates alternately, forming a contact hole by anisotropically etching the insulating layers, and exposing through the contact hole. Forming a fin structure by wet etching the insulating layer, forming a fin electrode by depositing and patterning a conductive material on the resultant, and forming a dielectric layer and a plate electrode on the storage electrode Characterized in that it comprises a step to. Therefore, it is possible to simplify and shorten the process time.

Description

반도체 메모리 장치의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2C도 내지 제2D도는 본 발명의 제1실시예에 따른 핀구조의 캐패시터의 제조 방법을 설명하기 위한 단면도들이다.2C to 2D are cross-sectional views illustrating a method of manufacturing a capacitor having a fin structure according to a first embodiment of the present invention.

Claims (4)

반도체기판 상에 식각방지층을 형성하는 공정; 습식식각 속도가 다른 두 절연층을 교대로 2층 이상 증착하는 공정; 상기 절연층들을 이방성식각하여 콘택홀을 형성하는 공정; 상기 콘택홀을 통해 노출된 상기 절연층을 습식식각함으로서, 핀구조를 형성하는 공정; 결과물 상에 도전물질을 증착한 후 패터닝함으로써 핀 형태의 스토리지전극을 형성하는 공정; 및 상기 스토리지전극 상에 유전체막 및 플레이트 전극을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조 방법.Forming an etch stop layer on the semiconductor substrate; Depositing two or more layers of two insulating layers having different wet etching rates alternately; Anisotropically etching the insulating layers to form contact holes; Forming a fin structure by wet etching the insulating layer exposed through the contact hole; Forming a fin-type storage electrode by depositing a conductive material on the resultant and patterning the conductive material; And forming a dielectric film and a plate electrode on the storage electrode. 제1항에 있어서, 상기 습식식각 속도가 빠른 절연층을 100℃~250℃의 온도와, RF전력이 100W~500W의 범위내에서 증착한 플라즈마 산화막이고, 상기 습식식각 속도가 느린 절연층은 증착 350℃~600℃의 증착온도와, RF 전력이 500W~900W에서 증착한 플라지마 산화막으로 형성되는 것을 특징으로 하는 반도체 메모리장치의 캐패시터 제조 방법.The method of claim 1, wherein the wet etching rate of the insulating layer is a plasma oxide film deposited at a temperature of 100 ℃ to 250 ℃, RF power of 100W ~ 500W, the insulating layer having a slow wet etching rate is deposited A method for manufacturing a capacitor of a semiconductor memory device, characterized in that it is formed of a plasma oxide film deposited at 350 ° C to 600 ° C and RF power is deposited at 500W to 900W. 제1항에 있어서, 상기 습식식각 속도가 빠른 절연층의 두께가 식각속도가 느린 절연층의 두께의 3배 이상이거나 비슷한 두께인 것을 특징으로 하는 반도체 메모리장치의 캐패시터 제조 방법.The method of claim 1, wherein a thickness of the insulating layer having a high wet etching rate is at least three times or similar to a thickness of the insulating layer having a low etching rate. 제1항에 있어서, 상부 전극 형성을 위한 사진공정 대신에 스핀 온 글래스(SOG)막이나, 포토레지스트를 도포한 후 에치백하는 공정을 사용하여 진행하는 것을 특징으로 하는 반도체 메모리장치의 캐패시터 제조 방법.The method of manufacturing a capacitor of a semiconductor memory device according to claim 1, wherein a spin-on glass (SOG) film or a photoresist is applied and then etched back in place of a photo process for forming an upper electrode. .
KR1019950029327A 1995-09-07 1995-09-07 Capacitor Manufacturing Method of Semiconductor Memory Device KR970018553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950029327A KR970018553A (en) 1995-09-07 1995-09-07 Capacitor Manufacturing Method of Semiconductor Memory Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950029327A KR970018553A (en) 1995-09-07 1995-09-07 Capacitor Manufacturing Method of Semiconductor Memory Device

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KR970018553A true KR970018553A (en) 1997-04-30

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010005301A (en) * 1999-06-30 2001-01-15 김영환 Forming method for capacitor of semiconductor device
KR100388682B1 (en) * 2001-03-03 2003-06-25 삼성전자주식회사 Storage electric terminal layer and method for forming thereof
KR100434496B1 (en) * 2001-12-11 2004-06-05 삼성전자주식회사 One cylinder stack capacitor and fabrication method thereof using double mold
KR100590798B1 (en) * 1999-07-26 2006-06-15 삼성전자주식회사 Method for forming capacitor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010005301A (en) * 1999-06-30 2001-01-15 김영환 Forming method for capacitor of semiconductor device
KR100590798B1 (en) * 1999-07-26 2006-06-15 삼성전자주식회사 Method for forming capacitor
KR100388682B1 (en) * 2001-03-03 2003-06-25 삼성전자주식회사 Storage electric terminal layer and method for forming thereof
KR100434496B1 (en) * 2001-12-11 2004-06-05 삼성전자주식회사 One cylinder stack capacitor and fabrication method thereof using double mold

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