KR930005178A - 범프가 구비된 리드프레임을 이용한 반도체 패키지 및 그 제작방법 - Google Patents

범프가 구비된 리드프레임을 이용한 반도체 패키지 및 그 제작방법 Download PDF

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KR930005178A
KR930005178A KR1019910014053A KR910014053A KR930005178A KR 930005178 A KR930005178 A KR 930005178A KR 1019910014053 A KR1019910014053 A KR 1019910014053A KR 910014053 A KR910014053 A KR 910014053A KR 930005178 A KR930005178 A KR 930005178A
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South Korea
Prior art keywords
inner lead
chip
bump
semiconductor package
lead frame
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KR1019910014053A
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English (en)
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KR940008337B1 (ko
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고준수
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문정환
금성일렉트론 주식회사
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Priority to KR1019910014053A priority Critical patent/KR940008337B1/ko
Publication of KR930005178A publication Critical patent/KR930005178A/ko
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Publication of KR940008337B1 publication Critical patent/KR940008337B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

내용 없음.

Description

범프가 구비된 리드프레임을 이용한 반도체 패키지 및 그 제작방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의한 범프가 구비된 리드프레임을 이용하여 제작한 반도체 패키지의 구성을 보이는 단면도.

Claims (7)

  1. 반도체 패키지에 있어서, 리드프레임의 인너리드(11)에 형성된 범프(12)와, 반도체 칩(13)외 알루미늄 페드(13a)를 가압열 압착시킴으로써 전기적으로 접속하고, 상기 칩(13)과 인너리드(11)를 포함하는 일정부위를 플라스틱등과 같은 몰드물(14)로 몰딩하여 구성함을 특징으로 하는 범프가 구비된 리드프레임을 이용한 반도체 패키지.
  2. 반도체 패키지 제작방법에 있어서, 통상적인 다이 세퍼레이션 공겅 및 다이본딩 공정과, 인너리드(11)에 범프(12)를 형성시키는 공정과, 상기 범프(12)가 구비된 인너리드(11)와 칩(13)을 전기적으로 접속시키는 본딩 공정과, 상기 칩(13)과 인너리드(11)의 일정 부분을 몰딩하는 몰딩공정과, 통상적인 플래텀공정과, 리드프레임의 댐퍼를 절단하는 트리밍 공정과, 리드프레임의 아웃리드를 소정의 방향으로 절곡하는 포밍공정을 포함하여 구성함을 특징으로 하는 범프가 구비된 리드프레임을 이용한 반도체 패키지 제작방법.
  3. 제1항에 있어서, 상기 인너리드(11)에 범프(12)를 형성하는 공정은 인너리드(11)의 일측부에 솔더플래팅을 한 다음 범프를 형성시킬 부분을 피팅하고, 피텅부위를 디파인하기 위한 PR 코팅을 실시한 후, 피팅부분에 전도성물질을 코팅하고 상기 PR충을 제거하여 인너러드(11)에 범프(12)가 형성되도특 함을 특징으로 하는 범프가 구비된 리드프레임을 이용한 반도체 패키지 제작방법.
  4. 제2항에 있어서, 상기 인너리드(11)와 칩(13)을 전기적으로 접속시키는 본딩공정은 펄스히팅 방법으로 가압 열압착함을 특징으로 하는 범프가 구비된 리드프레임을 이용한 반도체 패키지 제작방법.
  5. 제2항에 있어서, 상기 인너리드(11)와 칩(13)을 전기적으로 접속시키는 본딩공정은 핫-에어를 이용하여 가압 열압착함을 특징으로 하는 범프가 구비된 리드프레임을 이용한 반도체 패키지 제작방법.
  6. 제3항에 있어서, 상기 인너리드(11)의 피팅부분에 코팅되는 전도성 물질은 솔더인것을 특징으로 하는 범프가 구비된 리드프레임을 이용한 반도체 패키지 제작방법.
  7. 제3항에 있어서, 상기 인너리드(11)의 피팅부분에 코팅되는 전도성 물질은 골드인 것을 특징으로 하는 범프가 구비된 리드프레임을 이용한 반도체 패키지 제작방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910014053A 1991-08-14 1991-08-14 반도체 패키지의 제조방법 KR940008337B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910014053A KR940008337B1 (ko) 1991-08-14 1991-08-14 반도체 패키지의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910014053A KR940008337B1 (ko) 1991-08-14 1991-08-14 반도체 패키지의 제조방법

Publications (2)

Publication Number Publication Date
KR930005178A true KR930005178A (ko) 1993-03-23
KR940008337B1 KR940008337B1 (ko) 1994-09-12

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