KR930003595A - 위상 오차 처리기 - Google Patents
위상 오차 처리기 Download PDFInfo
- Publication number
- KR930003595A KR930003595A KR1019920012500A KR920012500A KR930003595A KR 930003595 A KR930003595 A KR 930003595A KR 1019920012500 A KR1019920012500 A KR 1019920012500A KR 920012500 A KR920012500 A KR 920012500A KR 930003595 A KR930003595 A KR 930003595A
- Authority
- KR
- South Korea
- Prior art keywords
- phase error
- data
- time slot
- error information
- processing window
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따라 위상 오차 처리기를 결합하는 위상동기 루프 회로의 블럭 다이어그램,
제2도는 바람직한 위상 검파기의 전달 특성을 도시한 도면,
제3도는 본 발명의 위상 오차 처리기의 바람직한 실시예에 관한 간략화된 블럭 다이어그램,
제7도는 바람직한 실시예에 사용된 충전 및 덤프 회로의 회로 다이어그램,
제8도는 위상 오차 처리기내에서의 충전 및 덤프회로의 동작을 도시한 타이밍 다이어그램.
Claims (1)
- 주기적인 클럭신호를 수신하며 양의 정수인 N개 클럭 사이클의 데이타 처리 윈도우를 규정하는 타이밍 신호들을 발생시키는 타임 슬롯 디코더; 데이타 신호내의 데이타 전이 각각에 대해서 위상 검파기로부터 비례 위상 오차 정보를 수신하며, 상기 적분회로가 각각의 데이타 처리 윈도우 동안에 예정된 갯수의 데이타 전이들에 대한 상기 비례 위상 오차 정보를 적분하는, 상기 타임 슬롯 디코더에 연결된 적분회로; 및 상기 적분된 비례 위상 오차 정보를 참조 신호와 비교하며 상기 비교에 따라 각 데이타 처리 윈도우마다 한번씩 Up/Down신호를 발생시키는, 상기 적분회로 및 상기 타임 슬롯 디코더에 연결된 비교기; 를 포함하며, 데이타 복구회로내에 사용하기 위한 위상 오차 처리기.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/731,138 US5239561A (en) | 1991-07-15 | 1991-07-15 | Phase error processor |
US7/731,138 | 1991-07-15 | ||
US07/731,138 | 1991-07-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930003595A true KR930003595A (ko) | 1993-02-24 |
KR100230611B1 KR100230611B1 (ko) | 1999-11-15 |
Family
ID=24938224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920012500A KR100230611B1 (ko) | 1991-07-15 | 1992-07-14 | 위상 오차 처리기 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5239561A (ko) |
EP (1) | EP0523886B1 (ko) |
JP (1) | JP3263436B2 (ko) |
KR (1) | KR100230611B1 (ko) |
DE (1) | DE69214888T2 (ko) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5351275A (en) * | 1991-07-15 | 1994-09-27 | National Semiconductor Corporation | Digital serial loop filter for high speed control systems |
US5402443A (en) * | 1992-12-15 | 1995-03-28 | National Semiconductor Corp. | Device and method for measuring the jitter of a recovered clock signal |
US6078634A (en) * | 1993-10-08 | 2000-06-20 | Texas Instruments Incorporated | Phase-locked loop circuit with a multi-cycle phase detector and multi-current charge pump |
CA2130871C (en) * | 1993-11-05 | 1999-09-28 | John M. Alder | Method and apparatus for a phase-locked loop circuit with holdover mode |
KR970002949B1 (ko) * | 1994-05-25 | 1997-03-13 | 삼성전자 주식회사 | 디지탈 통신시스템의 클럭발생방법 및 그 회로 |
US5477177A (en) * | 1995-01-11 | 1995-12-19 | National Semiconductor Corporation | Phase error processor circuit with a comparator input swapping technique |
US5651035A (en) * | 1995-04-28 | 1997-07-22 | International Microcircuits, Inc. | Apparatus for reducing jitter of a spectrum spread clock signal and method therefor |
US6014176A (en) * | 1995-06-21 | 2000-01-11 | Sony Corporation | Automatic phase control apparatus for phase locking the chroma burst of analog and digital video data using a numerically controlled oscillator |
US5825824A (en) * | 1995-10-05 | 1998-10-20 | Silicon Image, Inc. | DC-balanced and transition-controlled encoding method and apparatus |
US5999571A (en) * | 1995-10-05 | 1999-12-07 | Silicon Image, Inc. | Transition-controlled digital encoding and signal transmission system |
US5974464A (en) * | 1995-10-06 | 1999-10-26 | Silicon Image, Inc. | System for high speed serial video signal transmission using DC-balanced coding |
US6212248B1 (en) * | 1998-03-18 | 2001-04-03 | International Business Machines Corporation | Shared path phase detector having phase indicator |
KR100767319B1 (ko) * | 2000-06-28 | 2007-10-17 | 톰슨 라이센싱 | 고주파 발진기 |
AU2002218798A1 (en) | 2000-07-10 | 2002-01-21 | Silicon Laboratories, Inc. | Digital phase detector circuit and method therefor |
US6950957B1 (en) | 2000-09-11 | 2005-09-27 | Adc Telecommunications, Inc. | Phase comparator for a phase locked loop |
US6333651B1 (en) * | 2000-12-01 | 2001-12-25 | Exar Corporation | Second order digital jitter attenuator |
US6590427B2 (en) | 2001-01-03 | 2003-07-08 | Seagate Technology Llc | Phase frequency detector circuit having reduced dead band |
US6987424B1 (en) | 2002-07-02 | 2006-01-17 | Silicon Laboratories Inc. | Narrow band clock multiplier unit |
US6836167B2 (en) * | 2002-07-17 | 2004-12-28 | Intel Corporation | Techniques to control signal phase |
US7478257B2 (en) | 2003-03-31 | 2009-01-13 | Intel Corporation | Local receive clock signal adjustment |
EP1473828A1 (en) * | 2003-04-30 | 2004-11-03 | STMicroelectronics S.r.l. | Phase detector and method of generating a differential signal representative of a phase-shift |
US7265690B2 (en) * | 2003-09-25 | 2007-09-04 | Texas Instruments Incorporated | Simplified data recovery from high speed encoded data |
US7200782B2 (en) * | 2003-10-23 | 2007-04-03 | Texas Instruments Incorporated | Clock recovery system for encoded serial data with simplified logic and jitter tolerance |
US7721060B2 (en) * | 2003-11-13 | 2010-05-18 | Intel Corporation | Method and apparatus for maintaining data density for derived clocking |
US7119583B2 (en) * | 2004-03-31 | 2006-10-10 | Micron Technology, Inc. | Phase detector and method having hysteresis characteristics |
US7948327B1 (en) | 2005-06-30 | 2011-05-24 | Cypress Semiconductor Corporation | Simplified phase lock loop control model system and method |
US7961059B1 (en) | 2005-06-30 | 2011-06-14 | Cypress Semiconductor Corporation | Phase lock loop control system and method with non-consecutive feedback divide values |
US8174326B1 (en) | 2005-06-30 | 2012-05-08 | Cypress Semiconductor Corporation | Phase lock loop control error selection system and method |
US8072277B1 (en) | 2005-06-30 | 2011-12-06 | Cypress Semiconductor Corporation | Spread spectrum frequency synthesizer |
US7932787B1 (en) | 2005-06-30 | 2011-04-26 | Cypress Semiconductor Corporation | Phase lock loop control system and method |
US7813411B1 (en) | 2005-06-30 | 2010-10-12 | Cypress Semiconductor Corporation | Spread spectrum frequency synthesizer with high order accumulation for frequency profile generation |
US7912109B1 (en) | 2005-06-30 | 2011-03-22 | Cypress Semiconductor Corporation | Spread spectrum frequency synthesizer with first order accumulation for frequency profile generation |
WO2007063643A1 (ja) * | 2005-11-29 | 2007-06-07 | Nec Corporation | 自動調整回路およびフィルタ回路 |
US7423456B2 (en) * | 2006-12-01 | 2008-09-09 | Micron Technology, Inc. | Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods |
US9036755B2 (en) * | 2012-09-28 | 2015-05-19 | Liming Xiu | Circuits and methods for time-average frequency based clock data recovery |
US11606230B2 (en) | 2021-03-03 | 2023-03-14 | Apple Inc. | Channel equalization |
US11784731B2 (en) * | 2021-03-09 | 2023-10-10 | Apple Inc. | Multi-phase-level signaling to improve data bandwidth over lossy channels |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4371974A (en) * | 1981-02-25 | 1983-02-01 | Rockwell International Corporation | NRZ Data phase detector |
US4584695A (en) * | 1983-11-09 | 1986-04-22 | National Semiconductor Corporation | Digital PLL decoder |
US4635277A (en) * | 1985-10-21 | 1987-01-06 | Rockwell International Corporation | Digital clock recovery circuit apparatus |
IT1197969B (it) * | 1986-11-12 | 1988-12-21 | Honeywell Inf Systems | Circuito ad aggancio di fase |
US4752748A (en) * | 1987-04-16 | 1988-06-21 | Amdahl Corporation | Intelligent phase-locked loop |
GB2222751B (en) * | 1988-03-29 | 1992-08-26 | Plessey Co Plc | Clock driven data sampling circuit |
JPH0282835A (ja) * | 1988-09-20 | 1990-03-23 | Sony Corp | ディジタル信号受信装置 |
ATE121239T1 (de) * | 1989-06-15 | 1995-04-15 | Siemens Ag | Schaltungsanordnung zur phasenrichtigen regenerierung eines taktsignals. |
GB8924202D0 (en) * | 1989-10-27 | 1989-12-13 | Ncr Co | Digital phase lock loop decoder |
-
1991
- 1991-07-15 US US07/731,138 patent/US5239561A/en not_active Expired - Lifetime
-
1992
- 1992-07-01 DE DE69214888T patent/DE69214888T2/de not_active Expired - Fee Related
- 1992-07-01 EP EP92306099A patent/EP0523886B1/en not_active Expired - Lifetime
- 1992-07-13 JP JP18550992A patent/JP3263436B2/ja not_active Expired - Lifetime
- 1992-07-14 KR KR1019920012500A patent/KR100230611B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69214888D1 (de) | 1996-12-05 |
KR100230611B1 (ko) | 1999-11-15 |
US5239561A (en) | 1993-08-24 |
JPH05291946A (ja) | 1993-11-05 |
EP0523886A1 (en) | 1993-01-20 |
DE69214888T2 (de) | 1997-05-15 |
EP0523886B1 (en) | 1996-10-30 |
JP3263436B2 (ja) | 2002-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR930003595A (ko) | 위상 오차 처리기 | |
KR930003584A (ko) | 초 고주파 클럭 및 데이타 복구 회로를 위한 위상 검파기 | |
US5410550A (en) | Asynchronous latch circuit and register | |
DE69815211D1 (de) | Integrierte Schaltung mit Phasenregelschleife und eingebautem Selbsttest von Phase und Phasenzittern | |
KR880003238A (ko) | 클럭 재생 장치 | |
KR830009698A (ko) | 개선된 로크-인을 갖는 위상고정 루우프 | |
KR970701950A (ko) | 비교기 입력 스와핑 기법을 사용하는 위상 오차 처리기 회로(a phase error processor circuit with a comparator input swapping technique) | |
EP0102662A3 (en) | Non-pll concurrent carrier and clock synchronization | |
JP3196725B2 (ja) | 位相比較回路 | |
KR880013326A (ko) | 듀티사이클과 무관한 위상 검파기 | |
US4646167A (en) | Time code decoder | |
GB1476878A (en) | Binary phase digital decoding system | |
JPH10503342A (ja) | フェーズロックループ、該フェーズロックループ用位相比較器、及び該フェーズロックループを含む再生装置 | |
NO902663D0 (no) | Fremgangsmaate og koblingsanordning til faseriktig regenerering av et taktsignal. | |
JP3089962B2 (ja) | 二相符号化データの復号装置 | |
EP0604189B1 (en) | Bit-serial decoder for a specially encoded bit stream | |
KR900002624A (ko) | 클램프펄스 작성회로 | |
KR0149720B1 (ko) | 맨체스터 디코더 | |
JPS59156049A (ja) | 信号検出回路 | |
JP2864779B2 (ja) | パルス入力回路 | |
JP3011047B2 (ja) | 位相比較回路 | |
SU1711169A1 (ru) | Устройство дл сопр жени электронной вычислительной машины с магнитофоном | |
JPH06311153A (ja) | 位相比較回路 | |
US20040028165A1 (en) | Digital phase detector with extended resolution | |
KR930011452A (ko) | 직렬 데이타의 패리티 에러 검출회로 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20110810 Year of fee payment: 13 |
|
EXPY | Expiration of term |