KR920020516A - 아날로그·디지탈 혼재 집적회로 - Google Patents

아날로그·디지탈 혼재 집적회로 Download PDF

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Publication number
KR920020516A
KR920020516A KR1019920006748A KR920006748A KR920020516A KR 920020516 A KR920020516 A KR 920020516A KR 1019920006748 A KR1019920006748 A KR 1019920006748A KR 920006748 A KR920006748 A KR 920006748A KR 920020516 A KR920020516 A KR 920020516A
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KR
South Korea
Prior art keywords
analog
clock
digital
signal
unit
Prior art date
Application number
KR1019920006748A
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English (en)
Other versions
KR950005221B1 (ko
Inventor
야스시 히라타
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR920020516A publication Critical patent/KR920020516A/ko
Application granted granted Critical
Publication of KR950005221B1 publication Critical patent/KR950005221B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Microcomputers (AREA)

Abstract

내용 없음

Description

아날로그·디지탈 혼재 집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예를 나타낸 도면,
제2도는 본 발명의 제2실시예를 나타낸 도면,
제3도는 본 발명의 제3실시예를 나타낸 도면.

Claims (4)

  1. 아날로그신호를 처리해서 디지털신호로 변환시키는 아날로그부(11)와, 상기 디지털신호의 처리를 수행하는 디지털부(13), 상기 아날로그부(11)와 상기 디지털부(13)에 동작클럭신호(14A, 14D)를 공급하는 클럭신호 생성부(14)로 구성된 것을 특징으로 하는 아날로그·디지탈 혼재 집적회로에 있어서, 상기 아날로그(11)의 동작중에는 상기 디지털부(13)에 공급되는 동작클럭을 정지시키는 클럭정지 수단을 설치한 것을 특징으로 하는 아날로그·디지탈 혼재 집적회로.
  2. 제1항에 있어서, 상기 클럭정지수단은 상기 아날로그부(11)가 동작중인 것을 특징으로 나타내는 신호를 인가 받아서 상기 클럭신호 생성부(14)의 디지털부(13)에 대한 클럭신호공급을 정지시키도록 된 것을 특징으로 하는 아날로그·디지탈 혼재 집적회로.
  3. 제2항에 있어서, 상기 클럭정지수단(17)이 디지털부(13)내에 설치된 것을 특징으로 하는 아날로그·디지탈 혼재 집적회로.
  4. 제1항에 있어서, 상기 아날로그부(11)가 동작중인 것을 나타내는 신호가 외부회로의 동작을 정지시키기 위해 외부회로에도 공급되도록 된 것을 특징으로 하는 아날로그·디지탈 혼재 집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920006748A 1991-04-30 1992-04-22 아날로그 · 디지탈 혼재 집적회로 KR950005221B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-098823 1991-04-30
JP3098823A JP2777291B2 (ja) 1991-04-30 1991-04-30 アナログ・ディジタル混在集積回路

Publications (2)

Publication Number Publication Date
KR920020516A true KR920020516A (ko) 1992-11-21
KR950005221B1 KR950005221B1 (ko) 1995-05-22

Family

ID=14230024

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920006748A KR950005221B1 (ko) 1991-04-30 1992-04-22 아날로그 · 디지탈 혼재 집적회로

Country Status (3)

Country Link
US (1) US5373293A (ko)
JP (1) JP2777291B2 (ko)
KR (1) KR950005221B1 (ko)

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Publication number Priority date Publication date Assignee Title
JP3055192B2 (ja) 1991-03-18 2000-06-26 株式会社デンソー 音声認識装置
US5649160A (en) * 1995-05-23 1997-07-15 Microunity Systems Engineering, Inc. Noise reduction in integrated circuits and circuit assemblies
US5706004A (en) * 1995-09-18 1998-01-06 Phylon Communications, Inc. System for reducing noise coupling between digital and analog circuitry
US6091349A (en) * 1998-09-30 2000-07-18 Cirrus Logic, Inc. Noise management scheme for high-speed mixed-signal integrated circuits
US6963626B1 (en) 1998-10-02 2005-11-08 The Board Of Trustees Of The Leland Stanford Junior University Noise-reducing arrangement and method for signal processing
US6215432B1 (en) 1999-03-04 2001-04-10 Atmel Corporation Reducing digital switching noise in mixed signal IC's
US6137429A (en) * 1999-03-08 2000-10-24 Motorola, Inc. Circuit and method for attenuating noise in a data converter
JP2003037172A (ja) * 2001-07-23 2003-02-07 Niigata Seimitsu Kk アナログ・デジタル混載集積回路
JP3889659B2 (ja) * 2002-04-25 2007-03-07 株式会社ルネサステクノロジ Ａ／ｄ変換器
US7940202B1 (en) 2008-07-31 2011-05-10 Cypress Semiconductor Corporation Clocking analog components operating in a digital system
JP5371808B2 (ja) * 2010-01-26 2013-12-18 ルネサスエレクトロニクス株式会社 マイクロコンピュータ、半導体装置及びマイクロコンピュータ応用機器
CN103199862B (zh) * 2013-02-21 2016-06-22 四川电力科学研究院 一种用于模数混合录波的数据同步方法
KR20170001565U (ko) 2015-10-26 2017-05-10 최병석 옷감인장장치
DE102017110821A1 (de) 2016-01-25 2018-07-26 Samsung Electronics Co., Ltd. Halbleitervorrichtung
US10429881B2 (en) 2016-01-25 2019-10-01 Samsung Electronics Co., Ltd. Semiconductor device for stopping an oscillating clock signal from being provided to an IP block, a semiconductor system having the semiconductor device, and a method of operating the semiconductor device
US10248155B2 (en) 2016-01-25 2019-04-02 Samsung Electronics Co., Ltd. Semiconductor device including clock generating circuit and channel management circuit
US10303203B2 (en) 2016-01-25 2019-05-28 Samsung Electronics Co., Ltd. Semiconductor device, semiconductor system and method for operating semiconductor device
KR102467172B1 (ko) 2016-01-25 2022-11-14 삼성전자주식회사 반도체 장치
US10296066B2 (en) 2016-01-25 2019-05-21 Samsung Electronics Co., Ltd. Semiconductor device, semiconductor system, and method of operating the semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4303880A (en) * 1979-09-26 1981-12-01 Sangamo Weston, Inc. Gated precision offset circuit for a digital meter having a dual slope analog-to-digital converter
US4544914A (en) * 1979-12-17 1985-10-01 Trw Inc. Asynchronously controllable successive approximation analog-to-digital converter
WO1987004880A1 (en) * 1986-01-30 1987-08-13 Plessey Overseas Limited Analogue to digital conversion: method and apparatus therefor
JPS6458043A (en) * 1987-08-28 1989-03-06 Nec Corp Microcomputer incorporating a/d and d/a converters
US4990912A (en) * 1988-10-21 1991-02-05 Wavetek Rf Products, Inc. Digital peak/valley detector
JPH02297683A (ja) * 1989-05-11 1990-12-10 Nec Corp マイクロコンピュータ
DE3933491A1 (de) * 1989-10-06 1991-04-18 Endress Hauser Gmbh Co Anordnung zur umwandlung einer elektrischen eingangsgroesse in ein dazu proportionales elektrisches gleichsignal

Also Published As

Publication number Publication date
KR950005221B1 (ko) 1995-05-22
JP2777291B2 (ja) 1998-07-16
US5373293A (en) 1994-12-13
JPH04328624A (ja) 1992-11-17

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