KR920017357A - 지연회로 - Google Patents

지연회로 Download PDF

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Publication number
KR920017357A
KR920017357A KR1019920002591A KR920002591A KR920017357A KR 920017357 A KR920017357 A KR 920017357A KR 1019920002591 A KR1019920002591 A KR 1019920002591A KR 920002591 A KR920002591 A KR 920002591A KR 920017357 A KR920017357 A KR 920017357A
Authority
KR
South Korea
Prior art keywords
capacitance
delay circuit
collector
output terminal
capacitor
Prior art date
Application number
KR1019920002591A
Other languages
English (en)
Other versions
KR100195320B1 (ko
Inventor
다이스께 무라가미
Original Assignee
오가 노리오
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR920017357A publication Critical patent/KR920017357A/ko
Application granted granted Critical
Publication of KR100195320B1 publication Critical patent/KR100195320B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00169—Layout of the delay element using bipolar transistors using current mirrors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00176—Layout of the delay element using bipolar transistors using differential stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00228—Layout of the delay element having complementary input and output signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Networks Using Active Elements (AREA)
  • Pulse Circuits (AREA)

Abstract

내용 없음

Description

지연회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명에 의한 지연회로의 일실시예를 도시한 회로도.
제2도는 제1도의 회로를 간략적으로 표현한 등가회로도.
제3도는 본원발명의 시뮬레이션결과를 도시한 지연특성도.

Claims (2)

  1. 지연해야할 입력신호가 공급되는 입력단자와, 지연된 신호를 도출하는 출력단자와, 상기 입력단자와 상기 출력단자간에 삽입된 저항소자와, 단위용량을 C로 할 때 각각 C,2C,4C…, 2n-1C인 용량을 가지고 각 일단이 상기 저항소자의 출력단에 공통접속된 n단의 용량소자와, 상기 n단의 용량소자의 각 타단에 대해 상기 입력신호와 역상(逆相)또는 동상(同相)의 신호 또는 기준전위레벨을 선택적으로 인가하는 n개의 선택수단을 구비한 것을 특징으로 하는 지연회로.
  2. 제1항에 있어서, 상기 용량소자의 단위용량 C으로서 베이스-에미터간 또는 콜렉터-에미터간이 단락된 트랜지스터의 베이스-콜렉터간 결합용량 또는 콜렉터-기판간 접합용량을 사용한 것을 특징으로 하는 지연회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920002591A 1991-02-22 1992-02-21 지연회로 KR100195320B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-50473 1991-02-22
JP05047391A JP3225527B2 (ja) 1991-02-22 1991-02-22 遅延回路

Publications (2)

Publication Number Publication Date
KR920017357A true KR920017357A (ko) 1992-09-26
KR100195320B1 KR100195320B1 (ko) 1999-06-15

Family

ID=12859870

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920002591A KR100195320B1 (ko) 1991-02-22 1992-02-21 지연회로

Country Status (3)

Country Link
US (1) US5175454A (ko)
JP (1) JP3225527B2 (ko)
KR (1) KR100195320B1 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5465076A (en) * 1991-10-04 1995-11-07 Nippondenso Co., Ltd. Programmable delay line programmable delay circuit and digital controlled oscillator
US5262690A (en) * 1992-04-29 1993-11-16 International Business Machines Corporation Variable delay clock circuit
US5306971A (en) * 1992-07-23 1994-04-26 Proxim, Inc. Binary controlled digital tapped delay line
JP3550404B2 (ja) * 1992-09-10 2004-08-04 株式会社日立製作所 可変遅延回路及び可変遅延回路を用いたクロック信号供給装置
US6285197B2 (en) 1998-07-31 2001-09-04 Philips Electronics North America Corporation System and method for generating a jittered test signal

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866314A (en) * 1986-07-18 1989-09-12 Tektronix, Inc. Programmable high-speed digital delay circuit
JPH01119114A (ja) * 1987-10-31 1989-05-11 Sony Corp ディレイ回路
US4797586A (en) * 1987-11-25 1989-01-10 Tektronix, Inc. Controllable delay circuit
US5063311A (en) * 1990-06-04 1991-11-05 Motorola, Inc. Programmable time delay circuit for digital logic circuits

Also Published As

Publication number Publication date
JP3225527B2 (ja) 2001-11-05
KR100195320B1 (ko) 1999-06-15
JPH04268810A (ja) 1992-09-24
US5175454A (en) 1992-12-29

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