KR920005864B1 - 집적회로의 배치구조 - Google Patents
집적회로의 배치구조 Download PDFInfo
- Publication number
- KR920005864B1 KR920005864B1 KR1019890011494A KR890011494A KR920005864B1 KR 920005864 B1 KR920005864 B1 KR 920005864B1 KR 1019890011494 A KR1019890011494 A KR 1019890011494A KR 890011494 A KR890011494 A KR 890011494A KR 920005864 B1 KR920005864 B1 KR 920005864B1
- Authority
- KR
- South Korea
- Prior art keywords
- block
- control
- wiring
- functional block
- control signal
- Prior art date
Links
- 230000010354 integration Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000004821 distillation Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63200202A JP2790287B2 (ja) | 1988-08-12 | 1988-08-12 | 集積回路の配置構造 |
JP63-200202 | 1988-08-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900004002A KR900004002A (ko) | 1990-03-27 |
KR920005864B1 true KR920005864B1 (ko) | 1992-07-23 |
Family
ID=16420499
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890011494A KR920005864B1 (ko) | 1988-08-12 | 1989-08-12 | 집적회로의 배치구조 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2790287B2 (ja) |
KR (1) | KR920005864B1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9231895B2 (en) | 2012-10-23 | 2016-01-05 | International Business Machines Corporation | Tag management of information technology services improvement |
JP6384201B2 (ja) | 2014-08-28 | 2018-09-05 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56134745A (en) * | 1980-03-26 | 1981-10-21 | Nec Corp | Integrated circuit device |
JPS59127845A (ja) * | 1983-01-13 | 1984-07-23 | Seiko Epson Corp | 集積回路のテスト回路 |
JPS59149424A (ja) * | 1983-02-15 | 1984-08-27 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JPH0682801B2 (ja) * | 1983-12-23 | 1994-10-19 | 株式会社日立製作所 | 半導体記憶装置とそのレイアウト方法 |
JPS6244835A (ja) * | 1985-08-23 | 1987-02-26 | Hitachi Ltd | マイクロ・プロセツサ |
-
1988
- 1988-08-12 JP JP63200202A patent/JP2790287B2/ja not_active Expired - Lifetime
-
1989
- 1989-08-12 KR KR1019890011494A patent/KR920005864B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP2790287B2 (ja) | 1998-08-27 |
JPH0250459A (ja) | 1990-02-20 |
KR900004002A (ko) | 1990-03-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR970062923A (ko) | 마이크로컴퓨터 | |
US4665538A (en) | Bidirectional barrel shift circuit | |
JPS61198761A (ja) | 半導体集積回路 | |
JPH0828421B2 (ja) | 半導体集積回路装置 | |
KR920005864B1 (ko) | 집적회로의 배치구조 | |
US4093993A (en) | Bit-slice type large scale integrated circuit with multiple functions on a one-chip semiconductor device | |
KR970051163A (ko) | 반도체 메모리장치 | |
JPH02165386A (ja) | 描画処理装置及びその描画処理装置を用いた画像表示装置 | |
JPH077809B2 (ja) | 集積回路 | |
US5359212A (en) | Integrated circuit with layout effective for high-speed processing | |
KR0123261B1 (ko) | 집적회로장치 및 그의 설계방법 | |
KR100261201B1 (ko) | 반도체 집적회로 및 시스템 | |
US6249163B1 (en) | Logic circuits | |
JP2001229133A (ja) | 並列プロセッサ及びそれを用いた画像処理装置 | |
JPS59220948A (ja) | 半導体装置 | |
JP2006269900A (ja) | 半導体集積回路の設計方法 | |
US20030069914A1 (en) | Carry lookahead adder having a reduced fanout architecture | |
JPH027542A (ja) | 半導体集積回路 | |
JPS62107362A (ja) | システム構成用lsi | |
KR19980065642A (ko) | 반도체 메모리장치의 출력패드 배치방법 | |
JPS6022356A (ja) | 大規模集積回路 | |
JPH07226439A (ja) | 半導体集積回路 | |
JPH06112445A (ja) | ゲートアレイ装置 | |
JPH05102394A (ja) | 半導体集積回路装置 | |
JPH02283050A (ja) | 半導体集積回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030701 Year of fee payment: 12 |
|
LAPS | Lapse due to unpaid annual fee |