KR910016057A - 다결정 실리콘 완충층을 이용한 텅스텐 박막 제조방법 - Google Patents

다결정 실리콘 완충층을 이용한 텅스텐 박막 제조방법 Download PDF

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Publication number
KR910016057A
KR910016057A KR1019900002351A KR900002351A KR910016057A KR 910016057 A KR910016057 A KR 910016057A KR 1019900002351 A KR1019900002351 A KR 1019900002351A KR 900002351 A KR900002351 A KR 900002351A KR 910016057 A KR910016057 A KR 910016057A
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KR
South Korea
Prior art keywords
thin film
polycrystalline silicon
buffer layer
tungsten thin
film
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Application number
KR1019900002351A
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English (en)
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KR930005240B1 (ko
Inventor
김준기
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900002351A priority Critical patent/KR930005240B1/ko
Publication of KR910016057A publication Critical patent/KR910016057A/ko
Application granted granted Critical
Publication of KR930005240B1 publication Critical patent/KR930005240B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

내용 없음

Description

다결정 실리콘 완충층을 이용한 텅스텐 박막 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도(A)~(G)는 본 발명에 의한 다결정 실리콘 완충층을 이용한 텅스텐 박막 제조의 공정도.

Claims (1)

  1. 실리콘 소자(1)위에 산화막(2)을 입히는 산화막부 공정과, 텅스텐과의 접착성이 좋은 폴리막(5)을 웨이퍼의 앞면 및 뒷면에 입히는 폴리부 공정과, 사진 식각법에 의하여 접촉창(6)을 형성시키는 접촉창 형성 공정과 접착성 향상층(3)을 입히는 접착성 향상층 형성 공정과, 웨이퍼의 전면에 텅스텐 박막(4)을 입체로 전면 텅스텐 중착공정화, 접촉상(b)내부의 박막(4)만을 남기고 그위의 텅스텐 박막은 건식 식각하여 제거하는 건식 식각 공정과, 산화막(2)에 영향을 적게 주면서 혼합용액(HNO3, CH3CHOOH, HF)을 사용하여 폴리막(5)을 제거하는 폴리실리콘 제거 공정을 포함하여 이루어진 것을 특징으로 하는 다결정 실리콘 완충층을 이용한 텅스텐 박막 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900002351A 1990-02-23 1990-02-23 다결정 실리콘 완충층을 이용한 텅스텐 박막 제조방법 KR930005240B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900002351A KR930005240B1 (ko) 1990-02-23 1990-02-23 다결정 실리콘 완충층을 이용한 텅스텐 박막 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900002351A KR930005240B1 (ko) 1990-02-23 1990-02-23 다결정 실리콘 완충층을 이용한 텅스텐 박막 제조방법

Publications (2)

Publication Number Publication Date
KR910016057A true KR910016057A (ko) 1991-09-30
KR930005240B1 KR930005240B1 (ko) 1993-06-16

Family

ID=19296383

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900002351A KR930005240B1 (ko) 1990-02-23 1990-02-23 다결정 실리콘 완충층을 이용한 텅스텐 박막 제조방법

Country Status (1)

Country Link
KR (1) KR930005240B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100329206B1 (ko) * 1999-07-09 2002-03-22 방우영 계면층을 이용한 박막 성장법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100329206B1 (ko) * 1999-07-09 2002-03-22 방우영 계면층을 이용한 박막 성장법

Also Published As

Publication number Publication date
KR930005240B1 (ko) 1993-06-16

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