KR910005597B1 - 분할된 정류회로를 가진 반도체 기억장치 - Google Patents

분할된 정류회로를 가진 반도체 기억장치 Download PDF

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Publication number
KR910005597B1
KR910005597B1 KR1019840003724A KR840003724A KR910005597B1 KR 910005597 B1 KR910005597 B1 KR 910005597B1 KR 1019840003724 A KR1019840003724 A KR 1019840003724A KR 840003724 A KR840003724 A KR 840003724A KR 910005597 B1 KR910005597 B1 KR 910005597B1
Authority
KR
South Korea
Prior art keywords
pads
pad
semiconductor memory
bonding
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019840003724A
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English (en)
Korean (ko)
Other versions
KR850000124A (ko
Inventor
요시히로 다께마에
도미오 나까노
기미아끼 사또오
Original Assignee
후지쓰 가부시끼가이샤
야마모도 다꾸마
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰 가부시끼가이샤, 야마모도 다꾸마 filed Critical 후지쓰 가부시끼가이샤
Publication of KR850000124A publication Critical patent/KR850000124A/ko
Application granted granted Critical
Publication of KR910005597B1 publication Critical patent/KR910005597B1/ko
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)
KR1019840003724A 1983-06-29 1984-06-29 분할된 정류회로를 가진 반도체 기억장치 Expired KR910005597B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58115878A JPS609152A (ja) 1983-06-29 1983-06-29 半導体装置
JP115878 1983-06-29

Publications (2)

Publication Number Publication Date
KR850000124A KR850000124A (ko) 1985-02-25
KR910005597B1 true KR910005597B1 (ko) 1991-07-31

Family

ID=14673401

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840003724A Expired KR910005597B1 (ko) 1983-06-29 1984-06-29 분할된 정류회로를 가진 반도체 기억장치

Country Status (5)

Country Link
US (1) US4660174A (enExample)
EP (1) EP0130798B1 (enExample)
JP (1) JPS609152A (enExample)
KR (1) KR910005597B1 (enExample)
DE (1) DE3485625D1 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3585756D1 (de) * 1984-07-02 1992-05-07 Fujitsu Ltd Halbleiterschaltungsanordnung in hauptscheibentechnik.
JPH0652784B2 (ja) * 1984-12-07 1994-07-06 富士通株式会社 ゲートアレイ集積回路装置及びその製造方法
JPS61227289A (ja) * 1985-03-30 1986-10-09 Fujitsu Ltd 半導体記憶装置
EP0204177A1 (de) * 1985-05-31 1986-12-10 Siemens Aktiengesellschaft Anschlussanordnung für einen integrierten Halbleiterschaltkreis
JPS62122139A (ja) * 1985-11-21 1987-06-03 Nec Corp 半導体記憶装置
JP2659179B2 (ja) * 1985-12-20 1997-09-30 日本電気株式会社 半導体記憶装置
JPS62180594A (ja) * 1986-02-04 1987-08-07 Fujitsu Ltd 半導体記憶装置
JPS62192086A (ja) * 1986-02-18 1987-08-22 Matsushita Electronics Corp 半導体記憶装置
US5265045A (en) * 1986-10-31 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit device with built-in memory circuit group
JPS6379871U (enExample) * 1986-11-14 1988-05-26
US5243208A (en) * 1987-05-27 1993-09-07 Hitachi, Ltd. Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
US5287000A (en) * 1987-10-20 1994-02-15 Hitachi, Ltd. Resin-encapsulated semiconductor memory device useful for single in-line packages
EP0317666B1 (en) * 1987-11-23 1992-02-19 Koninklijke Philips Electronics N.V. Fast operating static ram memory with high storage capacity
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
JP2585738B2 (ja) * 1988-08-12 1997-02-26 株式会社日立製作所 半導体記憶装置
JPH081945B2 (ja) * 1988-10-24 1996-01-10 日本電気株式会社 半導体記憶装置
US5278802A (en) * 1988-10-28 1994-01-11 Texas Instruments Incorporated Decoding global drive/boot signals using local predecoders
JPH0772991B2 (ja) * 1988-12-06 1995-08-02 三菱電機株式会社 半導体記憶装置
US6069814A (en) * 1989-05-26 2000-05-30 Texas Instruments Incorporated Multiple input buffers for address bits
JP2542706B2 (ja) * 1989-10-05 1996-10-09 株式会社東芝 ダイナミックｒａｍ
ATE101746T1 (de) * 1989-11-24 1994-03-15 Siemens Ag Halbleiterspeicher.
JP3242101B2 (ja) * 1990-10-05 2001-12-25 三菱電機株式会社 半導体集積回路
JPH05308136A (ja) * 1992-04-01 1993-11-19 Nec Corp マスタスライス集積回路
JP3073610B2 (ja) * 1992-09-22 2000-08-07 株式会社東芝 半導体記憶装置
US5517442A (en) 1995-03-13 1996-05-14 International Business Machines Corporation Random access memory and an improved bus arrangement therefor
US5936877A (en) 1998-02-13 1999-08-10 Micron Technology, Inc. Die architecture accommodating high-speed semiconductor devices
DE19907922C1 (de) 1999-02-24 2000-09-28 Siemens Ag Leseverstärkeranordnung mit gemeinsamen durchgehendem Diffusionsgebiet der Leseverstärker-Transistoren
KR100380409B1 (ko) * 2001-01-18 2003-04-11 삼성전자주식회사 반도체 메모리 소자의 패드배열구조 및 그의 구동방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals
US4527254A (en) * 1982-11-15 1985-07-02 International Business Machines Corporation Dynamic random access memory having separated VDD pads for improved burn-in

Also Published As

Publication number Publication date
EP0130798B1 (en) 1992-04-01
JPS64822B2 (enExample) 1989-01-09
EP0130798A3 (en) 1988-08-31
EP0130798A2 (en) 1985-01-09
US4660174A (en) 1987-04-21
JPS609152A (ja) 1985-01-18
DE3485625D1 (de) 1992-05-07
KR850000124A (ko) 1985-02-25

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