KR900019132A - 웨이퍼 얼라인먼트 마크 및 그 제조방법 - Google Patents

웨이퍼 얼라인먼트 마크 및 그 제조방법

Info

Publication number
KR900019132A
KR900019132A KR1019900006912A KR900006912A KR900019132A KR 900019132 A KR900019132 A KR 900019132A KR 1019900006912 A KR1019900006912 A KR 1019900006912A KR 900006912 A KR900006912 A KR 900006912A KR 900019132 A KR900019132 A KR 900019132A
Authority
KR
South Korea
Prior art keywords
manufacturing
alignment mark
wafer alignment
wafer
mark
Prior art date
Application number
KR1019900006912A
Other languages
English (en)
Other versions
KR0177148B1 (ko
Inventor
료이찌 마쯔모도
도시가주 구로다
다까오 가또
Original Assignee
오끼뎅끼 고오교오 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1120532A external-priority patent/JPH02301121A/ja
Priority claimed from JP1124393A external-priority patent/JPH02304912A/ja
Application filed by 오끼뎅끼 고오교오 가부시끼가이샤 filed Critical 오끼뎅끼 고오교오 가부시끼가이샤
Publication of KR900019132A publication Critical patent/KR900019132A/ko
Application granted granted Critical
Publication of KR0177148B1 publication Critical patent/KR0177148B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
KR1019900006912A 1989-05-16 1990-05-15 웨이퍼 얼라인먼트 마크 및 그 제조방법 KR0177148B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP1120532A JPH02301121A (ja) 1989-05-16 1989-05-16 アライメントマーク
JP1-120532 1989-05-16
JP1124393A JPH02304912A (ja) 1989-05-19 1989-05-19 半導体装置の製造方法
JP1-124393 1989-05-19

Publications (2)

Publication Number Publication Date
KR900019132A true KR900019132A (ko) 1990-12-24
KR0177148B1 KR0177148B1 (ko) 1999-04-15

Family

ID=26458098

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900006912A KR0177148B1 (ko) 1989-05-16 1990-05-15 웨이퍼 얼라인먼트 마크 및 그 제조방법

Country Status (2)

Country Link
US (2) US5106432A (ko)
KR (1) KR0177148B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970051926A (ko) * 1995-12-29 1997-07-29

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0478123A (ja) * 1990-07-20 1992-03-12 Fujitsu Ltd 半導体装置の製造方法
FR2667440A1 (fr) * 1990-09-28 1992-04-03 Philips Nv Procede pour realiser des motifs d'alignement de masques.
KR100289348B1 (ko) * 1992-05-25 2001-12-28 이데이 노부유끼 절연기판실리콘반도체장치와그제조방법
US5314837A (en) * 1992-06-08 1994-05-24 Analog Devices, Incorporated Method of making a registration mark on a semiconductor
US5270255A (en) * 1993-01-08 1993-12-14 Chartered Semiconductor Manufacturing Pte, Ltd. Metallization process for good metal step coverage while maintaining useful alignment mark
US5474640A (en) * 1993-07-19 1995-12-12 Applied Materials, Inc. Apparatus for marking a substrate using ionized gas
US5580831A (en) * 1993-07-28 1996-12-03 Fujitsu Limited Sawcut method of forming alignment marks on two faces of a substrate
KR960014963B1 (ko) * 1993-10-15 1996-10-23 현대전자산업 주식회사 반도체 장치의 제조 방법
US5903330A (en) * 1995-10-31 1999-05-11 Rolic Ag Optical component with plural orientation layers on the same substrate wherein the surfaces of the orientation layers have different patterns and direction
JP2842360B2 (ja) * 1996-02-28 1999-01-06 日本電気株式会社 半導体装置およびその製造方法
US5748827A (en) * 1996-10-23 1998-05-05 University Of Washington Two-stage kinematic mount
US5902452A (en) * 1997-03-13 1999-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method for etching silicon surface
US5956564A (en) 1997-06-03 1999-09-21 Ultratech Stepper, Inc. Method of making a side alignment mark
US5874778A (en) * 1997-06-11 1999-02-23 International Business Machines Corporation Embedded power and ground plane structure
US5943587A (en) * 1997-06-25 1999-08-24 International Business Machines Corporation Method for making offset alignment marks
KR100307630B1 (ko) 1998-12-30 2001-09-28 윤종용 정렬 마크, 이를 사용하는 정렬 시스템 및 이를 이용한 정렬방법
JP3348783B2 (ja) * 1999-07-28 2002-11-20 日本電気株式会社 重ね合わせ用マーク及び半導体装置
WO2001009927A1 (en) * 1999-07-28 2001-02-08 Infineon Technologies North America Corp. Semiconductor structures and manufacturing methods
US6950188B2 (en) * 2003-04-23 2005-09-27 International Business Machines Corporation Wafer alignment system using parallel imaging detection
FR2869459B1 (fr) * 2004-04-21 2006-08-04 Commissariat Energie Atomique Realignement entre niveaux apres une etape d'epitaxie.
JP4982125B2 (ja) * 2006-07-11 2012-07-25 株式会社東芝 欠陥検査方法及びパターン抽出方法
JP2009302309A (ja) * 2008-06-13 2009-12-24 Elpida Memory Inc アライメントマーク構造およびこれを用いた位置合わせ方法
US8947664B2 (en) * 2009-12-23 2015-02-03 Infineon Technologies Ag Apparatus and method for aligning a wafer's backside to a wafer's frontside
US9646902B2 (en) * 2013-08-12 2017-05-09 Taiwan Semiconductor Manufacturing Company Limited Paired edge alignment
US9472506B2 (en) 2015-02-25 2016-10-18 International Business Machines Corporation Registration mark formation during sidewall image transfer process
US9653404B1 (en) 2016-08-23 2017-05-16 United Microelectronics Corp. Overlay target for optically measuring overlay alignment of layers formed on semiconductor wafer
US10833072B1 (en) 2019-05-06 2020-11-10 Globalfoundries Inc. Heterojunction bipolar transistors having bases with different elevations

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3796497A (en) * 1971-12-01 1974-03-12 Ibm Optical alignment method and apparatus
US4200395A (en) * 1977-05-03 1980-04-29 Massachusetts Institute Of Technology Alignment of diffraction gratings
FR2566179B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement
US4534804A (en) * 1984-06-14 1985-08-13 International Business Machines Corporation Laser process for forming identically positioned alignment marks on the opposite sides of a semiconductor wafer
US4824795A (en) * 1985-12-19 1989-04-25 Siliconix Incorporated Method for obtaining regions of dielectrically isolated single crystal silicon
US4936930A (en) * 1988-01-06 1990-06-26 Siliconix Incorporated Method for improved alignment for semiconductor devices with buried layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970051926A (ko) * 1995-12-29 1997-07-29

Also Published As

Publication number Publication date
US5106432A (en) 1992-04-21
KR0177148B1 (ko) 1999-04-15
US5128280A (en) 1992-07-07

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