KR900017100A - 반도체 웨이퍼 후면 처리방법 - Google Patents

반도체 웨이퍼 후면 처리방법 Download PDF

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KR900017100A
KR900017100A KR1019900005099A KR900005099A KR900017100A KR 900017100 A KR900017100 A KR 900017100A KR 1019900005099 A KR1019900005099 A KR 1019900005099A KR 900005099 A KR900005099 A KR 900005099A KR 900017100 A KR900017100 A KR 900017100A
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wafer
cathode
plasma
semiconductor wafer
semiconductor
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KR1019900005099A
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창 메이
쳉 데이빗
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제임스 조셉 드롱
어플라이드 머티어리얼, 인코포레이션
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Publication of KR900017100A publication Critical patent/KR900017100A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/08—Preparation of the foundation plate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/021—Cleaning or etching treatments
    • C23C14/022—Cleaning or etching treatments by means of bombardment with energetic particles or radiation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
    • C23C16/0245—Pretreatment of the material to be coated by cleaning or etching by etching with a plasma
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C8/00—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals
    • C23C8/06—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases
    • C23C8/36—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases using ionised gases, e.g. ionitriding
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing

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Abstract

내용 없음

Description

반도체 웨이퍼 후면 처리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 방법을 설명하는 계통도,
제2도는 도전 캐소드(10)에서 부터 반도체 웨이퍼 하면(34)까지 일정한 거리 간격을 두기위해 지지핀들의 사용을나타내는, 웨이퍼 후면 처리에 이용된 장치의 수직 부분 단면도,
제3도는 제2도에 나타낸 웨이퍼의 하부에 있어서 지지핀들의 정형적인 위치 또는 배열을 나타내는 반도체 웨이퍼의 평면도.

Claims (9)

  1. 캐소드와 대면해 있는 웨이퍼 후면을 갖는 반도체 웨이퍼를 캐소드로부터 일정한 거리를 둔 상태에 유지하는 단계와, 상기 반도체 웨이퍼을 처리하기 위해, 상기 캐소드와 상기 웨이퍼 후면 사이에 형성되는 공간에 플라즈마를 형성하는 단계로 구성되는, 반도체 웨이퍼 후면 처리 방법.
  2. 제1항에 있어서, 상기 캐소드에서부터 상기 웨이퍼 후면까지의 거리 간격을 약 0.25내지 1인치로 구성되는 캐소드로 부터 거리 간격을 둔 반도체 웨이퍼를 설치하는 단계로 구성되는 것을 특징으로 하는, 반도체 후면 처리 방법.
  3. 제2항에 있어서, 상기 공정이 50내지 300밀리토르 압력의 진공에서 유지되는 진공 챔버 내에서 행해지는 것을 특징으로 하는, 반도체 후면 처리방법.
  4. 제3항에 있어서, 상기 플라즈마를 상기 웨이퍼 후면에 실질적으로 한정하기위해 25내지 100와트로 고주파 발전기를 유지하는 것을 특징으로 하는, 반도체 후면 처리방법.
  5. 제4항에 있어서, 10초 내지 3분의 시간동안 상기 웨이퍼 후면과 상기 캐소드사이에 플라즈마를 유지하는 것으로 이루어진 플라즈마를 형성하는 단계로 구성되는 것을 특징으로 하는, 반도체 후면 처리방법.
  6. 제5항에 있어서, 50내지 200㎤의 비활성 기체를 웨이퍼를 통해 흘러보내는 것을 포함하는 상기 플라즈마를 형성하는 단계로 구성되는 것을 특징으로 하는. 반도체 후면 처리방법.
  7. 제6항에 있어서, 비활성 기체는 아르곤, 네온 및 헬륨 중에 선택하는 것을 특징으로 하는, 반도체 후면 처리 방법.
  8. 제5항에 있어서, 상기 웨이퍼 후면상에 약 10내지 30A의 산화물 층을 형성하기 위해 약 20내지 200㎤양의 산화 기체를 챔버를 통해 흘러 보내는 것을 포함하는 상기 플라즈마를 형성하는 단계로 구성되는 것을 특징으로 하는, 반도체 후면 처리방법.
  9. 제8항에 있어서, 상기 산화 기체는 02, N2O, 03와 CO2중에서 선택하는 것을 특징으로 하는 반도체 후면 처리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900005099A 1989-04-13 1990-04-13 반도체 웨이퍼 후면 처리방법 KR900017100A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/337,607 US4962049A (en) 1989-04-13 1989-04-13 Process for the plasma treatment of the backside of a semiconductor wafer
US337,607 1989-04-13

Publications (1)

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KR900017100A true KR900017100A (ko) 1990-11-15

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Country Link
US (1) US4962049A (ko)
EP (1) EP0392134A3 (ko)
JP (1) JPH0642480B2 (ko)
KR (1) KR900017100A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9487900B2 (en) 2009-03-20 2016-11-08 Lg Electronics Inc. Washing machine

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5213650A (en) * 1989-08-25 1993-05-25 Applied Materials, Inc. Apparatus for removing deposits from backside and end edge of semiconductor wafer while preventing removal of materials from front surface of wafer
US5075256A (en) * 1989-08-25 1991-12-24 Applied Materials, Inc. Process for removing deposits from backside and end edge of semiconductor wafer while preventing removal of materials from front surface of wafer
JPH04162422A (ja) * 1990-10-24 1992-06-05 Fujitsu Ltd 半導体装置の製造装置
DE4109955A1 (de) * 1991-03-26 1992-10-01 Siemens Ag Verfahren zum nasschemischen aetzen einer wolframrueckseitenbeschichtung auf einer halbleiterscheibe
US5340770A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method of making a shallow junction by using first and second SOG layers
US5533635A (en) * 1994-10-11 1996-07-09 Chartered Semiconductor Manufacturing Pte. Ltd. Method of wafer cleaning after metal etch
US6239038B1 (en) 1995-10-13 2001-05-29 Ziying Wen Method for chemical processing semiconductor wafers
US5926689A (en) * 1995-12-19 1999-07-20 International Business Machines Corporation Process for reducing circuit damage during PECVD in single wafer PECVD system
JP3942672B2 (ja) * 1996-04-12 2007-07-11 キヤノンアネルバ株式会社 基板処理方法および基板処理装置
US6413436B1 (en) * 1999-01-27 2002-07-02 Semitool, Inc. Selective treatment of the surface of a microelectronic workpiece
US5780363A (en) * 1997-04-04 1998-07-14 International Business Machines Coporation Etching composition and use thereof
US5965465A (en) * 1997-09-18 1999-10-12 International Business Machines Corporation Etching of silicon nitride
US6150282A (en) * 1997-11-13 2000-11-21 International Business Machines Corporation Selective removal of etching residues
US6033996A (en) * 1997-11-13 2000-03-07 International Business Machines Corporation Process for removing etching residues, etching mask and silicon nitride and/or silicon dioxide
US20050217707A1 (en) * 1998-03-13 2005-10-06 Aegerter Brian K Selective processing of microelectronic workpiece surfaces
US6632292B1 (en) 1998-03-13 2003-10-14 Semitool, Inc. Selective treatment of microelectronic workpiece surfaces
US6423642B1 (en) * 1998-03-13 2002-07-23 Semitool, Inc. Reactor for processing a semiconductor wafer
US6335293B1 (en) * 1998-07-13 2002-01-01 Mattson Technology, Inc. Systems and methods for two-sided etch of a semiconductor substrate
US6117796A (en) * 1998-08-13 2000-09-12 International Business Machines Corporation Removal of silicon oxide
US6200891B1 (en) 1998-08-13 2001-03-13 International Business Machines Corporation Removal of dielectric oxides
US6248642B1 (en) 1999-06-24 2001-06-19 Ibis Technology Corporation SIMOX using controlled water vapor for oxygen implants
US6452195B1 (en) 1999-08-18 2002-09-17 Ibis Technology Corporation Wafer holding pin
US6423975B1 (en) 1999-08-18 2002-07-23 Ibis Technology, Inc. Wafer holder for simox processing
US6155436A (en) * 1999-08-18 2000-12-05 Ibis Technology Corporation Arc inhibiting wafer holder assembly
US6433342B1 (en) 1999-08-18 2002-08-13 Ibis Technology Corporation Coated wafer holding pin
US6184154B1 (en) * 1999-10-13 2001-02-06 Seh America, Inc. Method of processing the backside of a wafer within an epitaxial reactor chamber
US6376156B1 (en) * 1999-11-22 2002-04-23 Taiwan Semiconductor Manufacturing Company Prevent defocus issue on wafer with tungsten coating on back-side
DE10024710A1 (de) * 2000-05-18 2001-12-20 Steag Rtp Systems Gmbh Einstellung von Defektprofilen in Kristallen oder kristallähnlichen Strukturen
JP2002118027A (ja) 2000-10-10 2002-04-19 Anelva Corp 磁性膜形成装置および磁性膜形成方法
US7628864B2 (en) * 2004-04-28 2009-12-08 Tokyo Electron Limited Substrate cleaning apparatus and method
US7597816B2 (en) * 2004-09-03 2009-10-06 Lam Research Corporation Wafer bevel polymer removal
US20060137711A1 (en) * 2004-12-27 2006-06-29 Kun-Yuan Liao Single-wafer cleaning procedure
US20070272270A1 (en) * 2004-12-27 2007-11-29 Kun-Yuan Liao Single-wafer cleaning procedure
US7465680B2 (en) * 2005-09-07 2008-12-16 Applied Materials, Inc. Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2
US7993465B2 (en) * 2006-09-07 2011-08-09 Applied Materials, Inc. Electrostatic chuck cleaning during semiconductor substrate processing
US20080060741A1 (en) * 2006-09-07 2008-03-13 Privitera Marc P Ultrasonically Bonded Nonwoven Permeable Pouch
US8268081B2 (en) * 2008-10-02 2012-09-18 Varian Semiconductor Equipment Associates, Inc. Platen cleaning method
JP2010263244A (ja) * 2010-08-11 2010-11-18 Tokyo Electron Ltd プラズマ処理方法
US10020187B2 (en) 2012-11-26 2018-07-10 Applied Materials, Inc. Apparatus and methods for backside passivation
CN103077883B (zh) * 2013-01-11 2016-08-24 武汉新芯集成电路制造有限公司 一种背照式cmos影像传感器制作方法
CN103077952B (zh) * 2013-01-11 2016-02-10 武汉新芯集成电路制造有限公司 一种影像传感器的制造方法
WO2018119959A1 (zh) * 2016-12-29 2018-07-05 深圳市柔宇科技有限公司 干蚀刻设备

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3907660A (en) * 1970-07-31 1975-09-23 Ppg Industries Inc Apparatus for coating glass
US4113599A (en) * 1977-09-26 1978-09-12 Ppg Industries, Inc. Sputtering technique for the deposition of indium oxide
US4300989A (en) * 1979-10-03 1981-11-17 Bell Telephone Laboratories, Incorporated Fluorine enhanced plasma growth of native layers on silicon
US4572841A (en) * 1984-12-28 1986-02-25 Rca Corporation Low temperature method of deposition silicon dioxide
US4664938A (en) * 1985-05-06 1987-05-12 Phillips Petroleum Company Method for deposition of silicon
US4624728A (en) * 1985-06-11 1986-11-25 Tegal Corporation Pin lift plasma processing
US4692344A (en) * 1986-02-28 1987-09-08 Rca Corporation Method of forming a dielectric film and semiconductor device including said film
US4687682A (en) * 1986-05-02 1987-08-18 American Telephone And Telegraph Company, At&T Technologies, Inc. Back sealing of silicon wafers
US4736087A (en) * 1987-01-12 1988-04-05 Olin Corporation Plasma stripper with multiple contact point cathode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9487900B2 (en) 2009-03-20 2016-11-08 Lg Electronics Inc. Washing machine

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