KR900015286A - 반도체장치내의 소자 배치방법 - Google Patents

반도체장치내의 소자 배치방법

Info

Publication number
KR900015286A
KR900015286A KR1019900003458A KR900003458A KR900015286A KR 900015286 A KR900015286 A KR 900015286A KR 1019900003458 A KR1019900003458 A KR 1019900003458A KR 900003458 A KR900003458 A KR 900003458A KR 900015286 A KR900015286 A KR 900015286A
Authority
KR
South Korea
Prior art keywords
semiconductor devices
arranging elements
arranging
elements
semiconductor
Prior art date
Application number
KR1019900003458A
Other languages
English (en)
Other versions
KR930003279B1 (ko
Inventor
세이시 니시오까
아쯔히꼬 오까다
Original Assignee
후지쓰 가부시끼기이샤
후지쓰 브이 엘 에스 아이 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰 가부시끼기이샤, 후지쓰 브이 엘 에스 아이 가부시끼가이샤 filed Critical 후지쓰 가부시끼기이샤
Publication of KR900015286A publication Critical patent/KR900015286A/ko
Application granted granted Critical
Publication of KR930003279B1 publication Critical patent/KR930003279B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1019900003458A 1989-03-15 1990-03-15 반도체장치내의 소자 배치방법 KR930003279B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1062831A JP2664465B2 (ja) 1989-03-15 1989-03-15 半導体装置のセル配置方法
JP01-062831 1989-03-15

Publications (2)

Publication Number Publication Date
KR900015286A true KR900015286A (ko) 1990-10-26
KR930003279B1 KR930003279B1 (ko) 1993-04-24

Family

ID=13211661

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900003458A KR930003279B1 (ko) 1989-03-15 1990-03-15 반도체장치내의 소자 배치방법

Country Status (5)

Country Link
US (1) US5519631A (ko)
EP (1) EP0388189B1 (ko)
JP (1) JP2664465B2 (ko)
KR (1) KR930003279B1 (ko)
DE (1) DE69027239T2 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367469A (en) * 1990-12-13 1994-11-22 Vlsi Technology, Inc. Predictive capacitance layout method for integrated circuits
JP3986717B2 (ja) * 1999-12-01 2007-10-03 富士通株式会社 パス決定方法及び記憶媒体
JP3433731B2 (ja) * 2000-11-10 2003-08-04 セイコーエプソン株式会社 Ｉ／ｏセル配置方法及び半導体装置
JP2004040447A (ja) * 2002-07-03 2004-02-05 Toyota Industries Corp Ａｇｃ回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4694403A (en) * 1983-08-25 1987-09-15 Nec Corporation Equalized capacitance wiring method for LSI circuits
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates
US4630219A (en) * 1983-11-23 1986-12-16 International Business Machines Corporation Element placement method
US4686629A (en) * 1984-05-10 1987-08-11 Rca Corporation Logic cell placement method in computer-aided-customization of universal arrays and resulting integrated circuit
JPS6156435A (ja) * 1984-07-25 1986-03-22 Fujitsu Ltd 半導体集積回路装置に於ける配線長予測方法
JPH0679319B2 (ja) * 1985-04-10 1994-10-05 株式会社日立製作所 配置更新方法
US4924430A (en) * 1988-01-28 1990-05-08 Teradyne, Inc. Static timing analysis of semiconductor digital circuits

Also Published As

Publication number Publication date
DE69027239D1 (de) 1996-07-11
EP0388189B1 (en) 1996-06-05
DE69027239T2 (de) 1996-10-02
US5519631A (en) 1996-05-21
EP0388189A2 (en) 1990-09-19
JP2664465B2 (ja) 1997-10-15
EP0388189A3 (en) 1991-07-10
KR930003279B1 (ko) 1993-04-24
JPH02241062A (ja) 1990-09-25

Similar Documents

Publication Publication Date Title
KR900008644A (ko) 반도체 장치 제조 방법
KR910008793A (ko) 반도체장치 및 그 제조방법
KR880701023A (ko) 반도체 장치 제조 방법
KR880004552A (ko) 반도체장치 제조방법
KR910007164A (ko) 반도체장치 및 그 제조방법
KR900019215A (ko) 반도체장치 및 그의 제조방법
KR890015368A (ko) 반도체장치 제조방법
KR880701457A (ko) 반도체 장치 제조 방법
KR910010653A (ko) 전자 장치의 리드 세정 방법
KR900012352A (ko) 반도체장치 패키지 및 그 패키지의 제조방법
KR910001871A (ko) 반도체 소자 제조방법
KR900015301A (ko) 반도체장치 및 그 제조방법
DE69031609D1 (de) Halbleiteranordnung
KR900015282A (ko) 반도체 소자의 제조방법
KR900015277A (ko) 반도체장치 및 그 제조방법
KR900019242A (ko) 반도체장치 및 그 제조방법
DE69029226D1 (de) Halbleiteranordnung
DE69125498D1 (de) Halbleiterverrichtungsherstellungsverfahren
KR900015286A (ko) 반도체장치내의 소자 배치방법
KR870009470A (ko) 반도체 장치 제조 방법
KR900019159A (ko) 반도체장치 제조방법
DE69025825D1 (de) Halbleiteranordnung
DE69027586D1 (de) Halbleiteranordnung
KR890015360A (ko) 반도체장치 및 그 제조방법
KR900015310A (ko) 반도체장치와 그 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010418

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee