KR900007226B1 - 반도체 메모리 장치 - Google Patents
반도체 메모리 장치 Download PDFInfo
- Publication number
- KR900007226B1 KR900007226B1 KR1019850007804A KR850007804A KR900007226B1 KR 900007226 B1 KR900007226 B1 KR 900007226B1 KR 1019850007804 A KR1019850007804 A KR 1019850007804A KR 850007804 A KR850007804 A KR 850007804A KR 900007226 B1 KR900007226 B1 KR 900007226B1
- Authority
- KR
- South Korea
- Prior art keywords
- data
- registers
- circuit
- output
- gates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP221165 | 1984-10-23 | ||
| JP59221165A JPS61104391A (ja) | 1984-10-23 | 1984-10-23 | 半導体記憶装置 |
| JP59-221165 | 1984-10-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR860003611A KR860003611A (ko) | 1986-05-28 |
| KR900007226B1 true KR900007226B1 (ko) | 1990-10-05 |
Family
ID=16762485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019850007804A Expired KR900007226B1 (ko) | 1984-10-23 | 1985-10-23 | 반도체 메모리 장치 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4740922A (enExample) |
| EP (1) | EP0188059B1 (enExample) |
| JP (1) | JPS61104391A (enExample) |
| KR (1) | KR900007226B1 (enExample) |
| DE (1) | DE3585733D1 (enExample) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270981A (en) * | 1985-07-30 | 1993-12-14 | Kabushiki Kaisha Toshiba | Field memory device functioning as a variable stage shift register with gated feedback from its output to its input |
| JPS6243744A (ja) * | 1985-08-21 | 1987-02-25 | Nec Corp | マイクロコンピユ−タ |
| JPS6314395A (ja) * | 1986-07-04 | 1988-01-21 | Nec Corp | 記憶回路 |
| GB8616852D0 (en) * | 1986-07-10 | 1986-08-20 | Hughes Microelectronics Ltd | Electronic counter |
| US4891752A (en) * | 1987-03-03 | 1990-01-02 | Tandon Corporation | Multimode expanded memory space addressing system using independently generated DMA channel selection and DMA page address signals |
| US4849875A (en) * | 1987-03-03 | 1989-07-18 | Tandon Corporation | Computer address modification system with optional DMA paging |
| US5101339A (en) * | 1987-08-10 | 1992-03-31 | Tandon Corporation | Computer address modification system using writable mapping and page stores |
| WO1989001662A1 (en) * | 1987-08-10 | 1989-02-23 | Tandon Corporation | Computer system providing address modification for use also with dma and interrupts |
| DE3733012A1 (de) * | 1987-09-30 | 1989-04-13 | Thomson Brandt Gmbh | Speicheranordnung |
| JP2542248B2 (ja) * | 1988-11-17 | 1996-10-09 | 三菱電機株式会社 | 半導体記憶装置 |
| US4980828A (en) * | 1988-11-25 | 1990-12-25 | Picker International, Inc. | Medical imaging system including use of DMA control for selective bit mapping of DRAM and VRAM memories |
| US5214761A (en) * | 1989-05-08 | 1993-05-25 | Wang Laboratories, Inc. | Real-time adjustable-transform device driver for physical devices |
| DE69023334T2 (de) * | 1989-05-08 | 1996-07-18 | Wang Laboratories, Inc., Lowell, Mass. | In echtzeit regelbarer transformier-modul für eingabevorrichtungen. |
| US5167029A (en) * | 1989-12-13 | 1992-11-24 | International Business Machines Corporation | Data processing system and associated process using memory cards having data modify functions utilizing a data mask and an internal register |
| EP0446847B1 (en) * | 1990-03-12 | 1998-06-17 | Nec Corporation | Semiconductor memory device having improved write function |
| JP2604276B2 (ja) * | 1990-11-20 | 1997-04-30 | 三菱電機株式会社 | 半導体記憶装置 |
| US5270970A (en) * | 1991-03-15 | 1993-12-14 | Motorola, Inc. | Memory device having a buffer for gating data transmissions |
| DE4228213C2 (de) * | 1991-09-19 | 1997-05-15 | Siemens Ag | Integrierte Halbleiterspeicherschaltung und Verfahren zu ihrem Betreiben |
| JPH06111010A (ja) * | 1992-09-29 | 1994-04-22 | Ricoh Co Ltd | Dram及びコントローラ |
| WO1995010804A1 (en) * | 1993-10-12 | 1995-04-20 | Wang Laboratories, Inc. | Hardware assisted modify count instruction |
| US5802586A (en) * | 1995-02-27 | 1998-09-01 | Motorola, Inc. | Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor |
| US6804162B1 (en) | 2001-04-05 | 2004-10-12 | T-Ram, Inc. | Read-modify-write memory using read-or-write banks |
| DE10340861A1 (de) * | 2003-09-04 | 2005-04-07 | Infineon Technologies Ag | Prozessorschaltung und Verfahren zum Zuordnen eines Logikchips zu einem Speicherchip |
| US7212431B2 (en) * | 2004-12-29 | 2007-05-01 | Hynix Semiconductor Inc. | Nonvolatile ferroelectric memory device and control method thereof |
| US9350386B2 (en) | 2012-04-12 | 2016-05-24 | Samsung Electronics Co., Ltd. | Memory device, memory system, and method of operating the same |
| KR20220106307A (ko) | 2021-01-22 | 2022-07-29 | 삼성전자주식회사 | 스토리지 장치 및 그 구동 방법 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3763480A (en) * | 1971-10-12 | 1973-10-02 | Rca Corp | Digital and analog data handling devices |
| US3757313A (en) * | 1972-06-29 | 1973-09-04 | Ibm | Data storage with predetermined settable configuration |
| US4272829A (en) * | 1977-12-29 | 1981-06-09 | Ncr Corporation | Reconfigurable register and logic circuitry device for selective connection to external buses |
| US4276609A (en) * | 1979-01-04 | 1981-06-30 | Ncr Corporation | CCD memory retrieval system |
| JPS6045499B2 (ja) * | 1980-04-15 | 1985-10-09 | 富士通株式会社 | 半導体記憶装置 |
| JPS5727477A (en) * | 1980-07-23 | 1982-02-13 | Nec Corp | Memory circuit |
| JPS57117168A (en) * | 1981-01-08 | 1982-07-21 | Nec Corp | Memory circuit |
| US4412313A (en) * | 1981-01-19 | 1983-10-25 | Bell Telephone Laboratories, Incorporated | Random access memory system having high-speed serial data paths |
| US4422161A (en) * | 1981-10-08 | 1983-12-20 | Rca Corporation | Memory array with redundant elements |
| JPS60236184A (ja) * | 1984-05-08 | 1985-11-22 | Nec Corp | 半導体メモリ |
-
1984
- 1984-10-23 JP JP59221165A patent/JPS61104391A/ja active Granted
-
1985
- 1985-10-17 US US06/788,398 patent/US4740922A/en not_active Expired - Fee Related
- 1985-10-22 EP EP85307600A patent/EP0188059B1/en not_active Expired - Lifetime
- 1985-10-22 DE DE8585307600T patent/DE3585733D1/de not_active Expired - Lifetime
- 1985-10-23 KR KR1019850007804A patent/KR900007226B1/ko not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0542078B2 (enExample) | 1993-06-25 |
| DE3585733D1 (de) | 1992-04-30 |
| EP0188059B1 (en) | 1992-03-25 |
| KR860003611A (ko) | 1986-05-28 |
| JPS61104391A (ja) | 1986-05-22 |
| EP0188059A1 (en) | 1986-07-23 |
| US4740922A (en) | 1988-04-26 |
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| KR900007226B1 (ko) | 반도체 메모리 장치 | |
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| DE3586523T2 (de) | Halbleiterspeicheranordnung mit einer seriellen dateneingangs- und ausgangsschaltung. | |
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| KR950014551B1 (ko) | 반도체기억장치 및 그 출력제어방법 | |
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| KR960700490A (ko) | 행방향 주소 스트로브 사이클을 갖지않고 프레임버퍼에 영향을 미치는 동작을 제공하기 위한 방법 및 장치(method and apparatus for providing operations affecting a frame buffer without a row adderss strobe cycle) | |
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| JPH081745B2 (ja) | シリアルアクセスメモリ | |
| JPH0778989B2 (ja) | 半導体メモリ装置 |
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| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
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St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
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| E902 | Notification of reason for refusal | ||
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| P13-X000 | Application amended |
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| FPAY | Annual fee payment |
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