KR900006318B1 - Gate array intergrated circuit device and method thereof for various bit-word construstions - Google Patents

Gate array intergrated circuit device and method thereof for various bit-word construstions

Info

Publication number
KR900006318B1
KR900006318B1 KR8509159A KR850009159A KR900006318B1 KR 900006318 B1 KR900006318 B1 KR 900006318B1 KR 8509159 A KR8509159 A KR 8509159A KR 850009159 A KR850009159 A KR 850009159A KR 900006318 B1 KR900006318 B1 KR 900006318B1
Authority
KR
South Korea
Prior art keywords
word
circuit device
gate array
construstions
various bit
Prior art date
Application number
KR8509159A
Other languages
English (en)
Inventor
Masato Igarashi
Yoshiyuki Suehiro
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of KR900006318B1 publication Critical patent/KR900006318B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/11809—Microarchitecture
    • H01L2027/11835—Degree of specialisation for implementing specific functions
    • H01L2027/11837—Implementation of digital circuits
    • H01L2027/11838—Implementation of memory functions
KR8509159A 1984-12-07 1985-12-06 Gate array intergrated circuit device and method thereof for various bit-word construstions KR900006318B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59258594A JPH0652784B2 (ja) 1984-12-07 1984-12-07 ゲートアレイ集積回路装置及びその製造方法

Publications (1)

Publication Number Publication Date
KR900006318B1 true KR900006318B1 (en) 1990-08-28

Family

ID=17322431

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8509159A KR900006318B1 (en) 1984-12-07 1985-12-06 Gate array intergrated circuit device and method thereof for various bit-word construstions

Country Status (5)

Country Link
US (1) US4791607A (ko)
EP (1) EP0184464B1 (ko)
JP (1) JPH0652784B2 (ko)
KR (1) KR900006318B1 (ko)
DE (1) DE3571103D1 (ko)

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US4706219A (en) * 1985-04-10 1987-11-10 Nec Corporation Word length selectable memory
US4905189B1 (en) * 1985-12-18 1993-06-01 System for reading and writing information
US5265045A (en) * 1986-10-31 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit device with built-in memory circuit group
US5243208A (en) * 1987-05-27 1993-09-07 Hitachi, Ltd. Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
JPS63293966A (ja) * 1987-05-27 1988-11-30 Hitachi Ltd 半導体集積回路装置
JPH0810724B2 (ja) * 1987-08-05 1996-01-31 富士通株式会社 ゲ−トアレイ及びメモリを有する半導体集積回路装置
JPH0812903B2 (ja) * 1987-10-19 1996-02-07 三菱電機株式会社 ゲートアレイ集積回路
JP2545416B2 (ja) * 1987-11-21 1996-10-16 株式会社日立製作所 半導体メモリ
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
JPH01158758A (ja) * 1987-12-16 1989-06-21 Toshiba Corp 半導体集積回路
JP2712079B2 (ja) * 1988-02-15 1998-02-10 株式会社東芝 半導体装置
JP2600304B2 (ja) * 1988-06-30 1997-04-16 三菱電機株式会社 半導体記憶装置とこれを用いたデータパス
KR900003884A (ko) * 1988-08-12 1990-03-27 미다 가쓰시게 대규모 반도체 집적회로 장치
JP2539012B2 (ja) * 1988-09-28 1996-10-02 富士通株式会社 メモリカ―ド
JP2891709B2 (ja) * 1989-01-16 1999-05-17 株式会社日立製作所 半導体集積回路装置
US5146428A (en) * 1989-02-07 1992-09-08 Hitachi, Ltd. Single chip gate array
US4954990A (en) * 1989-05-30 1990-09-04 Cypress Semiconductor Corp. Programming voltage control circuit for EPROMS
JPH0336614A (ja) * 1989-07-03 1991-02-18 Mitsumi Electric Co Ltd 回路モジュール
KR910006849A (ko) * 1989-09-29 1991-04-30 미다 가쓰시게 반도체 집적회로 장치
US5166900A (en) * 1989-10-27 1992-11-24 Nec Corporation Non-volatile semiconductor memory device with improved layout
US5422857A (en) * 1989-11-21 1995-06-06 Matsushita Electric Industrial Co., Ltd. Semiconductor memory unit having overlapping addresses
JPH0782481B2 (ja) * 1989-12-26 1995-09-06 三菱電機株式会社 半導体神経回路網
US5257360A (en) * 1990-03-23 1993-10-26 Advanced Micro Devices,Inc. Re-configurable block length cache
US5220518A (en) * 1990-06-07 1993-06-15 Vlsi Technology, Inc. Integrated circuit memory with non-binary array configuration
US5093805A (en) * 1990-06-20 1992-03-03 Cypress Semiconductor Corporation Non-binary memory array
JP3361825B2 (ja) * 1990-08-22 2003-01-07 テキサス インスツルメンツ インコーポレイテツド メモリ・アレイ・アーキテクチャ
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5325338A (en) * 1991-09-04 1994-06-28 Advanced Micro Devices, Inc. Dual port memory, such as used in color lookup tables for video systems
JPH0582746A (ja) * 1991-09-20 1993-04-02 Fujitsu Ltd 半導体記憶装置
EP0636256B1 (en) 1992-03-31 1997-06-04 Seiko Epson Corporation Superscalar risc processor instruction scheduling
US5371684A (en) * 1992-03-31 1994-12-06 Seiko Epson Corporation Semiconductor floor plan for a register renaming circuit
EP0638183B1 (en) 1992-05-01 1997-03-05 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
JP3531166B2 (ja) 1992-12-31 2004-05-24 セイコーエプソン株式会社 レジスタ・リネーミングのシステム及び方法
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US7420836B1 (en) * 2007-02-13 2008-09-02 International Business Machines Corporation Single-ended memory cell with improved read stability and memory using the cell
US7460400B1 (en) * 2007-08-22 2008-12-02 Nscore Inc. Nonvolatile memory utilizing MIS memory transistors with bit mask function
US7463519B1 (en) * 2007-08-22 2008-12-09 Nscore Inc. MIS-transistor-based nonvolatile memory device for authentication
JP6644308B1 (ja) * 2019-09-30 2020-02-12 アースアイズ株式会社 デジタル・サイネージの取付け構造

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
JPS5624946A (en) * 1979-08-08 1981-03-10 Fujitsu Ltd Master slice type integrated circuit
JPS57124463A (en) * 1981-01-26 1982-08-03 Nec Corp Semiconductor device
EP0079127A1 (en) * 1981-11-06 1983-05-18 Texas Instruments Incorporated Programmable system component
JPS58114392A (ja) * 1981-12-07 1983-07-07 Fujitsu Ltd 半導体記憶装置
EP0101884A3 (en) * 1982-07-21 1987-09-02 Hitachi, Ltd. Monolithic semiconductor memory
JPS5919367A (ja) * 1982-07-26 1984-01-31 Toshiba Corp メモリ付ゲ−トアレイ
US4527254A (en) * 1982-11-15 1985-07-02 International Business Machines Corporation Dynamic random access memory having separated VDD pads for improved burn-in
JPS609152A (ja) * 1983-06-29 1985-01-18 Fujitsu Ltd 半導体装置
US4688197A (en) * 1983-12-30 1987-08-18 Texas Instruments Incorporated Control of data access to memory for improved video system

Also Published As

Publication number Publication date
EP0184464B1 (en) 1989-06-14
EP0184464A1 (en) 1986-06-11
US4791607A (en) 1988-12-13
JPS61136257A (ja) 1986-06-24
DE3571103D1 (en) 1989-07-20
JPH0652784B2 (ja) 1994-07-06

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A201 Request for examination
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Year of fee payment: 6

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