KR890003035A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR890003035A
KR890003035A KR1019880009514A KR880009514A KR890003035A KR 890003035 A KR890003035 A KR 890003035A KR 1019880009514 A KR1019880009514 A KR 1019880009514A KR 880009514 A KR880009514 A KR 880009514A KR 890003035 A KR890003035 A KR 890003035A
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South Korea
Prior art keywords
forming
manufacturing
semiconductor device
layer
conductive
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KR1019880009514A
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English (en)
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KR920000077B1 (ko
Inventor
사토시 마에다
시즈오 사와다
사토시 시노자키
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Priority claimed from JP62188241A external-priority patent/JPH06105772B2/ja
Priority claimed from JP63036767A external-priority patent/JPH0682659B2/ja
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR890003035A publication Critical patent/KR890003035A/ko
Application granted granted Critical
Publication of KR920000077B1 publication Critical patent/KR920000077B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용없음

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 5도(a)내지 제 5도(h)는 본 발명의 제 1 실시예에 따른 반도체장치의 제조방법을 각 공정별로 도시해 놓은 단면도, 제 6 도는 본 발명의 제 2 실시예에 따른 반도체장치의 제조방법을 설명하기 위한 반도체장치를 도시해 놓은 단면도, 제 7 도는 본 발명의 제 3 실시예에 따른 제조방법을 설명하기 위한 반도체장치를 도시해 놓은 단면도

Claims (13)

  1. 도전성 부재를 갖춘 반도체장치의 제조방법에 있어서, 상기 도전성 부재상에 부재절연층을 형성하는 공정과, 이 부재 절연층의 소정부분을 에칭해서 접속구멍을 형성하는 공정, 상기 부재절연층과 접속구멍에 제 1 도전층을 형성하는 공정, 축소된 편차를 갖는 표면을 형성하기 위해 상기 부재절연층과 제 1 도전층상에 평탄츠을 형성하는 공정, 상기 평탄층을 에칭해서 상기 제 1 도전층의 일부분을 노출시키는 공정 및, 상기 평탄층과 상기 제 1 도전층의 노출된 부분에 제 2 도전층을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법
  2. 제 1 항에 있어서, 상기 부재절연층을 형성하는 공정에 상기 제 1 및 제 2 부재절연층을 형성하는 공정이 구비되어 있는 것을 특징으로 하는 반도체장치의 제조방법
  3. 제 2 항에 있어서, 상기 부재절연층을 형성하는 공정에 도전성 부재위에 자기정합법으로 제 1 부재절연층을 형성하는 공정이 구비되어 있는 것을 특징으로 하는 반도체장치의 제조방법
  4. 제 2 항에 있어서, 상기 부재절연층을 형성하는 공정에 상기 제 1 및 제 2 절연하층을 형성하는 종속(sub)공정이 구비되어 있는 것을 특징으로 하는 반도체장치의 제조방법
  5. 제 4 항에 있어서, 제 1 도전층을 형성하는 공정에 대기압보다 낮으 압력에서 도전성 물질을 기체상태로 증착하여 제 1 도전층을 형성하는 공정이 구비되어 있는 것을 특징으로 하는 반도체장치의 제조방법
  6. 제 5 항에 있어서, 상기 제 1 도전층이 다결정실리콘으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법
  7. 제 1 항에 있어서, 상기 제 2 도전층이 금속을 포함하는 물질로 이루어진 것을 특징으로 하는 반도체장치의 제조방법
  8. 제 7 항에 있어서, 상기 제 2 도전층이 알루미늄으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법
  9. 제 1 항에 있어서, 상기 평탄층이 보론과 인을 포함하는 그룹(GroupP)에서 선택된 물질로 구성된 실리케이트·유리로 이루어진 것을 특징으로 하느 ㄴ반도체장치의 제조방법
  10. 제 9 항에 있어서, 상기 실리케이트·유리가 필수적으로 BPSG, PSG 및 BSG로 구성된 그룹에서 선택된 물질로 이루어진 것을 특징으로 하는 반도체장치의 제조방법
  11. 제 1 항에 있어서, 상기 평탄층을 형성하는 공정에 스핀코트법으로 실리케이트·유리의 평탄층을 형성하는 공정이 구비되어 있는 것을 특징으로 하는 반도체장치의 제조방법
  12. 제 1 항에 있어서, 상기 평탄층을 형성하는 공정에 접속구멍사이에 평탄층을 형성하는 공정이 구비되어 있는 것을 특징으로 하는 반도체장치의 제조방법
  13. 제 1 항에 있어서, 상기 도전부재에 워드선이 구비되어 있는 것을 특징으로 하는 반도체장치의 제조방법
KR1019880009514A 1987-07-28 1988-07-27 반도체장치의 제조방법 KR920000077B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP62-188241 1987-07-28
JP62188241A JPH06105772B2 (ja) 1987-07-28 1987-07-28 半導体装置の製造方法
JP63-036767 1988-02-19
JP63036767A JPH0682659B2 (ja) 1988-02-19 1988-02-19 半導体集積回路の配線構造
JP63-36767 1988-02-19

Publications (2)

Publication Number Publication Date
KR890003035A true KR890003035A (ko) 1989-04-12
KR920000077B1 KR920000077B1 (ko) 1992-01-06

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Application Number Title Priority Date Filing Date
KR1019880009514A KR920000077B1 (ko) 1987-07-28 1988-07-27 반도체장치의 제조방법

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US (1) US5110766A (ko)
EP (1) EP0305055B1 (ko)
KR (1) KR920000077B1 (ko)
DE (1) DE3877282T2 (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5602056A (en) * 1990-03-05 1997-02-11 Vlsi Technology, Inc. Method for forming reliable MOS devices using silicon rich plasma oxide film
US5374833A (en) * 1990-03-05 1994-12-20 Vlsi Technology, Inc. Structure for suppression of field inversion caused by charge build-up in the dielectric
US5763937A (en) * 1990-03-05 1998-06-09 Vlsi Technology, Inc. Device reliability of MOS devices using silicon rich plasma oxide films
JPH04342164A (ja) * 1991-05-20 1992-11-27 Hitachi Ltd 半導体集積回路装置の形成方法
JP3216104B2 (ja) * 1991-05-29 2001-10-09 ソニー株式会社 メタルプラグ形成方法及び配線形成方法
JP2689038B2 (ja) * 1991-12-04 1997-12-10 三菱電機株式会社 半導体装置およびその製造方法
US5414221A (en) 1991-12-31 1995-05-09 Intel Corporation Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias
US5220483A (en) * 1992-01-16 1993-06-15 Crystal Semiconductor Tri-level capacitor structure in switched-capacitor filter
US5250464A (en) * 1992-03-11 1993-10-05 Texas Instruments Incorporated Method of making a low capacitance, low resistance sidewall antifuse structure
US5500557A (en) * 1992-04-30 1996-03-19 Sgs-Thomson Microelectronics, Inc. Structure and method for fabricating integrated circuits
US5576225A (en) * 1992-05-09 1996-11-19 Semiconductor Energy Laboratory Co., Ltd. Method of forming electric circuit using anodic oxidation
US5229326A (en) * 1992-06-23 1993-07-20 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
USRE40790E1 (en) 1992-06-23 2009-06-23 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
DE69333722T2 (de) * 1993-05-31 2005-12-08 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Verbesserung der Haftung zwischen Dielektrikschichten, an ihrer Grenzfläche, in der Herstellung von Halbleiterbauelementen
US5534451A (en) * 1995-04-27 1996-07-09 Taiwan Semiconductor Manufacturing Company Method for fabricating a reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57126147A (en) * 1981-01-28 1982-08-05 Fujitsu Ltd Manufacture of semiconductor device
US4453306A (en) * 1983-05-27 1984-06-12 At&T Bell Laboratories Fabrication of FETs
KR890004962B1 (ko) * 1985-02-08 1989-12-02 가부시끼가이샤 도오시바 반도체장치 및 그 제조방법
KR900003618B1 (ko) * 1986-05-30 1990-05-26 후지쓰가부시끼가이샤 반도체장치 및 그 제조방법
US4894351A (en) * 1988-02-16 1990-01-16 Sprague Electric Company Method for making a silicon IC with planar double layer metal conductors system
US4874493A (en) * 1988-03-28 1989-10-17 Microelectronics And Computer Technology Corporation Method of deposition of metal into cavities on a substrate

Also Published As

Publication number Publication date
EP0305055B1 (en) 1993-01-07
EP0305055A1 (en) 1989-03-01
US5110766A (en) 1992-05-05
DE3877282D1 (de) 1993-02-18
KR920000077B1 (ko) 1992-01-06
DE3877282T2 (de) 1993-07-29

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