KR890003017A - 멀티레벨 상호접속라인 전달 및 처리방법 - Google Patents

멀티레벨 상호접속라인 전달 및 처리방법 Download PDF

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Publication number
KR890003017A
KR890003017A KR1019880008170A KR880008170A KR890003017A KR 890003017 A KR890003017 A KR 890003017A KR 1019880008170 A KR1019880008170 A KR 1019880008170A KR 880008170 A KR880008170 A KR 880008170A KR 890003017 A KR890003017 A KR 890003017A
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South Korea
Prior art keywords
layer
forming
substrate
multilevel
multilevel interconnect
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KR1019880008170A
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English (en)
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KR970000650B1 (ko
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에드윈 우드 토마스
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빈센트 죠셉 로너
모토로라 인코포레이티드
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Publication of KR890003017A publication Critical patent/KR890003017A/ko
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Publication of KR970000650B1 publication Critical patent/KR970000650B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

내용 없음

Description

멀티레벨 상호접속라인 전달 및 처리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 상호접속라인의 처리 이전의 멀티칩 모듈의 확대 평면도.

Claims (3)

  1. 병합된 다수의 전기적 접촉부를 가지는 모듈에 사용하기 위한 멀티레벨 상호접속라인 전달 및 처리하는 방법에 있어서, 기판을 제공하는 단계와, 상기 기판상에 분리층을 형성하는 단계와, 상기 분리층상에 멀티레벨 상호접속라인을 형성하는 단계와, 적어도 부분적으로 상기 기판과 상기 멀티레벨 상호접속라인을 분리하는 단계와, 상기 멀티레벨 상호접속라인과 예정된 관계로 다수의 전기적 접촉부를 가진 모듈이 점착하는 단계와, 상기 멀티레벨 상호접속라인과 예정된 관계로 다수의 전기적 접촉부를 가진 모듈이 점착하는 단계와, 상기 멀티레벨 상호접속라인과 상기 모듈의 상기 다수의 전기적 접촉부와 전기적으로 접속하는 단계를 포함하는 것을 특징으로 하는 멀티레벨 상호접속라인 전달 및 처리방법.
  2. 제 1 항에 있어서, 상기 멀티레벨 상호접속라인이 부분적으로 기판으로부터 분리된후 멀티레벨 상호접속라인에 안정화수단을 점착시키는 단계와, 상기 기판으로부터 상기 멀티레벨 상호접속라인을 완전히 분리시키기 위해 다른 분리층을 에칭시키는 단계와, 상기 안정화수단을 제거시키는 단계를 포함하는 것을 특징으로 하는 멀티레벨 상호접속라인 전달 및 처리방법.
  3. 제 1 항에 있어서, 상기 기판의 상기 분리층에 제 1 폴리머층을 형성하는 단계와, 상기 제 1 폴리머층에 제 1 도체층을 형성하는 단계와, 상기 제 1 도체층에 제 1 레지스트층을 패턴하는 단계와, 상기 제 1 레지스트층을 에칭 마스크로 사용하여 에칭하는 단계와, 상기 제 1 레지스트층을 제거하는 단계와, 상기 제 1 도체층을 확장시키는 통로를 갖는 상기 제 1 폴리머층과 제 2 폴리머층을 형성하는 단계와, 상기 제 2 폴리머층에 어떤 제 2 도체층을 형성하는 단계와, 상기 제 2 폴리머층을 형성하는 단계와, 상기 제 2 폴리머층에 어떤 제 2 도체층을 형성하는 단계와, 상기 제 2 도체를 에칭시키는 단계와, 상기 제 2 레지스트층을 제거시키는 단계와, 마지막 폴리머층을 형성하는 단계를 포함하는 것을 특징으로 하는 멀티레벨 상호접속라인 전달 및 처리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880008170A 1987-07-24 1988-07-01 멀티레벨 상호 접속라인처리 및 전이 방법 KR970000650B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US077,476 1987-07-24
US07/077,476 US4743568A (en) 1987-07-24 1987-07-24 Multilevel interconnect transfer process

Publications (2)

Publication Number Publication Date
KR890003017A true KR890003017A (ko) 1989-04-12
KR970000650B1 KR970000650B1 (ko) 1997-01-16

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ID=22138273

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880008170A KR970000650B1 (ko) 1987-07-24 1988-07-01 멀티레벨 상호 접속라인처리 및 전이 방법

Country Status (5)

Country Link
US (1) US4743568A (ko)
EP (1) EP0300720B1 (ko)
JP (1) JP2632376B2 (ko)
KR (1) KR970000650B1 (ko)
DE (1) DE3855719T2 (ko)

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US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
AU5094890A (en) * 1989-01-25 1990-09-05 Polylithics, Inc. Extended integration semiconductor structure and method of making the same
US5108819A (en) * 1990-02-14 1992-04-28 Eli Lilly And Company Thin film electrical component
US5258236A (en) * 1991-05-03 1993-11-02 Ibm Corporation Multi-layer thin film structure and parallel processing method for fabricating same
US5187121A (en) * 1991-12-18 1993-02-16 International Business Machines Corporation Process for fabrication of a semiconductor structure and contact stud
EP1179842A3 (en) * 1992-01-31 2002-09-04 Canon Kabushiki Kaisha Semiconductor substrate and method for preparing same
US5854534A (en) * 1992-08-05 1998-12-29 Fujitsu Limited Controlled impedence interposer substrate
US5567981A (en) * 1993-03-31 1996-10-22 Intel Corporation Bonding pad structure having an interposed rigid layer
US5474458A (en) * 1993-07-13 1995-12-12 Fujitsu Limited Interconnect carriers having high-density vertical connectors and methods for making the same
US5382759A (en) * 1993-09-28 1995-01-17 Trw Inc. Massive parallel interconnection attachment using flexible circuit
US5480970A (en) * 1993-12-22 1996-01-02 Resolution Pharmaceuticals Metal chelators
US5534466A (en) * 1995-06-01 1996-07-09 International Business Machines Corporation Method of making area direct transfer multilayer thin film structure
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
US7012811B1 (en) 2000-05-10 2006-03-14 Micron Technology, Inc. Method of tuning a multi-path circuit
BR0115537A (pt) * 2000-11-21 2006-05-02 Tyco Electronics Corp pigmentos e composições para uso em marcação a laser

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Also Published As

Publication number Publication date
JP2632376B2 (ja) 1997-07-23
EP0300720A1 (en) 1989-01-25
DE3855719D1 (de) 1997-02-06
KR970000650B1 (ko) 1997-01-16
EP0300720B1 (en) 1996-12-27
US4743568A (en) 1988-05-10
DE3855719T2 (de) 1997-06-19
JPS6442157A (en) 1989-02-14

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