DE3855719D1 - Verfahren zum Übertragen von aus mehreren Ebenen zusammengesetzten Verbindungselementen - Google Patents

Verfahren zum Übertragen von aus mehreren Ebenen zusammengesetzten Verbindungselementen

Info

Publication number
DE3855719D1
DE3855719D1 DE3855719T DE3855719T DE3855719D1 DE 3855719 D1 DE3855719 D1 DE 3855719D1 DE 3855719 T DE3855719 T DE 3855719T DE 3855719 T DE3855719 T DE 3855719T DE 3855719 D1 DE3855719 D1 DE 3855719D1
Authority
DE
Germany
Prior art keywords
connecting elements
several levels
elements composed
transferring connecting
transferring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855719T
Other languages
English (en)
Other versions
DE3855719T2 (de
Inventor
Thomas Edwin Wood
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE3855719D1 publication Critical patent/DE3855719D1/de
Application granted granted Critical
Publication of DE3855719T2 publication Critical patent/DE3855719T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
DE3855719T 1987-07-24 1988-07-18 Verfahren zum Übertragen von aus mehreren Ebenen zusammengesetzten Verbindungselementen Expired - Fee Related DE3855719T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/077,476 US4743568A (en) 1987-07-24 1987-07-24 Multilevel interconnect transfer process

Publications (2)

Publication Number Publication Date
DE3855719D1 true DE3855719D1 (de) 1997-02-06
DE3855719T2 DE3855719T2 (de) 1997-06-19

Family

ID=22138273

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855719T Expired - Fee Related DE3855719T2 (de) 1987-07-24 1988-07-18 Verfahren zum Übertragen von aus mehreren Ebenen zusammengesetzten Verbindungselementen

Country Status (5)

Country Link
US (1) US4743568A (de)
EP (1) EP0300720B1 (de)
JP (1) JP2632376B2 (de)
KR (1) KR970000650B1 (de)
DE (1) DE3855719T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
AU5094890A (en) * 1989-01-25 1990-09-05 Polylithics, Inc. Extended integration semiconductor structure and method of making the same
US5108819A (en) * 1990-02-14 1992-04-28 Eli Lilly And Company Thin film electrical component
US5258236A (en) * 1991-05-03 1993-11-02 Ibm Corporation Multi-layer thin film structure and parallel processing method for fabricating same
US5187121A (en) * 1991-12-18 1993-02-16 International Business Machines Corporation Process for fabrication of a semiconductor structure and contact stud
DE69331816T2 (de) * 1992-01-31 2002-08-29 Canon Kk Verfahren zur Herstellung eines Halbleitersubstrats
US5854534A (en) * 1992-08-05 1998-12-29 Fujitsu Limited Controlled impedence interposer substrate
US5567981A (en) * 1993-03-31 1996-10-22 Intel Corporation Bonding pad structure having an interposed rigid layer
US5474458A (en) * 1993-07-13 1995-12-12 Fujitsu Limited Interconnect carriers having high-density vertical connectors and methods for making the same
US5382759A (en) * 1993-09-28 1995-01-17 Trw Inc. Massive parallel interconnection attachment using flexible circuit
US5480970A (en) * 1993-12-22 1996-01-02 Resolution Pharmaceuticals Metal chelators
US5534466A (en) * 1995-06-01 1996-07-09 International Business Machines Corporation Method of making area direct transfer multilayer thin film structure
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
US7012811B1 (en) 2000-05-10 2006-03-14 Micron Technology, Inc. Method of tuning a multi-path circuit
EP1339782B1 (de) * 2000-11-21 2011-05-04 TYCO Electronics Corporation Pigmente und zusammensetzungen zur verwendung bei der lasermarkierung

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179324A (en) * 1977-11-28 1979-12-18 Spire Corporation Process for fabricating thin film and glass sheet laminate
US4251852A (en) * 1979-06-18 1981-02-17 International Business Machines Corporation Integrated circuit package
US4377316A (en) * 1981-02-27 1983-03-22 International Business Machines Corporation High density interconnection means for chip carriers
US4420203A (en) * 1981-06-04 1983-12-13 International Business Machines Corporation Semiconductor module circuit interconnection system
US4446477A (en) * 1981-08-21 1984-05-01 Sperry Corporation Multichip thin film module
US4480288A (en) * 1982-12-27 1984-10-30 International Business Machines Corporation Multi-layer flexible film module
US4630096A (en) * 1984-05-30 1986-12-16 Motorola, Inc. High density IC module assembly
US4698662A (en) * 1985-02-05 1987-10-06 Gould Inc. Multichip thin film module

Also Published As

Publication number Publication date
KR890003017A (ko) 1989-04-12
JP2632376B2 (ja) 1997-07-23
EP0300720A1 (de) 1989-01-25
KR970000650B1 (ko) 1997-01-16
JPS6442157A (en) 1989-02-14
DE3855719T2 (de) 1997-06-19
US4743568A (en) 1988-05-10
EP0300720B1 (de) 1996-12-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee