KR870003556A - 붕소 주입 제어 방법 - Google Patents

붕소 주입 제어 방법 Download PDF

Info

Publication number
KR870003556A
KR870003556A KR1019860007768A KR860007768A KR870003556A KR 870003556 A KR870003556 A KR 870003556A KR 1019860007768 A KR1019860007768 A KR 1019860007768A KR 860007768 A KR860007768 A KR 860007768A KR 870003556 A KR870003556 A KR 870003556A
Authority
KR
South Korea
Prior art keywords
ions
boron
implantation
doped
phosphorus
Prior art date
Application number
KR1019860007768A
Other languages
English (en)
Other versions
KR950008848B1 (ko
Inventor
위니프레드 플래틀리 도리스
뎅 후 셍
Original Assignee
글렌 에이치. 브루스틀
알. 씨. 에이 코오포레이숀
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 글렌 에이치. 브루스틀, 알. 씨. 에이 코오포레이숀 filed Critical 글렌 에이치. 브루스틀
Publication of KR870003556A publication Critical patent/KR870003556A/ko
Application granted granted Critical
Publication of KR950008848B1 publication Critical patent/KR950008848B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/919—Compensation doping

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

붕소 주입 제어 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 적절한 불순물이 소량 주입되어 n형 웰이 형성된 p형 실리콘 웨이퍼의 단면도.
제2도는 제1도의 웨이퍼에 종래의 방법으로 고순도 게이트 산화물의 얇은 층이 성장된 것을 도시한 단면도.
제3도는 제2도의 구조체 위에 소량의 인이 주입되고 사진 석판 인쇄술에 의해 절연된 게이트 구조체들의 형성된 실리콘 층이 형성된 것을 도시한 단면도.
*도면의 주요 부분에 대한 설명
10:p형 실리콘 웨이퍼 12:n형 웰 14:두꺼운 필드 산화물 부착물
16:게이트 산화물 18:실리콘 층 20,22:게이트 구조체
26,28:소오스 및 드레인영역 32:리플로우 글래스 층 34:개구
36:제2도전층 38:상부 밀봉층

Claims (8)

  1. 실리콘 디옥사이드 층을 덮는 실리콘 구조체에 이 구조체를 P도전형으로 만들기에 충분한 붕소 이온들로 이온 주입하는 방법에 있어서, 상기 구조체를 붕소 주입전에 인 이온으로 도우핑하여 붕소 주입된 것을 서냉시키는 동안 붕소 이온들이 산화물 층으로 이동하는 것을 거의 방지하는 것을 특징으로 하는 상기 방법.
  2. 제1항에 있어서, 실리콘 구조체는 실리콘 디옥사이드 층 위에 부착될 때 그 자체가 인 이온들로 도우핑 되는 것을 특징으로 하는 상기 방법.
  3. 제1항에 있어서, 실리콘 구조체는 확산에 의해 인 이온들로 도우핑되는 것을 특징으로 하는 상기방법.
  4. 제1항에 있어서, 실리콘 구조체는 이온 주입에 의해 인 이온들로 도우핑되는 것을 특징으로 하는 상기방법.
  5. 제4항에 있어서, 인 이온의 주입량이 입방 센티미터당 약 1012-1015이온으로 되는 것을 특징으로 하는 상기 방법.
  6. 제5항에 있어서, 인 이온의 주입량 입방 센티미터당 약 1013-1014이온으로 되는 것을 특징으로 하는 상기 방법.
  7. 제1항에 있어서, 붕소 이온의 주입량이 평방 센티미터당 최소한 약 1015이온으로 되는 것을 특징으로 하는 상기 방법.
  8. 제7항에 있어서, 붕소 이온의 주입량이 평방센티미터당 약 1015-1016이온으로 되는 것을 특징으로 하는 상기 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860007768A 1985-09-23 1986-09-16 붕소 주입 제어 방법 KR950008848B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US778,986 1985-09-23
US06/778,986 US4637836A (en) 1985-09-23 1985-09-23 Profile control of boron implant

Publications (2)

Publication Number Publication Date
KR870003556A true KR870003556A (ko) 1987-04-18
KR950008848B1 KR950008848B1 (ko) 1995-08-08

Family

ID=25114954

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860007768A KR950008848B1 (ko) 1985-09-23 1986-09-16 붕소 주입 제어 방법

Country Status (3)

Country Link
US (1) US4637836A (ko)
JP (1) JPH0727877B2 (ko)
KR (1) KR950008848B1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251248A (ja) * 1985-08-30 1987-03-05 Toshiba Corp 半導体装置の製造方法
US4889819A (en) * 1988-05-20 1989-12-26 International Business Machines Corporation Method for fabricating shallow junctions by preamorphizing with dopant of same conductivity as substrate
US5136344A (en) * 1988-11-02 1992-08-04 Universal Energy Systems, Inc. High energy ion implanted silicon on insulator structure
FR2651068B1 (fr) * 1989-08-16 1994-06-10 France Etat Procede de fabrication de transistor mos mesa de type silicium sur isolant
US5064775A (en) * 1990-09-04 1991-11-12 Industrial Technology Research Institute Method of fabricating an improved polycrystalline silicon thin film transistor
IT1256362B (it) * 1992-08-19 1995-12-04 St Microelectronics Srl Processo di realizzazione su semiconduttori di regioni impiantate a basso rischio di channeling
DE69424717T2 (de) * 1993-03-17 2001-05-31 Canon K.K., Tokio/Tokyo Verbindungsverfahren einer Verdrahtung mit einem Halbleitergebiet und durch dieses Verfahren hergestellte Halbleitervorrichtung
DE69433949T2 (de) * 1993-12-07 2005-09-08 Infineon Technologies Ag Verfahren zur Herstellung von MOSFETS mit verbesserten Kurz-Kanal Effekten
US5824576A (en) * 1996-02-23 1998-10-20 Micron Technology, Inc. Method of forming complementary type conductive regions on a substrate
US5780330A (en) * 1996-06-28 1998-07-14 Integrated Device Technology, Inc. Selective diffusion process for forming both n-type and p-type gates with a single masking step
US5882962A (en) * 1996-07-29 1999-03-16 Vanguard International Semiconductor Corporation Method of fabricating MOS transistor having a P+ -polysilicon gate
US6087214A (en) * 1998-04-29 2000-07-11 Vlsi Technology, Inc. Arrangement and method for DRAM cell using shallow trench isolation
AU2004226925A1 (en) * 2003-11-03 2005-05-19 Black & Decker, Inc. Tripod assembly

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USB421061I5 (ko) * 1964-12-24
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
US4507847A (en) * 1982-06-22 1985-04-02 Ncr Corporation Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor
US4502894A (en) * 1983-08-12 1985-03-05 Fairchild Camera & Instrument Corporation Method of fabricating polycrystalline silicon resistors in integrated circuit structures using outdiffusion
JPS6057952A (ja) * 1983-09-09 1985-04-03 Toshiba Corp 半導体装置の製造方法
US4560419A (en) * 1984-05-30 1985-12-24 Inmos Corporation Method of making polysilicon resistors with a low thermal activation energy

Also Published As

Publication number Publication date
US4637836A (en) 1987-01-20
JPH0727877B2 (ja) 1995-03-29
JPS6269666A (ja) 1987-03-30
KR950008848B1 (ko) 1995-08-08

Similar Documents

Publication Publication Date Title
US4729001A (en) Short-channel field effect transistor
JPS6453577A (en) Nonvolatile semiconductor device and manufacture thereof
US5134447A (en) Neutral impurities to increase lifetime of operation of semiconductor devices
JPS6446981A (en) Semiconductor device
KR930009101A (ko) 향상된 성능의 가로 방향 이중 확산 mos 트랜지스터 및 그 제조 방법
GB1465244A (en) Deep depletion insulated gate field effect transistors
KR870003556A (ko) 붕소 주입 제어 방법
US5770503A (en) Method of forming low threshold voltage vertical power transistor using epitaxial technology
GB1451096A (en) Semiconductor devices
JPH0783119B2 (ja) 電界効果トランジスタ
JPS5766674A (en) Semiconductor device
US4185291A (en) Junction-type field effect transistor and method of making the same
US3656031A (en) Low noise field effect transistor with channel having subsurface portion of high conductivity
US4713329A (en) Well mask for CMOS process
EP0077737A3 (en) Low capacitance field effect transistor
JPS645070A (en) Vertical insulated gate field effect transistor
KR870006679A (ko) 전기효과 트랜지스터
KR900019249A (ko) 알루미늄/붕소 p-웰
GB1325082A (en) Semiconductor devices
KR870002666A (ko) 반도체장치의 제조방법
JPS54139488A (en) Mos semiconductor element and its manufacture
KR900017177A (ko) 반도체 장치 및 그 제조방법
JPS57102073A (en) Semiconductor memory and manufacture thereof
JPS57192083A (en) Semiconductor device
JPS5721865A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010731

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee