KR850700184A - Ⅲ-ⅴ족 화합물 반도체 장치의 제조방법 - Google Patents

Ⅲ-ⅴ족 화합물 반도체 장치의 제조방법

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Publication number
KR850700184A
KR850700184A KR1019850700132A KR850700132A KR850700184A KR 850700184 A KR850700184 A KR 850700184A KR 1019850700132 A KR1019850700132 A KR 1019850700132A KR 850700132 A KR850700132 A KR 850700132A KR 850700184 A KR850700184 A KR 850700184A
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KR
South Korea
Prior art keywords
layer
temperature
manufacturing
semiconductor device
resistivity
Prior art date
Application number
KR1019850700132A
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English (en)
Inventor
존 안소니 필립
Original Assignee
마이클 와이. 엡스타인
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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Application filed by 마이클 와이. 엡스타인, 아메리칸 텔리폰 앤드 텔레그라프 캄파니 filed Critical 마이클 와이. 엡스타인
Publication of KR850700184A publication Critical patent/KR850700184A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology

Abstract

내용 없음

Description

Ⅲ-Ⅴ족 화합물 반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 한 실시예에 따라서 매입된 상호 연결로 N층을 사용한 집적회로의 개략도이다.

Claims (7)

  1. 제1도펀트를 가진 제1층(14)과 제2도펀트를 가진 제2층(16)을 포함하는 다층으로 된 Ⅲ-Ⅴ족 화합물 구조(제4도)의 제공을 구비하는 반도체 장치의 제조방법에 있어서, 일정한 양과 에너지로 상기 층을 이온충돌시켜서 상기 층이 저항성이 높아지게 되고, 상기 제1층의 비저항은 제1온도로 가열될때 비교적 높게 유지되지만 그 다음에는 비저항이 비교적 낮게 감소되고, 상기 제2층의 비저항은 상기 제1온도와 다른 제2온도로 가열될때 높게 유지되며 그 다음에는 비저항이 비교적 낮게 감소하며; 상기 층을 상기 제1온도와 상기 제2온도 사이의 온도로 가열하면 상기 제1층은 비저항이 낮아지고, 반면에 상기 제2층은 비저항이 높게 유지되는 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물 반도체 장치의 제조방법.
  2. 상기 구조의 표면에서 마스크를 형성하는 것을 포함하는 제1항의 방법에 있어서, 상기 이온층들은 상기 마스크를 통해 발생되는 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물 반도체 장치의 제조방법.
  3. 제1항의 방법에 있어서, 이온층들은 양자, 중양자 및 헬륨이온으로 구성된 그룹중에서 선택된 이온으로 상기 층에 충돌시키는 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물 반도체 장치의 제조방법.
  4. 제1항의 방법에 있어서, 상기 제1펀트는 도너이며 상기 제2도펀트는 억셉터인 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물 반도체 장치의 제조방법.
  5. 제1항의 방법에 있어서, 상기 제1 및 제2도펀트는 억셉터인 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물 반도체 장치의 제조방법.
  6. 제1항의 방법에 있어서, 상기 제1 및 제2도펀트는 억셉터인 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물 반도체 장치의 제조방법.
  7. 상기 제2층이 상기 제1층 위에 형성되어 있고, 상기 도펀트는 상기 제2온도를 상기 제1온도보다 높게 하였을때 상기 층이 초기에 도전성이 높은 상태로 하는데 효과적인 구조를 제공하는 것을 포함하는 제1항의 방법에 있어서, 상기 구조에 제1에너지로 이온층들을 시키면, 이온은 상기 두층 관통하고, 상기 구조에 낮은 에너지로 이온을 충돌시키면, 이온은 상기 제2층만 관통하는 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850700132A 1983-11-28 1984-10-18 Ⅲ-ⅴ족 화합물 반도체 장치의 제조방법 KR850700184A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US06/555,506 US4539743A (en) 1983-11-28 1983-11-28 Production of semiconductor structures with buried resistive or conductive regions by controlled ion bombardment and heat treatment
US555506 1983-11-28
PCT/US1984/001675 WO1985002495A1 (en) 1983-11-28 1984-10-18 Fabrication of group iii-v compound semiconductor devices having high and low resistivity regions

Publications (1)

Publication Number Publication Date
KR850700184A true KR850700184A (ko) 1985-10-25

Family

ID=24217514

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850700132A KR850700184A (ko) 1983-11-28 1984-10-18 Ⅲ-ⅴ족 화합물 반도체 장치의 제조방법

Country Status (7)

Country Link
US (1) US4539743A (ko)
EP (1) EP0162061B1 (ko)
JP (1) JPS61500521A (ko)
KR (1) KR850700184A (ko)
CA (1) CA1217877A (ko)
DE (1) DE3475992D1 (ko)
WO (1) WO1985002495A1 (ko)

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US4610731A (en) * 1985-04-03 1986-09-09 At&T Bell Laboratories Shallow impurity neutralization
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JPH01308063A (ja) * 1988-06-07 1989-12-12 Oki Electric Ind Co Ltd 半導体抵抗素子及びその形成方法
US5037766A (en) * 1988-12-06 1991-08-06 Industrial Technology Research Institute Method of fabricating a thin film polysilicon thin film transistor or resistor
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Also Published As

Publication number Publication date
DE3475992D1 (en) 1989-02-09
EP0162061A1 (en) 1985-11-27
WO1985002495A1 (en) 1985-06-06
JPS61500521A (ja) 1986-03-20
US4539743A (en) 1985-09-10
CA1217877A (en) 1987-02-10
EP0162061B1 (en) 1989-01-04

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