KR850004172A - 분리 반도체 디바이스 구조 제조방법 및 그 구조 - Google Patents

분리 반도체 디바이스 구조 제조방법 및 그 구조

Info

Publication number
KR850004172A
KR850004172A KR1019840007212A KR840007212A KR850004172A KR 850004172 A KR850004172 A KR 850004172A KR 1019840007212 A KR1019840007212 A KR 1019840007212A KR 840007212 A KR840007212 A KR 840007212A KR 850004172 A KR850004172 A KR 850004172A
Authority
KR
South Korea
Prior art keywords
semiconductor device
manufacturing
separation semiconductor
device structure
separation
Prior art date
Application number
KR1019840007212A
Other languages
English (en)
Other versions
KR910009782B1 (ko
Inventor
더블유. 볼랜드 버나드
Original Assignee
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 모토로라 인코포레이티드 filed Critical 모토로라 인코포레이티드
Publication of KR850004172A publication Critical patent/KR850004172A/ko
Application granted granted Critical
Publication of KR910009782B1 publication Critical patent/KR910009782B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/026Deposition thru hole in mask
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/05Etch and refill
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
KR1019840007212A 1983-11-18 1984-11-17 분리 반도체 디바이스 구조 제조방법 및 그 구조 KR910009782B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/553,326 US4609413A (en) 1983-11-18 1983-11-18 Method for manufacturing and epitaxially isolated semiconductor utilizing etch and refill technique
US553,326 1983-11-18

Publications (2)

Publication Number Publication Date
KR850004172A true KR850004172A (ko) 1985-07-01
KR910009782B1 KR910009782B1 (ko) 1991-11-30

Family

ID=24208993

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840007212A KR910009782B1 (ko) 1983-11-18 1984-11-17 분리 반도체 디바이스 구조 제조방법 및 그 구조

Country Status (6)

Country Link
US (1) US4609413A (ko)
EP (1) EP0154682B1 (ko)
JP (1) JPS60123039A (ko)
KR (1) KR910009782B1 (ko)
DE (1) DE3484708D1 (ko)
HK (1) HK69194A (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1218471B (it) * 1985-05-09 1990-04-19 Ates Componenti Elettron Circuito integrato bipolare comprendente transistori pnp verticali con collettore sul substrato
US4685196A (en) * 1985-07-29 1987-08-11 Industrial Technology Research Institute Method for making planar FET having gate, source and drain in the same plane
IT1188465B (it) * 1986-03-27 1988-01-14 Sgs Microelettronica Spa Rpocedimento per la fabbricazione di circuiti integrati a semiconduttore includenti dispositiv cmos e dispositivi elettronici ad alta tensione
JPH0812918B2 (ja) * 1986-03-28 1996-02-07 株式会社東芝 半導体装置の製造方法
USRE34025E (en) * 1987-02-13 1992-08-11 Kabushiki Kaisha Toshiba Semiconductor device with isolation between MOSFET and control circuit
JPS63198367A (ja) * 1987-02-13 1988-08-17 Toshiba Corp 半導体装置
FR2631488B1 (fr) * 1988-05-10 1990-07-27 Thomson Hybrides Microondes Circuit integre hyperfrequence de type planar, comportant au moins un composant mesa, et son procede de fabrication
JPH03263351A (ja) 1990-02-27 1991-11-22 Oki Electric Ind Co Ltd 半導体基板の製造方法
US5296392A (en) * 1990-03-06 1994-03-22 Digital Equipment Corporation Method of forming trench isolated regions with sidewall doping
GB2244373B (en) * 1990-05-19 1994-07-20 Stc Plc Semiconductor device manufacture
JP3449535B2 (ja) * 1999-04-22 2003-09-22 ソニー株式会社 半導体素子の製造方法
CN102456551A (zh) * 2010-10-21 2012-05-16 上海华虹Nec电子有限公司 外延生长方法
DE102020213385A1 (de) * 2020-10-23 2022-04-28 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen einer Buried-Layer-Schichtstruktur und entsprechende Buried-Layer-Schichtstruktur

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3587166A (en) * 1965-02-26 1971-06-28 Texas Instruments Inc Insulated isolation techniques in integrated circuits
US3793712A (en) * 1965-02-26 1974-02-26 Texas Instruments Inc Method of forming circuit components within a substrate
NL6606083A (ko) * 1965-06-22 1967-11-06 Philips Nv
US3370995A (en) * 1965-08-02 1968-02-27 Texas Instruments Inc Method for fabricating electrically isolated semiconductor devices in integrated circuits
GB1144850A (en) * 1966-10-13 1969-03-12 Westinghouse Electric Corp Complementary mos-type transistors and method of making
US3509433A (en) * 1967-05-01 1970-04-28 Fairchild Camera Instr Co Contacts for buried layer in a dielectrically isolated semiconductor pocket
US3753803A (en) * 1968-12-06 1973-08-21 Hitachi Ltd Method of dividing semiconductor layer into a plurality of isolated regions
US3566220A (en) * 1969-04-25 1971-02-23 Texas Instruments Inc Integrated semiconductor circuit having complementary transistors provided with dielectric isolation and surface collector contacts
US3853644A (en) * 1969-09-18 1974-12-10 Kogyo Gijutsuin Transistor for super-high frequency and method of manufacturing it
US3764409A (en) * 1969-09-29 1973-10-09 Hitachi Ltd Method for fabricating a semiconductor component for a semiconductor circuit
US3624463A (en) * 1969-10-17 1971-11-30 Motorola Inc Method of and apparatus for indicating semiconductor island thickness and for increasing isolation and decreasing capacity between islands
US3740276A (en) * 1970-08-24 1973-06-19 Texas Instruments Inc Multi-component semiconductor network and method for making same
US3982269A (en) * 1974-11-22 1976-09-21 General Electric Company Semiconductor devices and method, including TGZM, of making same
JPS5269587A (en) * 1975-12-08 1977-06-09 Hitachi Ltd Device and manufacture for high voltage resisting semiconductor
JPS5314579A (en) * 1976-07-26 1978-02-09 Hitachi Ltd Semiconductor integrated circuit and its production
JPS60776B2 (ja) * 1976-07-30 1985-01-10 株式会社日立製作所 半導体装置
GB2060252B (en) * 1979-09-17 1984-02-22 Nippon Telegraph & Telephone Mutually isolated complementary semiconductor elements
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
US4393574A (en) * 1980-12-05 1983-07-19 Kabushiki Kaisha Daini Seikosha Method for fabricating integrated circuits

Also Published As

Publication number Publication date
US4609413A (en) 1986-09-02
EP0154682A1 (en) 1985-09-18
KR910009782B1 (ko) 1991-11-30
JPS60123039A (ja) 1985-07-01
DE3484708D1 (de) 1991-07-18
HK69194A (en) 1994-07-22
EP0154682B1 (en) 1991-06-12

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