KR840002362B1 - 디스플레이장치 - Google Patents

디스플레이장치 Download PDF

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Publication number
KR840002362B1
KR840002362B1 KR1019810000118A KR810000118A KR840002362B1 KR 840002362 B1 KR840002362 B1 KR 840002362B1 KR 1019810000118 A KR1019810000118 A KR 1019810000118A KR 810000118 A KR810000118 A KR 810000118A KR 840002362 B1 KR840002362 B1 KR 840002362B1
Authority
KR
South Korea
Prior art keywords
substrate
input
led
pixel
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019810000118A
Other languages
English (en)
Korean (ko)
Other versions
KR830005618A (ko
Inventor
오사무 이찌가와
테쓰오 사다마사
Original Assignee
가부시기가이샤 도시바
사바쇼오이찌
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시기가이샤 도시바, 사바쇼오이찌 filed Critical 가부시기가이샤 도시바
Publication of KR830005618A publication Critical patent/KR830005618A/ko
Application granted granted Critical
Publication of KR840002362B1 publication Critical patent/KR840002362B1/ko
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Led Device Packages (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
KR1019810000118A 1980-06-13 1981-01-17 디스플레이장치 Expired KR840002362B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP?78938? 1980-06-13
JP78938 1980-06-13
JP7893880A JPS575083A (en) 1980-06-13 1980-06-13 Display unit

Publications (2)

Publication Number Publication Date
KR830005618A KR830005618A (ko) 1983-08-20
KR840002362B1 true KR840002362B1 (ko) 1984-12-21

Family

ID=13675815

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019810000118A Expired KR840002362B1 (ko) 1980-06-13 1981-01-17 디스플레이장치

Country Status (5)

Country Link
US (1) US4445132A (enExample)
EP (1) EP0042122B1 (enExample)
JP (1) JPS575083A (enExample)
KR (1) KR840002362B1 (enExample)
DE (1) DE3174041D1 (enExample)

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CN110121771A (zh) 2017-09-04 2019-08-13 首尔半导体株式会社 显示装置及该显示装置的制造方法
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Also Published As

Publication number Publication date
JPS612949B2 (enExample) 1986-01-29
EP0042122A3 (en) 1982-05-05
KR830005618A (ko) 1983-08-20
US4445132A (en) 1984-04-24
EP0042122B1 (en) 1986-03-12
JPS575083A (en) 1982-01-11
EP0042122A2 (en) 1981-12-23
DE3174041D1 (en) 1986-04-17

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PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

P11-X000 Amendment of application requested

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