KR20260002717A - 반도체 칩의 세정 방법 및 반도체 장치의 제조 방법 - Google Patents

반도체 칩의 세정 방법 및 반도체 장치의 제조 방법

Info

Publication number
KR20260002717A
KR20260002717A KR1020257034723A KR20257034723A KR20260002717A KR 20260002717 A KR20260002717 A KR 20260002717A KR 1020257034723 A KR1020257034723 A KR 1020257034723A KR 20257034723 A KR20257034723 A KR 20257034723A KR 20260002717 A KR20260002717 A KR 20260002717A
Authority
KR
South Korea
Prior art keywords
semiconductor
circuit layer
cleaning
semiconductor chip
adhesive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020257034723A
Other languages
English (en)
Korean (ko)
Inventor
히로요시 데구치
다츠야 마키노
세이지 가이
도시아키 시라사카
도모히토 모로사키
치카시 아오야기
가즈히로 사사키
다케히로 기노시타
고지 나오다
Original Assignee
가부시끼가이샤 레조낙
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 레조낙 filed Critical 가부시끼가이샤 레조낙
Publication of KR20260002717A publication Critical patent/KR20260002717A/ko
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/30—Cleaning after the substrates have been singulated
    • H01L21/02076—
    • H01L21/52—
    • H01L21/6836—
    • H01L21/78—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H01L2221/68327—

Landscapes

  • Cleaning Or Drying Semiconductors (AREA)
  • Dicing (AREA)
KR1020257034723A 2023-05-01 2024-04-25 반도체 칩의 세정 방법 및 반도체 장치의 제조 방법 Pending KR20260002717A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2023075732 2023-05-01
JPJP-P-2023-075732 2023-05-01
PCT/JP2024/016316 WO2024228364A1 (ja) 2023-05-01 2024-04-25 半導体チップの洗浄方法及び半導体装置の製造方法

Publications (1)

Publication Number Publication Date
KR20260002717A true KR20260002717A (ko) 2026-01-06

Family

ID=93333002

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020257034723A Pending KR20260002717A (ko) 2023-05-01 2024-04-25 반도체 칩의 세정 방법 및 반도체 장치의 제조 방법

Country Status (5)

Country Link
JP (3) JP7794362B2 (https=)
KR (1) KR20260002717A (https=)
CN (1) CN121002620A (https=)
TW (1) TW202445727A (https=)
WO (1) WO2024228364A1 (https=)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001197431A (ja) 2000-11-02 2001-07-19 Sony Corp 情報処理装置および情報処理方法、並びにプログラム格納媒体

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010093273A (ja) 2009-11-13 2010-04-22 Casio Computer Co Ltd 半導体装置の製造方法
JP5830250B2 (ja) 2011-02-15 2015-12-09 日東電工株式会社 半導体装置の製造方法
JP6390034B2 (ja) 2014-08-01 2018-09-19 リンテック株式会社 粘着シート
JP2016039186A (ja) 2014-08-05 2016-03-22 株式会社ディスコ ウエーハの加工方法
JP6899252B2 (ja) 2017-05-10 2021-07-07 株式会社ディスコ 加工方法
JP6961387B2 (ja) * 2017-05-19 2021-11-05 日東電工株式会社 ダイシングダイボンドフィルム
JP6519759B2 (ja) 2017-05-26 2019-05-29 パナソニックＩｐマネジメント株式会社 素子チップの製造方法
JP2020188154A (ja) 2019-05-15 2020-11-19 パナソニックＩｐマネジメント株式会社 樹脂組成物、樹脂被覆基板および素子チップの製造方法
CN111739854B (zh) 2020-07-06 2022-03-29 绍兴同芯成集成电路有限公司 一种开窗孔双面电镀厚铜膜
JP2022096079A (ja) 2020-12-17 2022-06-29 パナソニックＩｐマネジメント株式会社 素子チップの製造方法
KR20240005909A (ko) 2021-05-28 2024-01-12 미쓰이 가가쿠 토세로 가부시키가이샤 백그라인드용 점착성 필름 및 전자 장치의 제조 방법
JP7488231B2 (ja) 2021-09-16 2024-05-21 古河電気工業株式会社 半導体加工用テープ、及び半導体チップの製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001197431A (ja) 2000-11-02 2001-07-19 Sony Corp 情報処理装置および情報処理方法、並びにプログラム格納媒体

Also Published As

Publication number Publication date
JP2026066333A (ja) 2026-04-16
JP7819808B2 (ja) 2026-02-25
JP2026009401A (ja) 2026-01-19
WO2024228364A1 (ja) 2024-11-07
CN121002620A (zh) 2025-11-21
JPWO2024228364A1 (https=) 2024-11-07
JP7794362B2 (ja) 2026-01-06
TW202445727A (zh) 2024-11-16

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Legal Events

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PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

Q12 Application published

Free format text: ST27 STATUS EVENT CODE: A-1-1-Q10-Q12-NAP-PG1501 (AS PROVIDED BY THE NATIONAL OFFICE)

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000