KR20210068588A - 기판들을 본딩하기 위한 방법들 - Google Patents

기판들을 본딩하기 위한 방법들 Download PDF

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KR20210068588A
KR20210068588A KR1020217016196A KR20217016196A KR20210068588A KR 20210068588 A KR20210068588 A KR 20210068588A KR 1020217016196 A KR1020217016196 A KR 1020217016196A KR 20217016196 A KR20217016196 A KR 20217016196A KR 20210068588 A KR20210068588 A KR 20210068588A
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South Korea
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substrate
bonding
substrates
bonding interface
interface
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KR1020217016196A
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English (en)
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프라유디 리안토
구안 후에이 시
스리칸타라자 티루나부카라수
아르빈드 순다르라잔
슌동 다이
šœ동 다이
피터 카이 뭄 펑
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어플라이드 머티어리얼스, 인코포레이티드
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Publication of KR20210068588A publication Critical patent/KR20210068588A/ko

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Abstract

예컨대, 기판-레벨 패키징에서 사용되는, 기판들을 본딩하기 위한 방법들이 본원에서 제공된다. 일부 실시예들에서, 기판들을 본딩하기 위한 방법은: 제1 기판 및 제2 기판 각각 상에 적어도 하나의 재료를 증착하기 위해 ECD(electrochemical deposition)를 수행하는 단계, 제1 기판 및 제2 기판 각각 상에 본딩 계면을 형성하기 위해, 제1 기판 및 제2 기판에 대해 CMP(chemical mechanical polishing)를 수행하는 단계, 제1 기판 상의 본딩 계면이 제2 기판 상의 본딩 계면과 정렬되도록 제1 기판을 제2 기판 상에 포지셔닝하는 단계, 및 제1 기판 상의 본딩 계면 및 제2 기판 상의 본딩 계면을 사용하여 제1 기판을 제2 기판에 본딩하는 단계를 포함한다.

Description

기판들을 본딩하기 위한 방법들
[0001] 본 개시내용은 일반적으로 기판 프로세싱을 위한 방법들에 관한 것으로, 더 상세하게는, 예컨대 기판-레벨 패키징에서 사용되는, 기판들을 본딩하기 위한 방법들에 관한 것이다.
[0002] 현재의 구리-구리(Cu-Cu) 본딩 프로세싱 기법들은, 기판-레벨 패키징에 사용하기에 적절하지만, 하나 이상의 결점들을 갖는다. 예컨대, 기판-레벨 패키징 동안 고도로 산화될 수 있는 Cu 표면들을 서로 본딩하기에 충분한 본딩 강도를 달성하기 위해, 현재의 Cu-Cu 본딩 프로세싱 기법들은 약 300℃-400℃의 범위일 수 있는 온도들 및 수 메가파스칼(MPa)을 초과할 수 있는 본딩 압력들을 사용한다. 그러나, 그러한 높은 온도들/압력들을 사용하는 것은, 예컨대 기판 상의 Si와 본딩을 위해 사용되는 Cu 사이의 CTE(coefficient of thermal expansion) 불일치로 인해, Cu 표면을 포함하는 기판들(예컨대, 실리콘(Si) 기판들)이 서로 본딩될 때, 정렬 부정확성들을 초래할 수 있다. 더욱이, 그러한 높은 온도들/압력들은 때때로 하부 기판들 및/또는 하부 기판들 상에 형성된 회로들을 손상시킬 수 있다. 게다가, 현재의 Cu-Cu 본딩 프로세싱 기법들과 연관된 긴 프로세싱 시간들(이는 30분을 초과할 수 있음) 및 엄격한 진공 요건들(이는 Cu 표면 상의 산화를 감소시키는 데 필요함)은, 함께 본딩될 수 있는 기판들의 스루풋을 감소시키고 프로세싱 비용을 증가시킬 수 있다.
[0003] 따라서, 본 발명자들은 기판들을 프로세싱하기 위한 개선된 기법들을 제공하였다.
[0004] 예컨대, 기판-레벨 패키징에서 사용되는, 기판들을 본딩하기 위한 방법들이 본원에서 제공된다. 일부 실시예들에서, 기판들을 본딩하기 위한 방법들은: 제1 기판 및 제2 기판 각각 상에 적어도 하나의 재료를 증착하기 위해 ECD(electrochemical deposition)를 수행하는 단계, 제1 기판 및 제2 기판 각각 상에 본딩 계면을 형성하기 위해, 제1 기판 및 제2 기판에 대해 CMP(chemical mechanical polishing)를 수행하는 단계, 제1 기판 상의 본딩 계면이 제2 기판 상의 본딩 계면과 정렬되도록 제1 기판을 제2 기판 상에 포지셔닝하는 단계, 및 제1 기판 상의 본딩 계면 및 제2 기판 상의 본딩 계면을 사용하여 제1 기판을 제2 기판에 본딩하는 단계를 포함한다.
[0005] 일부 실시예들에서, 기판들을 본딩하기 위한 방법들은: 제1 기판 및 제2 기판 각각 상에 제1 재료를 증착하기 위해 PVD(physical vapor deposition)를 수행하는 단계, 제1 기판 및 제2 기판 각각 상에 제2 재료를 증착하기 위해 ECD를 수행하는 단계, 제1 기판 및 제2 기판 각각 상에 제2 재료의 본딩 계면을 형성하기 위해, 제1 기판 및 제2 기판에 대해 CMP를 수행하는 단계, 제1 기판 상의 본딩 계면이 제2 기판 상의 본딩 계면과 정렬되도록 제1 기판을 제2 기판 상에 포지셔닝하는 단계, 및 제1 기판 상의 본딩 계면 및 제2 기판 상의 본딩 계면을 사용하여 제1 기판을 제2 기판에 본딩하는 단계를 포함한다.
[0006] 일부 실시예들에서, 프로세서에 의해 실행될 때, 기판들을 본딩하기 위한 방법이 수행되게 하는 명령들이 저장된 비-일시적 컴퓨터 판독가능 저장 매체가 제공된다. 방법은 본원에서 개시되는 실시예들 중 임의의 실시예를 포함할 수 있다. 일부 실시예들에서, 방법은: 제1 기판 및 제2 기판 각각 상에 적어도 하나의 재료를 증착하기 위해 ECD를 수행하는 단계, 제1 기판 및 제2 기판 각각 상에 본딩 계면을 형성하기 위해, 제1 기판 및 제2 기판에 대해 CMP를 수행하는 단계, 제1 기판 상의 본딩 계면이 제2 기판 상의 본딩 계면과 정렬되도록 제1 기판을 제2 기판 상에 포지셔닝하는 단계, 및 제1 기판 상의 본딩 계면 및 제2 기판 상의 본딩 계면을 사용하여 제1 기판을 제2 기판에 본딩하는 단계를 포함한다.
[0007] 일부 실시예들에서, 기판들을 본딩하기 위한 방법들은: 제1 기판 및 제2 기판 각각 상에 적어도 하나의 재료를 증착하기 위해 그리고 제1 기판 및 제2 기판 각각 상에 본딩 계면을 형성하기 위해, ECD를 수행하는 단계, 제1 기판 상의 본딩 계면이 제2 기판 상의 본딩 계면과 정렬되도록 제1 기판을 제2 기판 상에 포지셔닝하는 단계, 및 제1 기판 상의 본딩 계면 및 제2 기판 상의 본딩 계면을 사용하여 제1 기판을 제2 기판에 본딩하는 단계를 포함한다.
[0008] 본 개시내용의 다른 그리고 추가적인 실시예들이 아래에서 설명된다.
[0009] 위에서 간략히 요약되고 아래에서 더 상세히 논의되는 본 개시내용의 실시예들은 첨부된 도면들에 도시된 본 개시내용의 예시적인 실시예들을 참조하여 이해될 수 있다. 그러나, 첨부된 도면들은 본 개시내용의 단지 전형적인 실시예들을 예시하는 것이므로 범위를 제한하는 것으로 간주되지 않아야 하는데, 이는 본 개시내용이 다른 균등하게 유효한 실시예들을 허용할 수 있기 때문이다.
[0010] 도 1은 본 개시내용의 적어도 일부 실시예들에 따른, 기판-레벨 패키징에서, 사용되는 기판들을 본딩하기 위한 방법의 흐름도이다.
[0011] 도 2a - 도 2g는 본 개시내용의 적어도 일부 실시예들에 따른, 도 1의 방법을 사용하여 형성된 기판의 개략도들이다.
[0012] 도 3은 본 개시내용의 적어도 일부 실시예들에 따른, 기판-레벨 패키징에서 사용되는, 기판들을 본딩하기 위한 방법의 흐름도이다.
[0013] 도 4a - 도 4c는 본 개시내용의 적어도 일부 실시예들에 따른, 도 3의 방법을 사용하여 형성된 기판의 개략도들이다.
[0014] 이해를 용이하게 하기 위해, 도면들에 대해 공통인 동일한 엘리먼트들을 지정하기 위해 가능한 경우 동일한 참조 번호들이 사용되었다. 도면들은 실척대로 그려지지 않으며, 명확성을 위해 단순화될 수 있다. 일 실시예의 엘리먼트들 및 특징들은 추가의 언급없이 다른 실시예들에 유익하게 통합될 수 있다.
[0015] 이제, 기판-레벨 패키징에서 사용되는, 구리-구리(Cu-Cu) 본딩을 위한 방법들이 본원에서 설명된다.
[0016] 도 1은 기판-레벨 패키징에서 사용되는, 기판들을 본딩하기 위한 방법의 흐름도이고, 도 2a - 도 2g는 본 개시내용의 적어도 일부 실시예들에 따른, 도 1의 방법을 사용하여 형성된 기판(200)의 개략도들이다.
[0017] 도 1의 방법을 수행하기 전에, 기판(200)은 하나 이상의 적절한 재료들 및 하나 이상의 종래의 전처리 기법들을 사용하여 미리-형성될 수 있다. 예컨대, 기판(200)의 전처리는, 실리콘(Si) 또는 다른 적절한 금속으로 형성되는 최하부 층(207), 최하부 층(207) 상에 증착되는 유전체 층(205)(예컨대, 산화물, 폴리머 등), 및 유전체 층(205) 상에 증착된 포토레지스트(PR) 층(203)을 포함하는 기판(200)에 대해 리소그래피 프로세스를 수행하는 것을 포함할 수 있다(도 2a). 리소그래피 프로세스가 완료된 후, PR 층(203), 및 유전체 층(205)의 일부를 제거하기 위해 기판(200)에 대해 에칭 및 PR 스트립 프로세스가 수행될 수 있다(도 2b). 기판(200)의 최하부 층(207) 및 유전체 층(205) 상에 하나 이상의 적절한 상호연결 재료들(201), 예컨대 구리(Cu), 알루미늄(Al), 또는 다른 적절한 재료들을 증착하기 위해, PVD(physical vapor deposition) 프로세스 및/또는 ECD 프로세스가 사용될 수 있다(도 2c). 그 후, CMP 프로세스가 상호연결 재료(201)의 일부를 제거하는 데 사용될 수 있으며, 그 위에 하나 이상의 재료들이 증착되어 2개의 기판들(200)을 서로 본딩하는 데 사용되는 본딩 계면을 형성할 수 있다(도 2d). 기판(200)에 대해 CMP 프로세스가 수행된 후에 기판(200)의 최하부 층(207) 및 유전체 층(205) 상에 남겨진 상호연결 재료(201)의 두께(또는 양)는, 하나 이상의 요인들, 예컨대 유전체 층(205)의 두께, 최하부 층(207)의 두께, 기판(200)의 의도된 용도 등에 따라 좌우될 수 있다.
[0018] 도 1의 방법에 따르면, 제1 기판(예컨대, 기판(200))과 제2 기판(예컨대, 기판(200)과 동일한 기판(200a)(도 2g))은 서로 본딩될 수 있다. 예시적인 목적들을 위해, 달리 언급되지 않는 한, 도 1의 방법은 기판(200)의 관점에서 설명된다. 102에서, 기판(200)의 상호연결 재료(201)의 표면 상에 하나 이상의 재료들을 증착하기 위해, 도 2d의 기판(200)(및 기판(200a))에 대해 ECD 프로세스가 수행된다. 상호연결 재료(201)의 표면 상에 증착될 수 있는 재료들은, 주석(Sn), 은(Ag), 납(Pb), 인듐(In), 비스무트(Bi), 금(Au) 또는 이들의 조합들(예컨대, (SnAg) 공융 솔더(202))을 포함할 수 있다(그러나 이에 제한되지 않음). 상호연결 재료(201)의 표면 상에 증착된 솔더(202)의 두께는 약 1 ㎛ 내지 약 5 ㎛의 범위일 수 있지만(도 2e), 솔더(202)의 두께는 1 ㎛ 미만 및 5 ㎛ 초과일 수 있고(도 2f), 상호연결 재료(201), 유전체 층(205), 최하부 층(207)의 특정 구성, 및/또는 제조사의 특정 제조 능력들을 수용하도록 조정될 수 있다.
[0019] 예컨대, 102에서 ECD 프로세스들이 상호연결 재료(201)의 표면 상으로의 솔더(202)의 제어된 증착(예컨대, 50 ㎚ 내지 약 100 ㎚의 범위의 두께(예컨대, 도 2f 참조))을 제공할 수 있는 경우, 102에서 EMP 프로세스를 사용하여 상호연결 재료(201)의 표면 상에 솔더(204)의 제어된 디싱부(dishing)/돌출부(protrusion) 또는 본딩 계면(계면 솔더(204))이 형성될 수 있는데, 즉, 계면 솔더(204)는 유전체 층(205)의 표면 너머로 연장되지 않도록 형성될 수 있다.
[0020] 대안적으로, 102에서의 EMP 프로세스가 상호연결 재료(201)의 표면 상으로의 솔더(202)의 제어된 증착을 제공할 수 없는 경우(도 2e), 104에서, 기판(200)의 상호연결 재료(201)의 표면 상에 계면 솔더(204)를 형성하는 것을 돕기 위해, 선택적 CMP 프로세스가 기판(200)(및 기판(200a))의 표면에 대해 수행된다(도 2f). 위에서 언급된 바와 같이, 상호연결 재료(201)의 표면 상에 남아 있는 계면 솔더(204)의 두께/양은 50 ㎚ 내지 약 100 ㎚의 범위일 수 있지만, 계면 솔더(204)의 두께는 50 ㎚ 미만 및 100 ㎚ 초과일 수 있다. 또한, 계면 솔더(204)의 두께는, 상호연결 재료(201), 유전체 층(205) 및/또는 최하부 층(207)의 특정 구성을 수용하도록 조정될 수 있다.
[0021] 기판(200)을 기판(200a)에 본딩하기 위해, 106에서, 2개의 기판들(200, 200a) 상의 계면 솔더(204, 204a)가 서로 정렬되도록, 2개의 기판들(200, 200a)이 서로의 최상부 상에 놓이는 식으로 포지셔닝될 수 있다(도 2g). 일단 정렬되면, 108에서, 계면 솔더(204, 204a)를 사용하여 기판들(200, 200a)을 서로 본딩하기 위해, 열압축(thermocompression) 본딩, 하이브리드 본딩, 또는 다른 알려진 본딩 프로세스를 포함하는(그러나 이에 제한되지 않음) 하나 이상의 알려진 본딩 프로세스들이 사용될 수 있다. 본딩 프로세스들은 대기압에서 수행될 수 있고, 본딩 프로세스들이 수행될 수 있는 온도는 230℃ 미만 및 250℃ 초과일 수 있지만, 이 온도는 약 230℃ 내지 약 250℃의 범위일 수 있는데, 즉, 계면 솔더(204)는 비교적 낮은 용융점을 갖는 재료들(예컨대, 공융 솔더(202))을 사용하여 형성되기 때문이다.
[0022] 2개의 기판들(200, 200a)이 계면 솔더(204, 204a)에서 서로 본딩된 후에, 기판들(200, 200a)의 유전체 층(205, 205a)의 본딩되지 않은 표면들 사이에 어떤 갭도 존재하지 않으면서, 2개의 기판들(200, 200a) 사이의 미세 피치 상호연결이 달성된다.
[0023] 도 3은 제1 기판(예컨대, 기판(400)(도 4a 및 도 4b))을 제2 기판(예컨대, 기판(400)과 동일한 기판(400a)(도 4c))에 본딩하기 위한 방법의 흐름도이다. 기판들(400, 400a)을 형성하는 데 사용되는 도 3의 방법은 도 2a - 도 2g의 기판들(200, 200a)을 형성하는 데 사용되는 방법과 실질적으로 동일하다. 따라서, 기판들(400, 400a)을 형성하기 위한 방법에 고유한 그러한 특징들만이 본원에서 설명된다. 예시적인 목적들을 위해, 달리 언급되지 않는 한, 도 3의 방법은 기판(400)의 관점에서 설명된다.
[0024] 기판(400)(및 기판(400a))에 대해 ECD 프로세스를 수행하기 전에, 300에서, 상호연결 재료(401)(그리고 유사하게, 기판(400a) 상의 상호연결 재료(401a)) 상에 하나 이상의 적절한 재료들의 층을 증착하기 위해 기판(400)(및 기판(400a))에 대해 PVD 프로세스가 수행되며, 이는 솔더(402)가 부착될 표면을 제공할 수 있다. 예컨대, Cu, 티타늄(Ti), 또는 이들의 조합의 층(406)이 상호연결 재료(401) 상에 증착될 수 있다. 층(406)의 두께는 0.1 ㎛ 미만 및 1 ㎛ 초과일 수 있지만, 층(406)의 두께는 0.1 ㎛ 내지 약 1 ㎛의 범위일 수 있다. 층(406)의 두께는, 상호연결 재료(401), 유전체(405), 최하부 층(407), 및/또는 층(406) 상에 증착될 솔더(402)의 특정 구성을 수용하도록 조정될 수 있다.
[0025] 302에서, (102에서의 ECD 프로세스와 같이) 층(406)의 표면 상에 솔더(402)를 증착하기 위해, 기판(400)(및 기판(400a))에 대해 ECD 프로세스가 수행된다. 302에서 ECD 프로세스를 수행하기 전에, 원하는 두께의 층(406)을 획득하는 것을 돕기 위해, 하나 이상의 다른 프로세스들, 예컨대 에칭 프로세스, CMP 프로세스 등이 층(406)에 대해 수행될 수 있다.
[0026] 302에서 솔더(402)가 층(406)의 표면 상에 증착된 후에, 304에서 기판(400)(및 기판(400a))에 대해 (104에서의 CMP 프로세스와 같은) CMP 프로세스가 수행될 수 있다. CMP 프로세스는 계면 솔더(404, 404a)의 층을 생성하기 위해 과잉 솔더(402, 402a)를 제거한다. 기판들(400, 400a)을 서로 본딩하기 위해, 306에서, 2개의 기판들(400, 400a) 상의 층들(406, 406a)(예컨대, CPM 프로세스가 수행된 후의 층들(406, 406a)의 나머지 부분들)과 계면 솔더(404, 404a)가 서로 정렬되도록(도 4c), 2개의 기판들(400, 400a)은 초기에, 서로의 최상부 상에 놓이는 식으로 포지셔닝될 수 있다. 일단 정렬되면, 308에서, 2개의 기판들(400, 400a)을 서로 본딩하기 위해, 위에서 설명된 본딩 프로세스들이 수행될 수 있다.
[0027] 본원에서 설명된 기판들을 본딩하기 위한 방법들은 기판-레벨 패키징을 위한 비교적 간단하고 비용 효율적인 방식을 제공하며, 종래의 기판 본딩 프로세스들과 전형적으로 연관되는 결점들을 극복한다. 더 구체적으로, 본원에서 설명된 본딩 프로세스들은, 위에서 언급된 바와 같이, 예컨대 300℃-400℃ 및 수 MPa의 높은 온도/압력을 사용하는 종래의 본딩 프로세스들과 비교할 때, 2개의 기판들(200/200a, 400/400a)을 서로 본딩하기 위해 비교적 낮은 온도/압력을 사용한다.
[0028] 전술한 바가 본 개시내용의 실시예들에 관한 것이지만, 본 개시내용의 다른 그리고 추가적인 실시예들이, 본 개시내용의 기본적인 범위를 벗어나지 않으면서 안출될 수 있다.

Claims (15)

  1. 기판들을 본딩하기 위한 방법으로서,
    제1 기판 및 제2 기판 각각 상에 적어도 하나의 재료를 증착하기 위해 ECD(electrochemical deposition)를 수행하는 단계;
    상기 제1 기판 및 상기 제2 기판 각각 상에 본딩 계면을 형성하기 위해, 상기 제1 기판 및 상기 제2 기판에 대해 CMP(chemical mechanical polishing)를 수행하는 단계;
    상기 제1 기판 상의 본딩 계면이 상기 제2 기판 상의 본딩 계면과 정렬되도록 상기 제1 기판을 상기 제2 기판 상에 포지셔닝하는 단계; 및
    상기 제1 기판 상의 본딩 계면 및 상기 제2 기판 상의 본딩 계면을 사용하여 상기 제1 기판을 상기 제2 기판에 본딩하는 단계를 포함하는,
    기판들을 본딩하기 위한 방법.
  2. 제1 항에 있어서,
    상기 적어도 하나의 재료는 Sn, Ag, Pb, In, Bi, 또는 Au 중 적어도 하나인,
    기판들을 본딩하기 위한 방법.
  3. 제2 항에 있어서,
    상기 제1 기판 및 상기 제2 기판 중 적어도 하나는 Cu 또는 Al 중 적어도 하나, 및 Si, 산화물, 또는 폴리머 중 적어도 하나를 포함하고, 그리고
    상기 적어도 하나의 재료는 Cu 또는 Al 중 적어도 하나 상에 증착되는,
    기판들을 본딩하기 위한 방법.
  4. 제1 항 내지 제3 항 중 어느 한 항에 있어서,
    상기 적어도 하나의 재료는 상기 제1 기판 및 상기 제2 기판 각각 상에 5 ㎛를 초과하지 않는 두께로 증착되는,
    기판들을 본딩하기 위한 방법.
  5. 제1 항 내지 제3 항 중 어느 한 항에 있어서,
    CMP가 수행된 후, 상기 제1 기판 상의 본딩 계면 및 상기 제2 기판 상의 본딩 계면 각각은 100 ㎚를 초과하지 않는 두께를 갖는,
    기판들을 본딩하기 위한 방법.
  6. 제1 항 내지 제3 항 중 어느 한 항에 있어서,
    상기 제1 기판을 상기 제2 기판에 본딩하는 단계는 대기압에서 수행되는,
    기판들을 본딩하기 위한 방법.
  7. 제1 항 내지 제3 항 중 어느 한 항에 있어서,
    상기 제1 기판을 상기 제2 기판에 본딩하는 단계는 250℃를 초과하지 않는 온도에서 수행되는,
    기판들을 본딩하기 위한 방법.
  8. 기판들을 본딩하기 위한 방법으로서,
    제1 기판 및 제2 기판 각각 상에 제1 재료를 증착하기 위해 PVD(physical vapor deposition)를 수행하는 단계;
    상기 제1 기판 및 상기 제2 기판 각각 상에 제2 재료를 증착하기 위해 ECD(electrochemical deposition)를 수행하는 단계;
    상기 제1 기판 및 상기 제2 기판 각각 상에 상기 제2 재료의 본딩 계면을 형성하기 위해, 상기 제1 기판 및 상기 제2 기판에 대해 CMP(chemical mechanical polishing)를 수행하는 단계;
    상기 제1 기판 상의 본딩 계면이 상기 제2 기판 상의 본딩 계면과 정렬되도록 상기 제1 기판을 상기 제2 기판 상에 포지셔닝하는 단계; 및
    상기 제1 기판 상의 본딩 계면 및 상기 제2 기판 상의 본딩 계면을 사용하여 상기 제1 기판을 상기 제2 기판에 본딩하는 단계를 포함하는,
    기판들을 본딩하기 위한 방법.
  9. 제8 항에 있어서,
    상기 제1 재료는 Ti, Cu, 및 이들의 조합들 중 하나이고, 그리고 상기 제2 재료는 Sn, Ag, Pb, In, Bi, 또는 Au 중 하나인,
    기판들을 본딩하기 위한 방법.
  10. 제9 항에 있어서,
    상기 제1 기판 및 상기 제2 기판 중 적어도 하나는 Cu 또는 Al 중 적어도 하나, 및 Si, 산화물, 또는 폴리머 중 적어도 하나를 포함하고, 그리고
    상기 제1 재료는 Cu 또는 Al 중 적어도 하나 상에 증착되고, 그리고 상기 제2 재료는 상기 제1 재료 상에 증착되는,
    기판들을 본딩하기 위한 방법.
  11. 제8 항 내지 제10 항 중 어느 한 항에 있어서,
    상기 제1 재료는 1 ㎛를 초과하지 않는 두께로 증착되고, 그리고 상기 제2 재료는 5 ㎛를 초과하지 않는 두께로 증착되는,
    기판들을 본딩하기 위한 방법.
  12. 제8 항 내지 제10 항 중 어느 한 항에 있어서,
    CMP가 수행된 후, 상기 제1 기판 상의 제1 재료와 본딩 계면은 100 ㎚를 초과하지 않는 조합된 두께를 갖고, 그리고 상기 제2 기판 상의 제1 재료와 본딩 계면은 100 ㎚를 초과하지 않는 조합된 두께를 갖는,
    기판들을 본딩하기 위한 방법.
  13. 제8 항 내지 제10 항 중 어느 한 항에 있어서,
    상기 제1 기판을 상기 제2 기판에 본딩하는 단계는 대기압에서 수행되는,
    기판들을 본딩하기 위한 방법.
  14. 제8 항 내지 제10 항 중 어느 한 항에 있어서,
    상기 제1 기판을 상기 제2 기판에 본딩하는 단계는 250℃를 초과하지 않는 온도에서 수행되는,
    기판들을 본딩하기 위한 방법.
  15. 프로세서에 의해 실행될 때, 기판들을 본딩하기 위한 방법을 수행하는 명령들이 저장된 비-일시적 컴퓨터 판독가능 저장 매체로서,
    상기 방법은,
    제1 기판 및 제2 기판 각각 상에 적어도 하나의 재료를 증착하기 위해 ECD(electrochemical deposition)를 수행하는 단계;
    상기 제1 기판 및 상기 제2 기판 각각 상에 본딩 계면을 형성하기 위해, 상기 제1 기판 및 상기 제2 기판에 대해 CMP(chemical mechanical polishing)를 수행하는 단계;
    상기 제1 기판 상의 본딩 계면이 상기 제2 기판 상의 본딩 계면과 정렬되도록 상기 제1 기판을 상기 제2 기판 상에 포지셔닝하는 단계; 및
    상기 제1 기판 상의 본딩 계면 및 상기 제2 기판 상의 본딩 계면을 사용하여 상기 제1 기판을 상기 제2 기판에 본딩하는 단계를 포함하는,
    비-일시적 컴퓨터 판독가능 저장 매체.
KR1020217016196A 2018-10-29 2019-10-28 기판들을 본딩하기 위한 방법들 KR20210068588A (ko)

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US11309278B2 (en) * 2018-10-29 2022-04-19 Applied Materials, Inc. Methods for bonding substrates
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US11935824B2 (en) 2021-09-29 2024-03-19 Microchip Technology Incorporated Integrated circuit package module including a bonding system
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Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4418858A (en) 1981-01-23 1983-12-06 Miller C Fredrick Deep bonding methods and apparatus
US5364004A (en) 1993-05-10 1994-11-15 Hughes Aircraft Company Wedge bump bonding apparatus and method
JP3644205B2 (ja) 1997-08-08 2005-04-27 株式会社デンソー 半導体装置及びその製造方法
US6350632B1 (en) 2000-09-20 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with ball bond connection joint
US6492252B1 (en) 2000-10-13 2002-12-10 Bridge Semiconductor Corporation Method of connecting a bumped conductive trace to a semiconductor chip
US7129575B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped metal pillar
KR20140140042A (ko) 2012-03-07 2014-12-08 도레이 카부시키가이샤 반도체 장치의 제조 방법 및 반도체 장치의 제조 장치
JPWO2014184988A1 (ja) 2013-05-16 2017-02-23 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
JP6069153B2 (ja) 2013-09-27 2017-02-01 デクセリアルズ株式会社 アンダーフィル材、及びこれを用いた半導体装置の製造方法
US9831154B2 (en) * 2014-07-14 2017-11-28 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacuting method of the same
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US20180233479A1 (en) 2017-02-16 2018-08-16 Nanya Technology Corporation Semiconductor apparatus and method for preparing the same
KR102246469B1 (ko) * 2017-07-21 2021-05-03 한국전자통신연구원 가역 전기화학 거울
US10622321B2 (en) * 2018-05-30 2020-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structures and methods of forming the same
US11309278B2 (en) * 2018-10-29 2022-04-19 Applied Materials, Inc. Methods for bonding substrates

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