KR20140040745A - 반도체 장치의 제조 방법 및 반도체 장치 - Google Patents
반도체 장치의 제조 방법 및 반도체 장치 Download PDFInfo
- Publication number
- KR20140040745A KR20140040745A KR1020137033054A KR20137033054A KR20140040745A KR 20140040745 A KR20140040745 A KR 20140040745A KR 1020137033054 A KR1020137033054 A KR 1020137033054A KR 20137033054 A KR20137033054 A KR 20137033054A KR 20140040745 A KR20140040745 A KR 20140040745A
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- KR
- South Korea
- Prior art keywords
- electrode
- circuit
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- signal
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 414
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 59
- 239000004020 conductor Substances 0.000 claims abstract description 104
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 238000012360 testing method Methods 0.000 claims abstract description 30
- 238000003475 lamination Methods 0.000 claims abstract description 11
- 238000010030 laminating Methods 0.000 claims abstract description 7
- 238000005304 joining Methods 0.000 claims abstract description 5
- 230000002950 deficient Effects 0.000 claims description 207
- 238000000034 method Methods 0.000 claims description 122
- 239000011810 insulating material Substances 0.000 claims description 94
- 238000006243 chemical reaction Methods 0.000 claims description 60
- 230000015572 biosynthetic process Effects 0.000 claims description 33
- 238000007747 plating Methods 0.000 claims description 18
- 230000000149 penetrating effect Effects 0.000 claims description 17
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 5
- 230000035515 penetration Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 148
- 238000010586 diagram Methods 0.000 description 35
- 239000011159 matrix material Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 239000000523 sample Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000007689 inspection Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
- G11C29/883—Masking faults in memories by using spares or by reconfiguring with partially good memories using a single defective memory device with reduced capacity, e.g. half capacity
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JPJP-P-2011-135276 | 2011-06-17 | ||
JP2011135273 | 2011-06-17 | ||
JPJP-P-2011-135273 | 2011-06-17 | ||
JPJP-P-2011-135279 | 2011-06-17 | ||
JP2011135279 | 2011-06-17 | ||
JP2011135276 | 2011-06-17 | ||
PCT/JP2012/065400 WO2012173238A1 (ja) | 2011-06-17 | 2012-06-15 | 半導体装置の製造方法及び半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20140040745A true KR20140040745A (ko) | 2014-04-03 |
Family
ID=47357215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020137033054A KR20140040745A (ko) | 2011-06-17 | 2012-06-15 | 반도체 장치의 제조 방법 및 반도체 장치 |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPWO2012173238A1 (ja) |
KR (1) | KR20140040745A (ja) |
TW (1) | TW201306173A (ja) |
WO (1) | WO2012173238A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013021847A1 (ja) * | 2011-08-11 | 2013-02-14 | 東京エレクトロン株式会社 | 半導体装置の製造方法、半導体装置及び配線形成用治具 |
JP2014107469A (ja) * | 2012-11-29 | 2014-06-09 | Tokyo Electron Ltd | 半導体装置の製造方法及び製造装置 |
US11056463B2 (en) * | 2014-12-18 | 2021-07-06 | Sony Corporation | Arrangement of penetrating electrode interconnections |
WO2017126014A1 (ja) * | 2016-01-18 | 2017-07-27 | ウルトラメモリ株式会社 | 積層型半導体装置及びその製造方法 |
KR102391499B1 (ko) * | 2017-08-11 | 2022-04-28 | 에스케이하이닉스 주식회사 | 저장 장치 및 그 동작 방법 |
JP2022138014A (ja) | 2021-03-09 | 2022-09-22 | キオクシア株式会社 | 半導体装置の製造方法、半導体製造システム、及び半導体装置 |
CN117042453A (zh) * | 2022-04-29 | 2023-11-10 | 华为技术有限公司 | 存储芯片、通孔结构的制备方法、存储器及电子设备 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003059288A (ja) * | 2001-08-09 | 2003-02-28 | Mitsubishi Electric Corp | 半導体装置 |
JP5697898B2 (ja) * | 2009-10-09 | 2015-04-08 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及びその製造方法 |
-
2012
- 2012-06-15 JP JP2013520604A patent/JPWO2012173238A1/ja active Pending
- 2012-06-15 KR KR1020137033054A patent/KR20140040745A/ko not_active Application Discontinuation
- 2012-06-15 WO PCT/JP2012/065400 patent/WO2012173238A1/ja active Application Filing
- 2012-06-15 TW TW101121677A patent/TW201306173A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
TW201306173A (zh) | 2013-02-01 |
JPWO2012173238A1 (ja) | 2015-02-23 |
WO2012173238A1 (ja) | 2012-12-20 |
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WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |