KR20110139105A - Substrate with fine metal pattern, print circuit board and semiconductor device, and production method of substrate with fine metal pattern, print curcuit board and semiconductor device - Google Patents

Abstract

PURPOSE: A substrate with a fine metal pattern, a print circuit board, a semiconductor apparatus, and a method for manufacturing a substrate with a fine metal pattern and a print circuit board are provided to reduce reaction active field which is generated by a metal micro pattern. CONSTITUTION: A metal micro pattern(7b') is filled in a recess(9). The recess is prepared in a support surface which consists of a resin. A part, which is not touched with the surface of the recess in a metal micro pattern area, is coated with a nickel-palladium-gold plated layer(8). The ratio of a shortest distance between patterns and the projection height of the metal micro pattern is below 0.8 in the area of the nickel-palladium-gold plated layer.

Description

Substrate with FINE METAL PATTERN, PRINT CIRCUIT BOARD AND SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD OF SUBSTRATE WITH FINE METAL PATTERN, PRINT CURCUIT BOARD AND SEMICONDUCTOR DEVICE}

TECHNICAL FIELD This invention relates to the base material with a metal fine pattern, a printed wiring board, a semiconductor device, and its manufacturing method.

The circuit on a printed wiring board is gold-plated for the purpose of ensuring connection reliability, such as solder joint and wire bonding.

As one of the typical methods of gold plating, there is an electroless nickel-gold plating method. In this method, after a pretreatment is performed to a plating target by suitable methods, such as a cleaner, a palladium catalyst is given, and after that, an electroless nickel plating process and an electroless gold plating process are further performed in order. ENIG (Electroless Nickel Immersion Gold) is one of the electroless nickel-gold plating methods, and is a method of performing the Immersion Gold in the electroless gold plating step.

In the case where the terminal portion is gold plated by the ENIG method, nickel is diffused on the gold film when the heat treatment is performed in order to wire-bond the terminal portion, thereby deteriorating connection reliability. For the problem of nickel diffusion, heat resistance can be ensured by further adding a gold electroless plating treatment on the nickel-gold film to increase the film thickness of gold.

However, from the viewpoint of environmental measures, the melting temperature of lead-free soldering, which is considered essential in the future, is about 260 ° C, which is higher than that of conventional solder soldering. For this reason, in consideration of lead-free soldering, the gold plating of the terminal portion needs to be more heat resistant than before. In the ENIG method, it may not be possible to cope with the high temperature heating at the time of lead-free soldering, and there is a problem that the higher the film thickness of the gold, the higher the cost in order to secure high heat resistance. .

In order to solve this problem, application of the electroless nickel-palladium-gold plating method is beginning to be examined. In this method, after the electroless nickel plating treatment of the electroless nickel-gold plating method, the electroless palladium plating treatment is performed, followed by the gold plating treatment.

ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) is one of the electroless nickel-palladium-gold plating methods. (Patent document 1). In the electroless nickel-palladium-gold plating method, it is possible to prevent the diffusion of conductor materials and to improve corrosion resistance, nickel oxidation prevention and diffusion prevention in circuits or terminal portions. In addition, the electroless nickel-palladium-gold plating method can prevent nickel oxidation by gold by providing an electroless palladium plating film, so that the reliability of lead-free solder joints with a large thermal load is improved, and further, the film thickness of gold is improved. Since the diffusion of nickel does not occur even if it is not thickened, there is an advantage that the cost can be reduced compared to the electroless nickel-gold plating method.

Japanese Patent Laid-Open No. 2008-144188

As described above, the electroless nickel-palladium-gold plating method has higher connection reliability with respect to high heat loads than the electroless nickel-gold plating method. However, when electroless nickel-palladium-gold plating is applied to a circuit of a printed wiring board, metal is abnormally precipitated around the terminal portion of the surface of the resin supporting the conductor circuit in the electroless palladium plating step, thereby improving the quality of the plated surface. It has been found to drop and cause a short between adjacent terminals in severe cases.

In addition, it has also been found that with the miniaturization of circuits, the narrower the circuit spacing, the easier the occurrence of abnormal precipitation on the resin surface between adjacent conductor circuits.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention is directed to a terminal portion of a printed wiring board, a conductor circuit surface of an electronic component other than the printed wiring board, and a surface of a metal fine pattern supported on a resin substrate as a target of plating treatment. It is an object of the present invention to provide a method for producing a plated product that can suppress abnormal deposition of metal on the underlying resin surface when electroless nickel-palladium-gold plating is performed on a surface to be plated. .

Furthermore, an object of this invention is to provide the base material with a metal micropattern, a printed wiring board, and a semiconductor device which have a plating process surface excellent in quality.

The said object is achieved by following invention (1)-(15).

(1) As a base material with a metal fine pattern,

At least the lower part of the metal fine pattern is embedded in the groove provided in the support surface which consists of resin,

A portion of the metal micropattern not in contact with the surface of the groove in at least a portion of the metal fine pattern is covered with a nickel-palladium-gold plating layer,

The protruding height from the support surface of the metal fine pattern in the region having the nickel-palladium-gold plating layer is set to X (where X = 0 (zero) is regarded as X = 0), and the minimum distance between patterns The ratio (X / Y) at the time of making Y into Y is less than 0.8, The base material with a metal fine pattern characterized by the above-mentioned.

(2) The base material with a metal fine pattern as described in said (1) whose line and space (L / S) of the area | region which has the nickel-palladium-gold plating layer of the said metal fine pattern is 5-100 micrometers / 5-100 micrometers.

(3) As a printed wiring board,

At least a lower portion of the conductor circuit is embedded in a groove provided in a support surface made of a core substrate or an insulating layer,

A portion of the at least part of the conductor circuit which is not in contact with the surface of the groove is covered with a nickel-palladium-gold plating layer,

The protruding height from the support surface of the conductor circuit in the region having the nickel-palladium-gold plated layer is X (where X = 0 (zero) is assumed to be X = 0), and the minimum distance between circuit patterns The ratio (X / Y) at the time of making Y into Y is less than 0.8, The printed wiring board characterized by the above-mentioned.

(4) The printed wiring board as described in said (3) whose line and space (L / S) of the area | region which has the nickel-palladium-gold plating layer of the said conductor circuit is 5-100 micrometers / 5-100 micrometers.

(5) The printed wiring board according to (3) or (4) above, wherein the region having the nickel-palladium-gold plating layer of the conductor circuit is a region in which a terminal is formed.

(6) A semiconductor device comprising a semiconductor element mounted on a printed wiring board as described in (5) above, wherein a terminal of the printed wiring board and an entry / exit part of the semiconductor element are connected.

(7) As a manufacturing method of a base material with a metal fine pattern,

Preparing a substrate for processing in which at least a lower portion of the metal fine pattern is embedded in a groove provided on a support surface made of resin;

Performing electroless nickel-palladium-gold plating on a portion not in contact with the surface of the groove in at least a part of the metal fine pattern of the substrate for processing;

The protrusion height from the support surface in the region where the fine metal pattern is subjected to electroless nickel-palladium-gold plating is X (except X = 0, where X = 0), and the pattern The manufacturing method of the base material with a metal micropattern characterized by making ratio (X / Y) at the time of making the minimum distance between Y into less than 0.8.

(8) The metal fine metal as described in said (7) which makes the line and space (L / S) of the area | region which electroless nickel-palladium-gold plating of the said metal fine pattern be 5-100 micrometers / 5-100 micrometers. The manufacturing method of a base material with a pattern.

(9) Said (7) or (8) which forms a metal fine pattern by forming a groove | channel by a laser in the support surface of a process substrate, and depositing metal in the said groove | channel in the process of preparing the said base material for a process. The manufacturing method of the base material with a metal fine pattern of description.

(10) In the step of preparing the substrate for treatment, the metal micropattern according to the above (7) or (8), wherein the metal fine pattern of the metal fine pattern transfer sheet is transferred to a support surface on which the substrate for treatment is heat-softened. The manufacturing method of an adhesion base material.

(11) As a manufacturing method of a printed wiring board,

Preparing a processing wiring board in which at least a lower portion of the conductor circuit is embedded in a groove provided in a support surface made of a core substrate or an insulating layer;

And performing electroless nickel-palladium-gold plating on a portion of the processing circuit board not in contact with the surface of the groove in at least a part of the conductor circuit.

The projected height from the support surface in the region where the electroless nickel-palladium-gold plating of the conductor circuit is to be performed is assumed to be X (where X = 0 when X≤0 (zero)), and the circuit pattern The manufacturing method of the printed wiring board which makes ratio (X / Y) at the time of making the minimum distance between them Y be less than 0.8.

(12) of the printed wiring board according to the above (11), wherein the line and space (L / S) of the region where the electroless nickel-palladium-gold plating of the conductor circuit is to be made 5 to 100 µm / 5 to 100 µm; Manufacturing method.

(13) The manufacturing method of the printed wiring board as described in said (11) or (12) whose area | region which performs nickel-palladium-gold plating of the said conductor circuit is a area | region which forms a terminal.

(14) In the process of preparing the processing wiring board, the grooves are formed on the support surface of the processing wiring board by a laser, and the above-mentioned (11) to (13) to form a conductor circuit by depositing a metal on the groove. The manufacturing method of the printed wiring board of any one of Claims 1.

(15) The process according to any one of the above (11) to (13), wherein the conductor circuit of the conductor circuit transfer sheet is transferred to a support surface on which the processing circuit board is heat-softened in the step of preparing the processing wiring board. Method of manufacturing a wiring board.

According to the present invention, by embedding the metal fine pattern of the substrate with a metal fine pattern on the resin surface and plating the surface of the exposed conductor circuit, the exposed area of the conductor circuit to the plating bath is reduced, so that the presence of the metal fine pattern The reaction active field (the space where the reaction activity of a plating bath is high) produced by it can be made small.

In addition, by embedding the metal fine pattern on the resin surface, the circuit irregularities (the difference between the heights of the circuit top and the resin surface) of the resin surface are reduced, so that the resin surface is cleaned and the palladium catalyst is removed.

Therefore, according to this invention, abnormal precipitation of the metal around the metal fine pattern of a base material with a metal fine pattern can be prevented.

Furthermore, in the present invention, since the conductor circuit is embedded in the resin surface in order to reduce the exposed area of the metal fine pattern, it is not necessary to make the thickness of the metal fine pattern thin (the circuit cross-sectional area small). Therefore, according to the present invention, it is possible not only to prevent abnormal deposition of metal, but also to avoid the problem of slow signal transmission speed.

The present invention can also be preferably applied to the surface of conductor circuits of electronic components other than printed wiring boards, and furthermore preferably applied to plating of metal fine patterns supported on resin substrates in various fields other than electronic components. It is possible to obtain a high quality plated surface.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows typically the cross section of an example of the printed wiring board which belongs to this invention.
2 is an enlarged plan view of a part of a terminal region of a printed wiring board.
FIG. 3 is a diagram schematically illustrating an AA cross section in FIG. 2.
It is a figure which shows typically the cross section of the part in which the conductor circuit layer was embedded in the groove | channel.
5 is a conceptual diagram illustrating the relationship between the projecting height X from the support surface of the metal fine pattern and the minimum distance Y between the patterns.
It is a figure which shows typically the cross section of only one surface of the semiconductor device which concerns on this invention.
FIG. 7A is a diagram of only one surface illustrating a procedure (overall) by laser processing. FIG.
FIG. 7B is a diagram of only one side illustrating the procedure (second half) by laser processing. FIG.
8 is a block diagram showing the sequence of electroless nickel-palladium-gold plating.

When electroless nickel-palladium-gold plating is performed to the conductor circuit of a printed wiring board, the cause of abnormal precipitation around a conductor circuit is considered as follows.

When electroless nickel-palladium-gold plating is performed on the conductor circuit of the printed wiring board, nickel electroless plating is performed after the palladium catalyst is applied to the surface to be treated as a pretreatment, but selectively on the surface of the terminal in the step of applying the palladium catalyst. it is that it is difficult to completely remove the Pd ^{2 +} ion from the resin support chain surface state in which a sufficient amount of adhesion to metal Pd is thought to be one of the causes. A Pd ^{2 +} ion remains in the resin surface is electroless and reduced width of zero in a palladium plating bath, a reduced Pd is the nucleus is considered that the growth is metal Pd particles.

Further, the reason why abnormal precipitation occurs locally on the resin surface around the conductor circuit is that the reaction activity of the plating bath is increased in the vicinity of the terminal, so that nickel is eluted from the nickel film and Ni to Pd is formed on the resin surface near the nickel elution point. substituted (elution Ni + resin surface ^{Pd 2 + → Ni 2 + +} Pd) this is thought to be due to the bundle.

In particular, the region sandwiched between the conductor circuits adjacent to each other is considered to be extremely high in the reaction activity of the plating bath because the conductor circuit is a dense space. In addition, as the circuit becomes finer and the distance between the conductor circuits becomes smaller, the degree of compactness of the conductor circuits increases. Therefore, it is considered that the reaction activity of the plating bath increases in the region sandwiched between adjacent conductor circuits.

MEANS TO SOLVE THE PROBLEM This inventor discovered that it becomes possible to suppress metal precipitation around a conductor circuit, and to suppress metal precipitation of the area | region sandwiched between adjacent conductor circuits by embedding a conductor circuit in the resin surface.

By embedding the conductor circuit on the resin surface, the exposed area of the conductor circuit to the plating bath is reduced, so that the reaction active field (space with high reaction activity of the plating bath) caused by the presence of the conductor circuit can be reduced.

In addition, by embedding the conductor circuit in the resin surface, the circuit irregularities (difference in height between the circuit top and the resin surface) of the resin surface are reduced, so that the resin surface is cleaned and the palladium catalyst is removed.

Even if the conductor circuit is embedded in the resin surface, even if the thickness of the conductor circuit is reduced (lower in height), it is possible to reduce the exposed area of the conductor circuit to the plating bath and to reduce the circuit irregularities on the resin surface. In this case, since the cross-sectional area of the conductor circuit is small, there is a problem that the electrical resistance is increased and the signal transmission speed is slowed. In particular, the finer the circuit, the greater the problem that the transmission speed of such a signal becomes slower.

On the other hand, in the present invention, since the conductor circuit is embedded in the resin surface in order to reduce the exposed area of the conductor circuit, the thickness of the conductor circuit does not need to be reduced. Therefore, according to the present invention, it is possible not only to prevent abnormal deposition of metal, but also to avoid the problem of slow signal transmission speed.

In addition, as described above, abnormal deposition during electroless nickel-palladium-gold plating on the conductor circuit of the printed wiring board is more likely to occur as the distance between the conductor circuits becomes smaller due to the miniaturization of the conductor circuit, and also the signal transmission. Although the speed also becomes slower as the cross sectional area of the circuit becomes smaller due to the miniaturization of the conductor circuit, the present invention can effectively prevent metal precipitation when electroless nickel-palladium-gold plating is applied to the miniaturized conductor circuit. The problem of slow signal transmission speed can be avoided.

The present invention can also be preferably applied to the surface of conductor circuits of electronic components other than printed wiring boards, and furthermore, it can be preferably used even when plating metal fine patterns supported on resin substrates in various fields other than electronic components. As a result, a high quality plated surface can be obtained.

The following invention is provided based on the said knowledge.

Substrate with a metal fine pattern of the present invention

At least the lower part of the metal fine pattern is embedded in the groove provided in the support surface which consists of resin,

A portion of the metal micropattern not in contact with the surface of the groove in at least a portion of the metal fine pattern is covered with a nickel-palladium-gold plating layer,

The protruding height from the support surface of the metal fine pattern in the region having the nickel-palladium-gold plating layer is set to X (where X = 0 (zero) is regarded as X = 0), and the minimum distance between patterns It is characterized by the ratio (X / Y) at which Y is made less than 0.8.

In addition, the printed wiring board of the present invention

At least a lower portion of the conductor circuit is embedded in a groove provided in a support surface made of a core substrate or an insulating layer,

A portion of the at least part of the conductor circuit which is not in contact with the surface of the groove is covered with a nickel-palladium-gold plating layer,

The protruding height from the support surface of the conductor circuit in the region having the nickel-palladium-gold plated layer is X (where X = 0 (zero) is assumed to be X = 0), and the minimum distance between circuit patterns It is characterized by the ratio (X / Y) at which Y is made less than 0.8.

Moreover, the semiconductor device of this invention mounts a semiconductor element on the said printed wiring board of this invention, and is connected with the terminal of the said printed wiring board and the entry / exit part of a semiconductor element. It is characterized by the above-mentioned.

Moreover, the manufacturing method of the base material with a metal micropattern of this invention

Preparing a substrate for processing in which at least a lower portion of the metal fine pattern is embedded in a groove provided on a support surface made of resin;

Performing electroless nickel-palladium-gold plating on a portion not in contact with the surface of the groove in at least a part of the metal fine pattern of the substrate for processing;

The protrusion height from the support surface in the region where the fine metal pattern is subjected to electroless nickel-palladium-gold plating is X (except X = 0, where X = 0), and the pattern It is characterized by making ratio (X / Y) at the time of making the minimum distance between Y into less than 0.8.

Moreover, the manufacturing method of the printed wiring board of this invention is

Preparing a processing wiring board in which at least a lower portion of the conductor circuit is embedded in a groove provided in a support surface made of a core substrate or an insulating layer;

And performing electroless nickel-palladium-gold plating on a portion of the processing circuit board not in contact with the surface of the groove in at least a part of the conductor circuit.

The projected height from the support surface in the region where the electroless nickel-palladium-gold plating of the conductor circuit is to be performed is assumed to be X (where X = 0 when X≤0 (zero)), and the circuit pattern It is characterized by making ratio (X / Y) at the time of making the minimum distance between Y into less than 0.8.

Hereinafter, this invention is demonstrated to the example which forms a copper circuit in the outermost layer of a printed wiring board, and performs plating to the terminal area | region.

First, the structure of a printed wiring board is demonstrated.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows typically the cross section of an example of the printed wiring board which belongs to this invention. The printed wiring board 1 has a core board | substrate 2, and has a conductor circuit layer on both surfaces. Four conductor circuit layers 3a, 3b, 3c, and 3d are sequentially stacked on the upper side of the core substrate 2 via the interlayer insulating layers 4a, 4b and 4c, and four conductor circuit layers on the bottom side thereof. (5a, 5b, 5c, 5d) are sequentially laminated through the interlayer insulating layers 4d, 4e, 4f. Conductor circuit layers 3a to 3d and 5a to 5d are formed on a support surface made of a core substrate or an interlayer insulating layer. In addition, the outermost layer circuit 3d is embedded in the groove provided in the interlayer insulating layer 4c, and the conductor circuit layers 3a to c, 5a to d other than the outermost layer circuit 3d are embedded in the support surface. It does not need to be embedded. The upper and lower conductor circuit layers are interlayer connected via via holes. Most of the outermost layer circuit 3d on the upper surface side of the core substrate is covered with the solder resist layer 6, but the terminal region 7 is exposed from the solder resist layer. In the outermost layer circuit 3d of the terminal region 7, a portion protruding from the groove is covered with the nickel-palladium-gold plating layer 8. The outermost layer circuit 5d on the bottom side of the core substrate is covered with the solder resist layer 6 so as to have an opening 6a for connection with a main board or the like. The printed wiring board 1 can be connected to a main board or the like by providing a contact member such as a handball on the pad portion 7c exposed from the opening 6a. The opening portion 6a may have a structure in which a gap is provided between the pad portion 7c and the solder resist 6, or may be a structure in which the periphery of the pad portion 7c is covered with the solder resist 6. 1, the opening part 6a of the structure which provided the clearance gap between the pad part 7c and the soldering resist 6 is shown. Since the opening portion 6a does not include a plurality of connecting terminals as in the terminal region 7, and a short circuit due to abnormal precipitation does not occur, the surface treatment (not shown) of the opening portion 6a is performed by electroless nickel. -Palladium-gold plating may be sufficient, and what is based on other well-known surface treatment method may be sufficient.

In addition, although the printed wiring board 1 has the laminated structure of an interlayer insulation layer on both surfaces of a core board | substrate, the printed wiring board of this invention is not limited to this, The structure which has an interlayer insulation layer only in one side of a core board | substrate may be sufficient, The structure of only a core substrate may be sufficient without having an interlayer insulation layer.

2 is an enlarged plan view of a part of the terminal region 7. In the present invention, the terminal region is an area exposed without being covered with an insulating material such as the solder resist layer 6 in order to connect the circuit layer with an electronic component (element or circuit), and the pad portion 7a serving as an electrical connection point. And a circuit 7b near the pad portion.

FIG. 3: is a figure which shows typically the AA cross section in FIG. 2, ie, the cross section of the groove | channel 9 and the terminal vicinity 7b embedded in the said groove | channel. A groove 9 is provided in the interlayer insulating layer 4c, and a lower portion of the terminal vicinity 7b is embedded in the groove.

The groove 9 has a bottom surface 9a and a side surface 9b, and a groove surface consisting of these bottom surfaces and side surfaces is in contact with the lower portion of the terminal vicinity 7b. The upper part of the terminal vicinity 7b protrudes from the groove and is covered with the nickel-palladium-gold plating layer 8. Although not shown in detail, a nickel-palladium-gold plating layer is a composite plating layer laminated | stacked in the order of a nickel film, a palladium film, and a gold film from the plating process surface side.

In addition, although the cross section of the circuit shown in FIG. 3 is rectangular, the shape of the cross section of the circuit which the printed wiring board of this invention has is not specifically limited, It is preferable that it is rectangular or square, For example, a trapezoid etc. may be sufficient.

In the present invention, "embedded" means a state in which a groove on the support surface is filled with a material forming a metal fine pattern. The state in which the metal fine patterns such as the conductor circuits are embedded in the grooves is the overlapping pattern of the metal fine patterns and the grooves and overlaps each other, and at least the lower part of the metal fine patterns is depressed in the support surface.

In the present invention, the height (thickness) of the metal fine pattern may be larger than the depth of the groove, the same as the depth of the groove, or smaller than the depth of the groove. Here, the height (thickness) of the metal fine pattern is the height from the bottom surface of the groove to the top of the metal fine pattern, and is not a "protrusion height" from the support surface.

The case where the height of the metal fine pattern is larger than the depth of the groove is the state shown in FIG. 3. That is, the material forming the metal fine pattern (in this example, the vicinity of the terminal 7b) completely fills the groove 9 of the support surface (in this example, the interlayer insulating layer 4c), so that the metal fine pattern is removed from the support surface. It means more protruding state.

Moreover, the case where the height of a metal fine pattern is equal to the depth of a groove | channel is a state shown to FIG. 4 (A). That is, it means that the material forming the metal fine pattern completely fills the groove 9 of the support surface, and the top surface of the metal fine pattern 7b 'is planar to the support surface 4c'. Only the top surface of the metal fine pattern 7b 'is not in contact with the surface of the groove, and only this top surface is covered with the nickel-palladium-gold plating layer 8.

In addition, the case where the height of a metal fine pattern is smaller than the depth of a groove | channel is a state shown to FIG. 4 (B). That is, it means that the material forming the metal fine pattern 7b 'is filled up to the middle of the depth of the groove of the support surface 4c' so that the metal fine pattern 7b 'is recessed from the support surface. Only the top surface of the metal fine pattern 7b 'is not in contact with the surface of the groove, and only this top surface is covered with the nickel-palladium-gold plating layer 8.

The protruding height of the conductor circuit in the terminal region 7 is limited in order to effectively suppress metal precipitation around the conductor circuit.

That is, in the present invention, as shown in Fig. 5, the protrusion height from the support surface 4c 'of the metal fine pattern 7b' in the region having the nickel-palladium-gold plating layer 8 is X (where X≤ If 0 (zero), X is assumed to be 0), and the dimension is adjusted so that the ratio (X / Y) when the minimum distance between patterns is Y is less than 0.8. Here, the case where the protrusion height X becomes 0 is a case where the height of the metal fine pattern is equal to the depth of the groove (FIG. 4A). In addition, the case where projection height X is regarded as 0 is the case where the height of a metal fine pattern is smaller than the depth of a groove | channel (FIG. 4 (B)). In addition, although the actual protrusion height X in the case where the height of a metal micropattern is smaller than the depth of a groove | channel is not specifically limited, It is preferable that it is -20 micrometer <= X <0, It is preferable that especially -15 <= X <0. Here, in the case where the protrusion height X is a negative value, it means that the metal fine pattern is recessed with respect to the support surface.

The minimum distance Y between patterns is, for example, a distance indicated by a lowercase letter y in the case of the plan view shown in FIG. 2, and a distance represented by an uppercase letter Y in the case of the sectional view shown in FIG. 5, that is, depending on the circuit shape. Minimum distance between circuits. For example, if the circuit shape is trapezoidal, it is the bottom surface, if it is an inverted trapezoid, it is the upper surface, and if it is columnar, it is the distance between circuits from the center of the circuit.

Since the printed wiring board 1 has little abnormal deposition of the resin surface around the terminal area 7, especially the resin surface at positions sandwiched between adjacent circuits, the plating wiring surface is excellent in quality and hardly shorted. Abnormal deposition by nickel-palladium-gold plating is more likely to occur as the conductor circuit becomes finer and the distance between the conductor circuits becomes smaller, and the signal transmission speed also becomes slower as the conductor circuit becomes finer and the cross-sectional area of the circuit becomes smaller. According to the present invention, metal deposition can be effectively prevented in the range where the line and space (L / S) of the region where the electroless nickel-palladium-gold plating of the conductor circuit is to be performed is in the range of 5 to 100 µm / 5 to 100 µm. . In addition, in the present invention, since the conductor circuit is embedded in the resin surface in order to reduce the exposed area of the conductor circuit, it is not necessary to reduce the thickness of the conductor circuit. For this reason, it is not only possible to prevent abnormal deposition of metal, but also to avoid the problem of slow signal transmission speed. Moreover, it is preferable that the line and space (L / S) of the area | region where electroless nickel-palladium-gold plating of a conductor circuit is to be performed is 5-50 micrometers / 5-50 micrometers, and 5-25 micrometers / 5-25 It is more preferable that it is micrometer.

FIG. 6: is a figure which shows typically the cross section of only one surface of the semiconductor device using the said printed wiring board 1. As shown in FIG. The semiconductor device 10 is formed by mounting the semiconductor element 11 on the printed wiring board 1.

The outermost layer circuit 3d on the upper side of the printed wiring board 1 is covered with the solder resist layer 6, but the terminal region is exposed from the solder resist layer, and the portion protruding from the groove of the terminal region is nickel-. It is covered with a palladium-gold plating layer 8.

The semiconductor element 11 is fixed on the soldering resist layer 6 of the printed wiring board 1 via the die bond material hardening layer 13, such as an epoxy resin. The semiconductor element 11 has the electrode pad 12 on the upper surface, and the connection terminal of this electrode pad 12 and the outermost layer circuit of the printed wiring board 1 is connected by the gold wire 14.

The semiconductor element mounting side of the semiconductor device 10 is sealed by the sealing material 15, such as an epoxy resin.

Although FIG. 6 shows the example which connected the semiconductor element by wire bonding, this invention is applied also when gold-plating the terminal part of another connection system, such as an area array type package.

Next, the method of manufacturing the printed wiring board 1 of FIG. 1 is demonstrated. First, a process wiring board for electroless nickel-palladium-gold plating is prepared.

In the case of the printed wiring board 1, the laminated body which has a structure which lacks the nickel-palladium- gold plating layer 8 from the printed wiring board 1 shown in FIG. 1 is prepared as a processing wiring board.

Here, the "processing wiring board" in the case of manufacturing a printed wiring board is an intermediate product which becomes an object of electroless nickel-palladium-gold plating, and coats the conductor circuit layer laminated | stacked on the surface of a core board | substrate or a core board | substrate. A groove is formed in the surface of the interlayer insulating layer to bury at least a lower portion of the conductor circuit, and at least a portion of the portion not in contact with the surface of the groove of the conductor circuit can be subjected to nickel-palladium-gold plating. It has a structure exposed from the plating treatment environment.

In addition, the "substrate for processing" in the case of manufacturing a base material with a metal micropattern other than a printed wiring board is a base material which has a support surface which consists of resin, and has a structure which embedded at least the lower part of a conductor circuit in the groove provided in the support surface. . The base may be made of a material other than resin as long as the surface is made of resin and the metal fine pattern can be embedded.

As a method of forming a structure in which the conductor circuit layer is embedded in a support surface made of resin such as an interlayer insulating layer, for example, a groove having the same pattern as the conductor circuit is formed on the support surface made of resin by laser processing, After forming a conductor layer in the support surface in which the groove | channel was formed, there exists a method (laser trench processing method) which removes the conductor layer of regions other than a groove | channel.

As another method, a substrate having a support surface made of a conductor circuit transfer sheet and a resin provided with a conductor circuit having a predetermined pattern shape on a carrier film is prepared, and the transfer sheet is laminated in a state in which the support surface of the substrate is softened by heat. There exists a method (transcription method) which removes a film by methods, such as peeling and melt | dissolution, and transfers a conductor circuit.

In one form of the transfer method, a circuit is formed on the nickel foil by a photolithography process using a photosensitive dry film resist, and the surface on which the circuit of the nickel foil is formed is softened by heating. After laminating | stacking and press-molding so that it may contact the support surface of the, there exists a method of etching-removing nickel foil.

7A and 7B are diagrams illustrating a procedure by laser processing. 7A and 7B are schematic diagrams showing only one surface of a printed wiring board. Hereinafter, the procedure for manufacturing the processing wiring board by laser processing will be described in detail.

First, in the procedure (a), three conductor circuit layers 3a, 3b, and 3c are laminated on the upper surface side of the core substrate 2 via the interlayer insulating layers 4a and 4b, and the conductor circuit is disposed on the lower surface side. The laminated body which formed the layer 5, and connected each conductor circuit layer between layers was prepared.

The core substrate can use a well-known thing, such as a glass epoxy substrate. Buildup of the conductor circuit layer onto the core substrate can also be carried out by a known method such as a semiadditive process (SAP) using a known material.

Moreover, the resin sheet which laminated | stacked the insulating layer 4c "on the carrier film 16 is prepared. The well-known thing which can transfer an interlayer insulation layer can also be used for a resin sheet.

It is preferable that the resin composition which comprises the insulating layer 4c "is comprised with the resin composition containing a thermosetting resin. Thereby, the heat resistance of a resin layer can be improved.

Moreover, the said insulating layer 4c "may contain base materials, such as a glass fiber base material.

Examples of thermosetting resins include oils modified with novolak-type phenol resins such as phenol novolak resins, cresol novolak resins, and bisphenol A novolak resins, unmodified resol phenol resins, copper oil, amani oil, and walnut oil. (Iii) Phenolic resins such as resol type phenol resins such as modified resol phenol resins, bisphenol A epoxy resins, bisphenol F epoxy resins, bisphenol E type epoxy resins, bisphenol S type epoxy resins, bisphenol Z type epoxy resins and bisphenol P type epoxy resins Bisphenol-type epoxy resins, such as resin and bisphenol M-type epoxy resin, phenol novolak-type epoxy resin, novolak-type epoxy resins, such as a cresol novolak epoxy resin, biphenyl type epoxy resin, biphenyl aralkyl type epoxy resin, and aryl alkylene type Epoxy resin, naphthalene type epoxy resin, anthracene type epoxy resin, phenoxy type epoxy resin, dicyclopentadiene type epoxy resin, nord Epoxy resins, such as a linen type epoxy resin, an adamantane type epoxy resin, and a fluorene type epoxy resin, resin which has triazine rings, such as urea (urea) resin and melamine resin, unsaturated polyester resin, bismaleimide resin, polyimide resin, Polyamideimide resin, polyurethane resin, diallyl phthalate resin, silicone resin, resin having benzoxazine ring, triazine resin, benzocyclobutene resin, cyanate resin, bismaleimide compound and the like.

Among these, 1 or more types of resin chosen from an epoxy resin, a phenol resin, a cyanate resin, a bismaleimide compound, and a benzocyclobutene resin are preferable, and especially a cyanate resin is preferable. Thereby, the thermal expansion coefficient of a resin layer can be made small. Moreover, the electrical characteristics (low dielectric constant, low dielectric tangent) of a resin layer, mechanical strength, etc. are also excellent.

Specific examples of the cyanate resin include bisphenol cyanate resins such as novolac cyanate resin, bisphenol A cyanate resin, bisphenol E cyanate resin, and tetramethyl bisphenol F cyanate resin. Among these, novolak-type cyanate resin is preferable. The novolac cyanate resin can reduce the coefficient of thermal expansion of the resin layer, and is excellent in mechanical strength and electrical properties (low dielectric constant, low dielectric tangent) of the resin layer.

Although the weight average molecular weight of cyanate resin is not specifically limited, The weight average molecular weights 500-4,500 are preferable and especially 600-3,000 are preferable. The mechanical strength of the hardened | cured material of a resin layer may fall that a weight average molecular weight is less than the said lower limit, and when a resin layer is produced, adhesiveness may arise and transfer of resin may arise. Moreover, when a weight average molecular weight exceeds the said upper limit, hardening reaction may become quick and when a board | substrate (especially a circuit board) is used, a molding defect may arise or an interlayer peeling strength may fall. In addition, the weight average molecular weight of cyanate resin etc. can be measured, for example by GPC (gel permeation chromatography, a standard substance: polystyrene conversion).

Although it does not specifically limit as a bismaleimide compound, For example, 4,4'- diphenylmethane bismaleimide, m-phenylene bismaleimide, p-phenylene bismaleimide, 2,2 '-[4 -(4-maleimide phenoxy) phenyl] propane, bis- (3-ethyl-5-methyl-4-maleimide phenyl) methane, 4-methyl-1,3-phenylene bismaleimide, N, N ' -Ethylene dimaleimide, N, N'-hexamethylene dimaleimide, etc. are mentioned, As polymaleimide, polyphenylmethane maleimide etc. are mentioned. Among them, 2,2'-bis [4- (4-maleimide phenoxy) phenyl] propane and bis- (3-ethyl-5-methyl-4-maleimide phenyl) methane are preferable in consideration of low water absorption and the like. Do.

Although content of a thermosetting resin is not specifically limited, 5-50 weight% of the whole resin composition is preferable, and 10-40 weight% is especially preferable. When content is less than a lower limit, it may become difficult to form a resin layer, and when it exceeds an upper limit, the strength of a resin layer may fall.

When using cyanate resin (especially novolak-type cyanate resin) as a thermosetting resin, it is preferable to use together an epoxy resin (it does not contain a halogen atom substantially).

As an epoxy resin, For example, bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, bisphenol Z type epoxy resin, bisphenol P type epoxy resin, bisphenol M type epoxy resin, etc. Aryl alkylene type epoxy resins such as novolak type epoxy resins such as epoxy resins, phenol novolac epoxy resins, cresol novolak epoxy resins, biphenyl type epoxy resins, xylylene type epoxy resins, and biphenyl aralkyl type epoxy resins; Naphthalene type epoxy resin, anthracene type epoxy resin, phenoxy type epoxy resin, dicyclopentadiene type epoxy resin, norbornene type epoxy resin, adamantane type epoxy resin, fluorene type epoxy resin and the like.

One type of these may be used alone as the epoxy resin, two or more types having different weight average molecular weights may be used in combination, or one or two or more types thereof and their prepolymers may be used in combination.

Although content of an epoxy resin is not specifically limited, 1-55 weight% of the whole resin composition is preferable, and 5-40 weight% is especially preferable. When content is less than the said lower limit, the reactivity of a cyanate resin may fall, or the moisture resistance of the obtained product may fall, and when it exceeds the said upper limit, low thermal expansion resistance and heat resistance may fall.

Although the weight average molecular weight of an epoxy resin is not specifically limited, The weight average molecular weights 500-20,000 are preferable and 800-15,000 are especially preferable. If a weight average molecular weight is less than the said lower limit, adhesiveness may arise on the surface of a resin layer, and when it exceeds the said upper limit, soldering heat resistance may fall. By carrying out a weight average molecular weight in the said range, it can be set as the outstanding balance of these characteristics. The weight average molecular weight of an epoxy resin can be measured, for example by GPC (gel permeation chromatography, a standard substance: polystyrene conversion).

The resin composition which comprises the resin layer of the printed wiring board of this invention can be made to contain an inorganic filler. As an average particle diameter of the inorganic filler which can be contained in the resin composition which comprises a resin layer, it is preferable that they are 0.05 micrometer or more and 0.5 micrometer or less. As a result, fine wiring can be formed with high insulation reliability and excellent signal response.

The measurement of the average particle diameter of an inorganic filler can be measured by a laser diffraction scattering method, for example. The inorganic filler was dispersed by ultrasonic waves in water, and the particle size distribution of the inorganic filler was prepared by volume using a laser diffraction particle size distribution measuring apparatus (manufactured by HORIBA, LA-500), and the intermediate diameter (D50) was converted into an average particle diameter. It can measure by making.

It is preferable that it is 2.0 micrometers or less as the largest particle diameter of the inorganic filler which can be contained in the resin composition which comprises a resin layer. As a result, fine wiring can be formed with high insulation reliability and excellent signal response. Moreover, although it does not specifically limit, 1.8 micrometers or less are more preferable, and, as for the maximum particle diameter of an inorganic filler, 1.5 micrometers or less are especially preferable. Thereby, the effect | action which raises insulation reliability and signal responsiveness can be expressed effectively.

When the average particle diameter of the inorganic filler which can be contained in the resin composition which comprises a resin layer exceeds the said upper limit, or the maximum particle diameter of an inorganic filler exceeds the said upper limit, an inorganic filler inhibits laser processing and forms a groove in a resin layer. A point which cannot be done may occur. Moreover, since the time to form a groove by laser light becomes long, workability may decrease. Moreover, the surface unevenness | corrugation of the conductor layer after plating becomes large by the inorganic filler which remained in the groove side wall surface after laser processing. As a result, the accuracy of the wiring deteriorates and the insulation reliability may be impaired in the high density printed wiring board. Furthermore, in the high frequency region over 1 GHz, the signal responsiveness may be impaired by the surface effect.

When the average particle diameter of the inorganic filler which can be contained in the resin composition which comprises a resin layer becomes less than the said lower limit, the physical property of the thermal expansion coefficient and elastic modulus of a resin composition will fall, and the mounting reliability at the time of semiconductor element mounting will be impaired.

Although it does not specifically limit as an inorganic filler which can be contained in the resin composition which comprises a resin layer, For example, silicate, such as talc, calcined clay, unbaked clay, mica, glass, titanium oxide, alumina, silica, fused silica Oxides, such as calcium carbonate, magnesium carbonate, hydrotalcite, hydroxides such as aluminum hydroxide, magnesium hydroxide, calcium hydroxide, sulfates such as barium sulfate, calcium sulfate, calcium sulfite or sulfite, zinc borate, barium metaborate, boric acid Borate salts, such as aluminum, calcium borate, and sodium borate, nitrides, such as aluminum nitride, boron nitride, silicon nitride, and carbon nitride, titanates, such as strontium titanate and barium titanate, etc. are mentioned. As an inorganic filler, one type of these may be used independently and two or more types may be used together. Among these, silica is preferable and fused silica is more preferable at the point which is excellent in low thermal expansion property, a flame retardance, and an elasticity modulus. Among these, spherical silica is preferable in shape.

The carrier film 16 of the resin sheet has a release property which can transfer the insulating layer 4c "on a conductor circuit layer. Although a carrier film is not specifically limited, A polymer film or a metal foil can be used. For example, a thermoplastic resin film having heat resistance such as polyester resin such as polyethylene terephthalate, polybutylene terephthalate, fluorine resin, polyimide resin, etc. may be used, for example, copper and / or Copper alloys, aluminum and / or aluminum alloys, iron and / or iron alloys, silver and / or silver alloys, gold and gold alloys, zinc and zinc alloys, nickel and nickel alloys, tin and tin alloys, and the like. Metal foil etc. can be used.

Although the thickness of a carrier film is not specifically limited, When the thing of thickness 10-70 micrometers is used, the handleability at the time of manufacturing a resin sheet is favorable, and it is preferable.

Although the thickness of the insulating layer on a carrier film is not specifically limited, 1-60 micrometers is preferable and 5-40 micrometers is especially preferable. In order to improve the insulation reliability, the thickness of the resin layer is preferably equal to or greater than the lower limit, and preferably equal to or less than the upper limit in achieving thinning of the multilayer printed wiring board.

Although the manufacturing method of a resin sheet is not specifically limited, For example, a resin composition is melt | dissolved and disperse | distributed to a solvent etc. to prepare a resin varnish, and after coating a resin varnish on a carrier film using various coater apparatuses, After spray-coating a resin varnish on a carrier film using a spray apparatus, the method of drying this, etc. are mentioned. Among these, after coating a resin varnish on a carrier film using various coater apparatuses, such as a comma coater and a die coater, the method of drying this is preferable. Thereby, there is no void and the resin sheet which has the thickness of a uniform resin layer can be manufactured efficiently.

Moreover, the surface of the carrier film of the resin sheet may be roughened, or may be unharmonized. As a method of roughening the surface of the carrier film of a resin sheet, the method of chemically roughening with an etching chemical liquid, the method of physically roughening using a grinder, etc. are mentioned, for example.

Next, in the step (b), the insulating film side of the resin sheet is placed on the upper surface side of the laminate prepared in the step (a) so as to face each other, and the carrier film is peeled off in the step (c) to interlayer insulating layer 4c. ).

The surface 4c 'of the side which peeled the carrier film of the interlayer insulation layer 4c may be roughened. As a method of the said roughening process, (a) The surface 4c of the interlayer insulation layer 4c peeled off by peeling the said carrier film using the carrier film in which the contact surface with the interlayer insulation layer 4c is harmonized, for example. '), (B) Plasma treatment of surface 4c' of interlayer insulating layer 4c from which said harmonized carrier film is peeled off using a carrier film in which contact surfaces with interlayer insulating layer 4c are harmonized. And / or a method for roughening by desmearing, and (c) plasma treatment and / or desmearing the surface 4c 'of the interlayer insulating layer 4c from which the above-mentioned uncarried carrier film is peeled off using the above-mentioned uncarried carrier film. The method of harmonizing by processing is mentioned.

In addition, you may peel after a laser processing in the procedure (d) mentioned later, without peeling a carrier film in procedure (c).

Next, in step (d), the laser light 17 is irradiated to form the groove 9 on the surface of the interlayer insulating layer 4c. In laser processing, in the region where nickel-palladium-gold plating of the conductor circuit finally formed along the groove is to be performed, the ratio of the height X of the circuit from the support surface to the minimum distance Y between the circuit patterns (X / Y ), The dimensions and shape of the grooves are adjusted to be less than 0.8.

Moreover, although the groove 9 is not specifically limited, It is preferable to form so that the depth of the said groove 9 may be 50% or less of the thickness of the interlayer insulation layer 4c.

The laser light is preferably an excimer laser or a YAG laser. By using these lasers, fine wiring can be formed with good accuracy and shape. Although it does not specifically limit, It is more preferable that the laser wavelength of an excimer laser is 193 nm, 308 nm, and 248 nm, and it is especially preferable that it is 193 nm, 248 nm. Thereby, the effect | action which can form a fine line and a fine fine wiring can be expressed effectively. It is preferable that the wavelength of a YAG laser is 355 nm. At other wavelengths, the resin composition constituting the interlayer insulating layer may not absorb laser light and thus may not be able to form fine wiring.

Next, in the step (e), via holes 18 are formed in the interlayer insulating layer 4c to secure the path for the interlayer connection, and then the electroless plating layer is formed on the surface of the interlayer insulating layer 4c by electroless plating. 19). Although the kind of metal of the electroless plating layer 19 is not specifically limited, Copper, nickel, etc. are preferable.

In addition, after the grooves 9 and the via holes 18 are formed, a desmear step may be appropriately added to improve the adhesion.

Next, if necessary, the procedure (f) is performed to form the electrolytic plating layer 20. Copper sulfate electroplating can be used for electroplating.

Next, in the step (g), the outermost layer circuit 3d is formed only in the groove 9 by removing the electroless plating layer 19 and the electrolytic plating layer 20 in regions other than the grooves. Although not particularly limited, the method of removing the electroless plating layer 19 and the electrolytic plating layer 20 is preferably a chemical etching treatment, a polishing treatment, a buff polishing treatment, or the like. Thereby, it is possible to effectively remove only the electroless plating layer 19 and the electrolytic plating layer 20 on the resin surface, leaving the conductor circuit only in the groove 9 portion.

Then, in the step (h), the solder resist layer 6 is formed on the outermost layer circuit 3d, and the process is performed by exposing only the portion of the terminal region 7 (not shown) from the solder resist layer 6 at that time. The wiring board for this is obtained.

In the processing wiring board obtained through the above steps (a) to (h), since only the terminal region 7 of the outermost layer circuit is exposed from the solder resist layer, electroless nickel-palladium-gold plating is applied to the terminal region of the outermost layer circuit. May be optionally performed.

In the present invention, when electroless nickel-palladium-gold plating is to be performed only on a part of a conductor circuit or a metal fine pattern, other plating masks such as soluble resists and molded product masks, in addition to permanent resists such as solder resist layers You can also use

8 is a block diagram showing the sequence of electroless nickel-palladium-gold plating. Below, the order of the said electroless nickel-palladium-gold plating is demonstrated in detail.

When plating to the outermost layer copper circuit of a printed wiring board by this invention, surface treatment can be given to the said terminal part by one or two or more methods as needed as a preprocessing before a palladium catalyst provision process. Although FIG. 8 showed the cleaner S1a, the soft etching S1b, the acid treatment S1c, and the pre-dip S1d as FIG. 8, you may perform another process.

After the pretreatment, a nickel-palladium-gold (Ni-Pd-Au) film is formed by sequentially applying a palladium catalyst, electroless nickel plating, electroless palladium plating, and electroless gold plating.

In the electroless nickel-palladium-gold plating method of the present invention, pretreatment (S1), palladium catalysis giving step (S2), electroless nickel plating treatment (S3), electroless palladium plating treatment (S4), electroless gold plating The processing S5 may be performed in the same manner as in the prior art.

Hereinafter, each process step of S1-S5 is demonstrated one by one.

<Pretreatment (S1)>

(1) cleaner treatment (S1a)

The cleaner treatment (S1a), which is one of the pretreatments, is performed in order to remove the organic film from the terminal surface, to activate the metal on the terminal surface, and to improve the wettability of the terminal surface by bringing the acidic or alkaline type cleaner liquid into contact with the terminal surface. .

Acid-type cleaners mainly etch extremely thin portions of the terminal surface to activate the surface, and effective for copper terminals include liquids containing oxycarboxylic acid, ammonia, salt, and surfactants (e.g., Kamimura Industries, Ltd.). ACL-007) is used. Other acid type cleaners effective for the copper terminal may be a solution containing sulfuric acid, a surfactant, and sodium chloride (for example, Kamimura Industries Co., Ltd. ACL-738), which is highly wettable.

The alkaline type cleaner mainly removes the organic coating, and the liquid containing a nonionic surfactant, 2-ethanolamine, and diethylenetriamine is effective for the copper terminal (for example, ACL of Kamimura Industries Co., Ltd.). -009) is used.

In order to perform a cleaner process, after contacting any one of said cleaner liquids by the method of immersion, spray, etc., a terminal part may be washed with water.

(2) soft etching treatment (S1b)

Another pre-processing soft etching process (S1b) is performed to etch an extremely thin portion of the terminal surface to remove the oxide film. As an effective soft etching solution for the copper terminal, an acid solution containing sodium persulfate and sulfuric acid is used.

In order to perform a soft etching process, after contacting the said soft etching liquid by the method of immersion, spray, etc., what is necessary is just to wash with water.

(3) Pickling treatment (S1c)

Another pretreatment, pickling treatment (S1c) is performed in order to remove the fine particles (copper fine particles) from the resin surface of the terminal surface or its vicinity.

Sulfuric acid is used as an effective pickling solution for copper terminals.

To perform the pickling treatment, the pickling liquid may be brought into contact with the terminal by immersion, spraying, or the like, followed by washing with water.

(4) pre-dip processing (S1d)

Another pre-treatment, pre-dip treatment (S1d) is a process of dipping in sulfuric acid at almost the same concentration as the catalyst imparting solution prior to the palladium catalyzing step, and improving the hydrophilicity of the terminal surface to improve adhesion to Pd ions contained in the catalyst imparting solution. In order to avoid the inflow of water to the catalyst imparting liquid, to enable the repeated reuse of the catalyst imparting liquid, or to remove the oxide film. Sulfuric acid is used as the pre-dip liquid.

In order to perform a pre-dip process, the terminal part is immersed in the said pre-dip liquid. In addition, water washing is not performed after a pre-dip process.

<Palladium catalyst provision process (S2)>

Pd ^{2 +} ions acid solution (catalyst giving liquid) containing in contact with the terminal surface is replaced with Pd ^{2 +} ion in the terminal surface by ionization tendency (Cu + Pd ^{2 +} → Cu ^{2 + +} Pd) of metal Pd. Pd attached to the terminal surface acts as a catalyst for electroless plating. Pd ^{2 +} ion as a supply source of palladium salt can be used sulfuric acid, palladium or palladium chloride.

Palladium sulfate is suitable for thin line formation because the adsorption power is weaker than that of palladium chloride, and Pd is easily removed. Palladium sulfate catalyst-imparting solutions effective for copper terminals include strong acid solutions containing sulfuric acid, palladium salts and copper salts (for example, KAT-450 from Kamimura Industries, Ltd.), oxycarboxylic acids, sulfuric acid and palladium salts. Strong acid solution (for example, MNK-4 of Kamimura Industries Co., Ltd.) is used.

On the other hand, since palladium chloride has a strong adsorption force and a substitution property, and Pd is hardly removed, an effect of preventing plating non-adherent is obtained when electroless plating is performed under conditions where plating unfixed easily occurs.

What is necessary is just to contact the said catalyst provision liquid with the method of immersion, spray, etc. to a terminal part, and to wash the water, in order to implement a palladium catalyst provision process.

<Electroless nickel plating treatment (S3)>

As an electroless nickel plating bath, the plating bath containing a water-soluble nickel salt, a reducing agent, and a complexing agent can be used, for example. Details of the electroless nickel plating bath are described, for example, in Japanese Patent Application Laid-Open No. 8-269726.

As a water-soluble nickel salt, it uses nickel sulfate, nickel chloride, etc., and makes the density | concentration about 0.01-1 mol / liter.

As a reducing agent, the density | concentration is made into about 0.01-1 mol / liter using hypophosphite, such as hypophosphorous acid and sodium hypophosphite, dimethylamine borane, trimethylamine borane, and hydrazine.

As a complexing agent, the density | concentration is made into about 0.01-2 mol / liter using amino acids, such as carboxylic acids, such as malic acid, succinic acid, lactic acid, a citric acid, its sodium salt, glycine, alanine, imino diacetic acid, arginine, glutamic acid.

This plating bath is adjusted to pH 4-7 and used at a bath temperature of 40-90 degreeC. When hypophosphorous acid is used as the reducing agent in this plating bath, the following main reaction proceeds by the Pd catalyst on the surface of the copper terminal to form a Ni plating film.

_{^{Ni 2 + + H 2 PO 2}} - + H 2 O + 2e - → Ni + H 2 PO 3 - + H 2

<Electroless palladium plating treatment (S4)>

As an electroless palladium plating bath, the plating bath containing a palladium compound, a complexing agent, a reducing agent, and an unsaturated carboxylic acid compound can be used, for example.

The palladium compound is, for example, palladium chloride, palladium sulfate, palladium acetate, palladium nitrate, tetraamine palladium hydrochloride, or the like, and the concentration thereof is about 0.001 to 0.5 mol / liter based on palladium.

As a complexing agent, the density | concentration shall be about 0.001-10 mol / liter using amine compounds, such as ammonia or methylamine, dimethylamine, methylenediamine, and EDTA.

The concentration of the reducing agent is about 0.001 to 5 mol / liter using hypophosphite, hypophosphite such as sodium hypophosphite and ammonium hypophosphite.

As the unsaturated carboxylic acid compound, the concentration of the unsaturated carboxylic acid such as acrylic acid, methacrylic acid and maleic acid, salts such as anhydrides thereof, sodium salts and ammonium salts thereof, derivatives such as ethyl esters and phenyl esters, etc. may be used. It should be about 10 mol / liter.

This plating bath is adjusted to pH 4-10 and used at a bath temperature of 40-90 degreeC. When hypophosphorous acid is used as the reducing agent in this plating bath, the next main reaction proceeds on the copper terminal surface (actually the nickel surface) to form a Pd plating film.

_{^{Pd 2 + + H 2 PO 2}} - + H 2 O → Pd + H 2 PO 3 - + 2H +

<Electroless gold plating treatment (S5)>

As the electroless gold plating bath, for example, a plating bath containing a water-soluble gold compound, a complexing agent and an aldehyde compound can be used. Details of the electroless gold plating bath are described, for example, in Japanese Patent Laid-Open No. 2008-144188.

As a water-soluble gold compound, the concentration is made into 0.0001-1 mol / liter on a gold basis using gold cyanide salts, such as gold cyanide, gold potassium cyanide, sodium gold cyanide, and gold ammonium cyanide, for example.

As the complexing agent, for example, phosphoric acid, boric acid, citric acid, gluconic acid, tartaric acid, lactic acid, malic acid, ethylene diamine, triethanol amine, ethylene diamine tetraacetic acid and the like are used at a concentration of about 0.001 to 1 mol / liter.

As the aldehyde compound (reducing agent), for example, aliphatic saturated aldehydes such as formaldehyde and acetaldehyde, aliphatic dialdehydes such as glyoxal and succinic aldehyde, aliphatic unsaturated aldehydes such as croton aldehyde, benzaldehyde, o-, m- or p The concentration is set to 0.0001 to 0.5 mol / liter using a sugar having an aldehyde group (-CHO) such as aromatic aldehyde such as nitro benzaldehyde, glucose, galactose or the like.

Adjust this plating bath to pH 5-10 and use it at bath temperature about 40-90 degreeC. When using this plating bath, the following two substitution reactions advance on a copper terminal surface (actually a palladium surface), and an Au plating film is formed.

^{Pd + Au + → Pd 2 +} + Au + e -

e ^- (also obtained by oxidation of components in the plating bath by the action of auto-Au catalyst) + Au → Au ⁺

In the electroless nickel-palladium-gold plating, a step of removing the Pd catalyst attached to the surface of the resin at any stage after the palladium catalyst applying step (S2) and before the electroless palladium plating treatment (S4) (post Dip step). A post-dip step may have for example, a method how to make the inert as Pd ^{2 +} ion and reacting the KCN to form a complex ion catalyst or using KCN, using an acid solution to eliminate wash Pd ^{2 +} ion.

The Ni-Pd-Au plating film of high quality is formed in the circuit of a printed wiring board through the said procedure, and the high quality plating process surface without abnormal precipitation is ensured on the resin surface around a terminal.

A semiconductor device with high connection reliability can be manufactured by mounting a semiconductor element on the printed wiring board of this invention manufactured by the said method.

Example

Although an Example is shown to the following and this invention is demonstrated to it in more detail, it is not limited to this.

< Example  1 ＞

(Creation of a test piece)

20 parts by weight of novolac-type cyanate resin (manufactured by Lonja Japan Co., Ltd., Primasset PT-30, weight average molecular weight approximately 700), methoxynaphthalene dimethylene type epoxy resin (manufactured by Japan Nippon Ink Chemical Co., Ltd., EXA-7320) 35 5 parts by weight, phenoxy resin (manufactured by Japan Epoxy Resin Co., jER4275), 0.2 parts by weight of imidazole compound (manufactured by Shikoku Kasei Kogyo Co., Ltd., quazole 1B2PZ (1-benzyl-2-phenyl imidazole)) to methyl ethyl ketone Dissolved and dispersed. In addition, a spherical fused silica (manufactured by Denki Chemical Industries, Ltd., SFP-20M) was filtered using a multilayer cartridge filter (manufactured by Sumitomo 3M Corporation) to filter particles having a maximum particle diameter of 2.0 μm, and average weight was 0.4 μm. Part added. Furthermore, 0.2 weight part of epoxy silane coupling agents (GE Toshiba Silicone Co., Ltd. make, A-187) were added, and it stirred for 10 minutes using the high speed stirring apparatus, and prepared the resin varnish of 50 weight% of solid content.

The resin varnish obtained above is coated on one side of a 25-micrometer-thick PET (polyethylene terephthalate) carrier film using a comma coater so that the thickness of the resin film after drying may be 40 micrometers, and this is carried out in a drying apparatus at 160 ° C for 10 minutes. It dried and produced the resin sheet.

This resin sheet was superimposed on the front and back of the inner layer circuit board, and was vacuum heated and press-molded at a temperature of 100 ° C. and a pressure of 1 MPa using a vacuum pressurized laminator device, followed by heat curing at 180 ° C. for 45 minutes in a hot air drying device. The substrate with a stratified layer was obtained.

In addition, the following were used as an inner circuit board.

Insulation layer: Halogen-free FR-5 material, thickness 0.4mm

Conductor layer: Copper foil thickness 18 micrometers, L / S = 120/180 micrometers, clearance hole 1 mm (phi), 3 mm (phi), slit 2 mm

After peeling a carrier film (PET), the groove | channel of line and space (L / S) = 40/40 and target depth 15micrometer was formed in the resin layer of the board | substrate with a resin layer with the excimer laser which has a wavelength of 193 nm. .

The obtained laminated body was immersed in 60 degreeC swelling liquid (Art-Tech Japan Co., Ltd., Swelling Deep Securitant P500) for 10 minutes, and also in 80 degreeC aqueous potassium permanganate solution (Art-Tech Japan Co., Ltd., condensate compact CP). After immersion for 20 minutes, it neutralized and desmeared.

After this step of degreasing, catalyzing, and activating, an electroless copper plating layer of about 0.2 mu m was formed.

Next, electroless copper plating layer as an electrode by the electrolytic copper plating to embodiment (Okuno Chemical Industries Co., Ltd., top Rutina α) 3A / dm ^2, 60 minutes to form a conductor layer thickness of about 20㎛ from the resin surface layer.

A dry film resist (AR320 manufactured by Tokyo Takagyo Co., Ltd.) was roll-laminated on the surface of the conductor layer, and exposed and developed using a predetermined negative film to form a plating resist required for the conductor circuit. After removing the exposed part of a pattern by flash etching process (SAC process of Ebara Co., Ltd.), the dry film was peeled off (peeling liquid: R-100 by Mitsubishi Gas Chemical, peeling time: 240 second).

Subsequently, the insulating resin layer was completely cured at a temperature of 200 ° C. for 60 minutes, and then subjected to circuit roughening treatment (harmonic treatment solution: Mack Co., Ltd. CZ8101, 1 μm roughening condition), and line and space (L / S) = 40 μm. The test piece which has the copper circuit of 40 micrometers, protrusion height (X) = 20 micrometers, and X / Y = 0.50 was created.

Electroless Nickel-Palladium-Gold Plating Process (ENEPIG Process)

The ENEPIG process was performed to the said test piece in the following procedure, and the four-layer printed wiring board of Example 1 was obtained.

(1) cleaner treatment

After the said test piece was immersed in the cleaner liquid of 50 degreeC of liquid temperature for 5 minutes using ACL-007 by Kamimura Industries Co., Ltd. as a cleaner liquid, it washed with water three times.

(2) soft etching treatment

After the cleaner treatment, the test piece was immersed in a soft etching solution having a liquid temperature of 25 ° C. for 1 minute using a mixture of soda persulfate and sulfuric acid as the soft etching solution, and then washed three times.

(3) pickling treatment

After the soft etching treatment, the test piece was immersed in sulfuric acid at a liquid temperature of 25 ° C. for 1 minute, and then washed three times with water.

(4) pre-dip processing

After the pickling treatment, the test piece was immersed in sulfuric acid at a liquid temperature of 25 ° C. for 1 minute.

(5) Palladium catalyst provision process

In order to provide a palladium catalyst to a wiring part after a pre-dip process, Kami-mura KK-450 was used as a palladium catalyst provision liquid. The test piece was immersed in the palladium catalyst imparting liquid at a liquid temperature of 25 ° C. for 2 minutes, and then washed three times with water.

(6) Electroless Ni Plating

After the palladium catalyst applying step, the test piece was immersed in an electroless Ni plating bath (NPR-4, manufactured by Kamimura Industries Co., Ltd.) at a liquid temperature of 80 ° C. for 35 minutes, and washed with water three times.

(7) Electroless Pd Plating

After the electroless Ni plating treatment, the test piece was immersed in an electroless Pd plating bath (TPD-30 manufactured by Kamimura Industries Co., Ltd.) at a liquid temperature of 50 ° C. for 15 minutes, and then washed with water three times.

(8) Electroless Au Plating

After the electroless Pd plating treatment, the test piece was immersed in an electroless Au plating bath (TWX-40, manufactured by Kamimura Industries Co., Ltd.) at a liquid temperature of 80 ° C. for 18 minutes, and washed with water three times.

< Example  2 ＞

A 4-layer printed wiring board was produced in the same manner as in Example 1 except that the line-and-space (L / S) was set to 20 µm / 20 µm and the projected height X was 15 µm, and X / Y was set to 0.75.

< Example  3 ＞

Line and space (L / S) = 25 micrometers / 25 micrometers, after electrolytic copper plating, it etches down 20 micrometers of electrolytic copper, and makes it the protrusion height (X) = 0 micrometer, except having made X / Y = 0. In the same manner as in 1, a four-layer printed wiring board was produced.

< Example  4>

Line and space (L / S) = 25 µm / 25 µm, after electrolytic copper plating, the projection height X <0 µm (actually X = -5 µm) by etching down 25 µm of electrolytic copper, X / A 4-layer printed wiring board was produced in the same manner as in Example 1 except that Y was set to 0.

< Comparative example  1 ＞

A 4-layer printed wiring board was produced in the same manner as in Example 1 except that the line-and-space (L / S) was 25 µm / 25 µm and the protrusion height X was 20 µm, and X / Y was 0.80.

< Comparative example  2 ＞

The 4-layer printed wiring board was produced like Example 1 except having set line and space (L / S) = 25 micrometers / 25 micrometers, protrusion height (X) = 25 micrometers, and setting it to X / Y = 1.00.

The following evaluation was performed about the printed wiring board obtained by each Example and the comparative example. An evaluation item is shown with the content and the obtained result is shown in Table 1.

<Having abnormal precipitation>

The presence or absence of abnormal precipitation was evaluated by observing the terminal portion of the printed wiring board with an electron microscope (reflected electron image).

○: No abnormal precipitation

(Triangle | delta): There exist some abnormal precipitation at the time of a circuit

X: Abnormal precipitation in the front of the space

<Insulation test>

The presence or absence of the wiring short of the printed wiring board obtained by the Example and the comparative example was verified using the conduction tester (HIOKI: X = YC Hightester 1116).

○: No conduction

×: With conduction

The printed wiring boards obtained in Examples 1 to 4 had little or no abnormal deposition between the wirings, and the insulation between the wirings could be maintained even after the ENEPIG process. On the other hand, in the printed wiring boards obtained in Comparative Examples 1 and 2, abnormal deposition was confirmed, and shorts between wirings were confirmed. Therefore, the printed wiring board of the present invention is characterized by the fact that the ratio (X / Y) of the projected height X from the support surface of the conductor circuit to the minimum distance Y between the circuit patterns is less than 0.8 by embedding the conductor circuit in the resin surface. It can be seen that abnormal deposition of metals in the metal structure is prevented and effective for insulation between wirings.

< Comparative example  3 ＞

A conductive circuit in which the line and space of the region where the electroless nickel-palladium-gold plating of the conductor circuit is to be performed is 40 mu m / 40 mu m as in Example 1, and the conductor circuit is not embedded in the resin surface but only on the resin surface. Compared with the conductive circuit of Example 1, the electrically conductive circuit produced by the conventional method of making the thickness of 20 micrometers has only a cross-sectional area of about 60%, and the electrical resistance increased approximately twice.

According to the present invention, it is possible not only to prevent abnormal deposition of metal, but also to avoid the problem of slow signal transmission speed.

1 printed wiring board
2 core board
3 (3a, 3b, 3c, 3d) top side conductor circuit layer
4 (4a, 4b, 4c, 4d, 4e, 4f) interlayer insulation layer
4c 'support surface
4c "insulation layer
5 (5a, 5b, 5c, 5d) bottom side conductor circuit layer
6 solder resist layer
6a opening
7 terminal area
7a pad
7b Circuit near pad part
7b 'metal fine pattern
7c pad
8 Nickel-Palladium-Gold Plating Layer
9 home
10 semiconductor devices
11 semiconductor devices
12 electrode pads
13 die bond material hardened layer
14 gold wire
15 bags
16 carrier film
17 laser light
18 Via Hole
19 Electroless Plating Layer
20 Electrolytic Plating Layer

Claims (15)

As a base material with a metal fine pattern,
At least the lower part of the metal fine pattern is embedded in the groove provided in the support surface which consists of resin,
A portion of the metal micropattern not in contact with the surface of the groove in at least a portion of the metal fine pattern is covered with a nickel-palladium-gold plating layer,
The protruding height from the support surface of the metal fine pattern in the region having the nickel-palladium-gold plating layer is set to X (where X = 0 (zero) is regarded as X = 0), and the minimum distance between patterns The ratio (X / Y) at the time of making Y into Y is less than 0.8, The base material with a metal fine pattern characterized by the above-mentioned. The method according to claim 1,
The base material with a metal fine pattern whose line and space (L / S) of the area | region which has the nickel-palladium- gold plating layer of the said metal fine pattern is 5-100 micrometers / 5-100 micrometers. As a printed wiring board,
At least a lower portion of the conductor circuit is embedded in a groove provided in a support surface made of a core substrate or an insulating layer,
A portion of the at least part of the conductor circuit which is not in contact with the surface of the groove is covered with a nickel-palladium-gold plating layer,
The protruding height from the support surface of the conductor circuit in the region having the nickel-palladium-gold plated layer is X (where X = 0 (zero) is assumed to be X = 0), and the minimum distance between circuit patterns The ratio (X / Y) at which Y is Y is less than 0.8. The printed wiring board characterized by the above-mentioned. The method according to claim 3,
The printed wiring board in which the line and space (L / S) of the area | region which has the nickel- palladium- gold plating layer of the said conductor circuit is 5-100 micrometers / 5-100 micrometers. The method according to claim 3 or 4,
The printed wiring board in which the area | region which has the nickel- palladium- gold plating layer of the said conductor circuit is an area | region which forms a terminal. A semiconductor device is mounted on a printed wiring board according to claim 5, and a terminal of the printed wiring board and an entry / exit part of the semiconductor element are connected. As a manufacturing method of a base material with a metal fine pattern,
Preparing a substrate for processing in which at least a lower portion of the metal fine pattern is embedded in a groove provided on a support surface made of resin;
Performing electroless nickel-palladium-gold plating on a portion not in contact with the surface of the groove in at least a part of the metal fine pattern of the substrate for processing;
The protrusion height from the support surface in the region where the fine metal pattern is subjected to electroless nickel-palladium-gold plating is X (except X = 0, where X = 0), and the pattern The manufacturing method of the base material with a metal micropattern characterized by making ratio (X / Y) at the time of making the minimum distance between Y into less than 0.8. The method according to claim 7,
The manufacturing method of the base material with a metal micropattern so that the line and space (L / S) of the area | region which electroless nickel-palladium-gold plating of the said metal micropattern is set to 5-100 micrometers / 5-100 micrometers. The method according to claim 7 or 8,
In the step of preparing the substrate for treatment, a method for producing a substrate with a metal micropattern, wherein a groove is formed on a support surface of the substrate for processing by laser, and a metal fine pattern is formed by depositing a metal in the groove. The method according to claim 7 or 8,
The manufacturing method of the base material with a metal fine pattern in the process of preparing the said base material for processing WHEREIN: The metal fine pattern of a metal fine pattern transfer sheet is transferred to the support surface which heat-softened the base material for processing. As a manufacturing method of a printed wiring board,
Preparing a processing wiring board in which at least a lower portion of the conductor circuit is embedded in a groove provided in a support surface made of a core substrate or an insulating layer;
And performing electroless nickel-palladium-gold plating on a portion of the processing circuit board not in contact with the surface of the groove in at least a part of the conductor circuit.
The projected height from the support surface in the region where the electroless nickel-palladium-gold plating of the conductor circuit is to be performed is assumed to be X (where X = 0 when X≤0 (zero)), and the circuit pattern The manufacturing method of the printed wiring board which makes ratio (X / Y) at the time of making the minimum distance between them Y be less than 0.8. The method of claim 11,
The manufacturing method of the printed wiring board which makes line and space (L / S) of the area | region which electroless nickel-palladium-gold plating of the said conductor circuit become 5-100 micrometers / 5-100 micrometers. The method of claim 11,
The manufacturing method of the printed wiring board in which the area | region which performs nickel-palladium-gold plating of the said conductor circuit is a area | region which forms a terminal. The method according to any one of claims 11 to 13,
In the step of preparing the processing wiring board, a groove is formed on the support surface of the processing wiring board by a laser, and a conductor circuit is formed by depositing a metal in the groove. The method according to any one of claims 11 to 13,
The manufacturing method of the printed wiring board which transfers the conductor circuit of a conductor circuit transfer sheet to the support surface which heat-softened the process wiring board in the process of preparing the said process wiring board.

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