CN102316668A - Substrate with fine metal pattern, print circuit board and semiconductor device, and production method of substrate with fine metal pattern, print circuit board and semiconductor device - Google Patents
Substrate with fine metal pattern, print circuit board and semiconductor device, and production method of substrate with fine metal pattern, print circuit board and semiconductor device Download PDFInfo
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- CN102316668A CN102316668A CN2011101839778A CN201110183977A CN102316668A CN 102316668 A CN102316668 A CN 102316668A CN 2011101839778 A CN2011101839778 A CN 2011101839778A CN 201110183977 A CN201110183977 A CN 201110183977A CN 102316668 A CN102316668 A CN 102316668A
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- palladium
- nickel
- gold
- conductor circuit
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Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
The invention provides a manufacturing method of a substrate with fine metal patterns. The method enables prevention of abnormal metal precipitation on the surface of a resin base when non-electrolyte nickel palladium gold plating processing is performed on the surface of fine metal patterns on a substrate such as the terminal part of a print circuit board. Meanwhile, by the method, high-quality substrate with plating processing faces having fine metal patterns, print circuit boards and semiconductor devices can be obtained. The manufacturing method of the substrate with fine metal patterns comprises the steps of embedding the lower part of a fine metal pattern in a trench equipped on a supporting surface of a substrate made of resin, performing non-electrolyte nickel palladium gold plating processing on the fine metal pattern part which is not in contact with the surface of the trench and making the ratio between the height X the plating area projects on the support surface and the minimum distance Y between patterns (X/Y)less than 0.8.
Description
Technical field
The present invention relates to base material, printed wiring board, semiconductor device and their manufacturing approach with the metal superfine pattern.
Background technology
Based on the purpose of the connection reliability of guaranteeing scolding tin joint, wire-bonded etc., carry out gold-plated to the circuit on the printed wiring board.
As one of gold-plated representative method, electroless plating nickel-golden method is arranged.In the method, after appropriate method such as employing clean are carried out preliminary treatment to the plating object, give palladium catalyst, and then carry out processing of electroless plating nickel and the processing of electroless plating gold successively.ENIG method (Electroless Nickel Immersion Gold: change the nickel gold leaching-out process) is one of non-electrolytic ni plating-golden method, is the processing stage of the electroless plating gold, to carry out the method that immersion gold plating (Immersion Gold: soak gold) is handled.
Adopting the ENIG method that the terminal part is carried out under the gold-plated situation, if this terminal part of wire-bonded and when carrying out heat treated, exist that nickel spread and the problem of connection reliability reduction on golden overlay film.To nickel diffusion problem, increase golden overlay film thickness through on nickel-golden overlay film, further implementing the processing of electroless plating gold, can guarantee thermal endurance.
But from the viewpoint of environmental protection strategy, the melt temperature of the Pb-free solder that must adopt in the future can reach about 260 ℃, is higher than the melt temperature of lead welding tin in the past.Therefore, consider that gold-plated for the terminal part requires to have than higher in the past thermal endurance from the angle of reply Pb-free solder.In the ENIG method, can not fully deal with the heat when implementing Pb-free solder sometimes, and make golden overlay film thicker in order to ensure high-fire resistance, then exist the problem that cost increases more.
In order to address the above problem, begin to inquire into the application of electroless plating nickel-palladium-golden method.In the method, after the electroless plating nickel of above-mentioned electroless plating nickel-golden method is handled, carry out the electroless plating palladium and handle, next carry out the electroless plating gold and handle.
ENEPIG method (Electroless Nickel Electroless Palladium Immersion Gold: change nickel palladium gold leaching-out process) is one of non-electrolytic ni plating-palladium-golden method, is the processing stage of the electroless plating gold of electroless plating nickel-palladium-golden method, to carry out the method (patent documentation 1) that immersion gold plating (Immersion Gold: soak gold) is handled.Adopt electroless plating nickel-palladium-golden method, can prevent the diffusion of conductor material in circuit, the terminal part and can improve corrosion resistance, can prevent nickel generation oxidation and diffusion.In addition; Electroless plating nickel-palladium-Jin Fazhong through electroless plating palladium overlay film is set, can prevent the nickel oxidation that is caused by gold; So can improve the reliability that the big Pb-free solder of heat load engages; Even and nickel diffusion can not take place the thickness that does not increase gold yet, therefore, compare advantage with cost degradation with electroless plating nickel-golden method.
The prior art document
Patent documentation 1: TOHKEMY 2008-144188 communique.
Summary of the invention
The problem that invention will solve
As stated, electroless plating nickel-palladium-Jin Fa compares with electroless plating nickel-golden method, and is high to the connection reliability of high heat load.But find to exist following problem: when the circuit to printed wiring board carries out electroless plating nickel-palladium-gold; In the processing stage of the electroless plating palladium; Around the terminal part of the resin surface that supports conductor circuit; There is metal to separate out unusually, thereby reduced the quality of plating treated side, even become the reason that causes short circuit between the terminals of adjacent sometimes.
And find that be accompanied by the miniaturization of circuit and circuit is narrow more at interval, just easier on the resin surface between the adjacent conductor circuit, the generation separated out unusually.
The present invention accomplishes in order to remove the problems referred to above; Its purpose is; The manufacturing approach of plating item for disposal is provided; In said method, with the conductor circuit surface of the electronic unit beyond the terminal part of printed wiring board or the printed wiring board as the plating process object, in addition also with the surface that is bearing in the metal superfine pattern on the resin base material as the plating process object; And when this type of plating process object face carried out electroless plating nickel-palladium-gold, can be suppressed at as separating out unusually of metal taken place on the resin surface of substrate.
And the object of the invention also is, base material, printed wiring board and the semiconductor device of the band metal superfine pattern with colory plating treated side is provided.
Solve the method for problem
Adopt following technical proposals (1)～(15) can realize above-mentioned purpose.
(1) a kind of base material with the metal superfine pattern is characterized in that,
At least the bottom of metal superfine pattern is embedded in the ditch that is arranged on the area supported that is made up of resin,
Cover by nickel-palladium-gold plate at least a portion zone of aforementioned metal fine pattern with the discontiguous part in aforementioned ditch surface,
When the metal superfine pattern in the zone that will have aforementioned nickel-palladium-gold plate was made as X (wherein, X≤0 o'clock is regarded as X=0) and the minimum range between pattern is made as Y from the projecting height of area supported, ratio (X/Y) was less than 0.8.
(2) like the base material of above-mentioned (1) described band metal superfine pattern, wherein, the live width/gap (line and space) of aforementioned metal fine pattern in the zone with nickel-palladium-gold plate is 5～100 μ m/5～100 μ m (L/S).
(3) a kind of printed wiring board is characterized in that,
At least the bottom of conductor circuit be embedded into core substrate or the area supported that constitutes by insulating barrier in the set ditch,
Cover by nickel-palladium-gold plate at least a portion zone of aforementioned conductor circuit with the discontiguous part in aforementioned ditch surface,
Conductor circuit in the zone that will have aforementioned nickel-palladium-gold plate from the projecting height of area supported be made as X (wherein, X≤0 o'clock is regarded as X=0), when the minimum range between pattern is made as Y, ratio (X/Y) is less than 0.8.
(4) like above-mentioned (3) described printed wiring board, wherein, the live width/gap (line and space) of aforementioned conductor circuit in the zone with nickel-palladium-gold plate is 5～100 μ m/5～100 μ m (L/S).
(5) like above-mentioned (3) or (4) described printed wiring board, wherein, the zone with nickel-palladium-gold plate of aforementioned conductor circuit is the zone that forms terminal.
(6) a kind of semiconductor device is characterized in that, semiconductor element mounted thereon on aforementioned (5) described printed wiring board, and the terminal of this printed wiring board is connected with the output input part of semiconductor element.
(7) a kind of manufacturing approach of the base material with the metal superfine pattern is characterized in that, comprising:
At least the bottom of preparing the metal fine pattern is embedded into the processing that forms in the ditch set on the area supported that is made up of the resin operation with base material, and
To aforementioned processing with carrying out the operation of electroless plating nickel-palladium-gold with the surperficial discontiguous part of aforementioned ditch at least a portion zone of the metal superfine pattern of base material;
Aforementioned metal fine pattern in the zone that will carry out electroless plating nickel-palladium-gold from the projecting height of area supported be made as X (wherein, X≤0 o'clock is regarded as X=0), when the minimum range between pattern is made as Y, ratio (X/Y) is less than 0.8.
(8) like the manufacturing approach of the base material of above-mentioned (7) described band metal superfine pattern, wherein, the live width/gap (L/S) of aforementioned metal fine pattern in the zone of carrying out electroless plating nickel-palladium-gold is 5～100 μ m/5～100 μ m.
(9) like the manufacturing approach of the base material of above-mentioned (7) or (8) described band metal superfine pattern; Wherein, handle in the operation with base material, adopt laser to form ditch at the area supported of handling with base material in aforementioned preparation; And in this ditch deposit, form the metal superfine pattern thus.
(10) like the manufacturing approach of the base material of above-mentioned (7) or (8) described band metal superfine pattern; Wherein, Handle in the operation with base material in aforementioned preparation,, be transferred to the thermoplastic area supported of handling with base material that is able to the metal superfine pattern of metal superfine pattern transfer sheet.
(11) a kind of manufacturing approach of printed wiring board is characterized in that, comprising:
At least the bottom of preparing conductor circuit be embedded in core substrate or the area supported that constitutes by insulating barrier on the processing that forms in the set ditch with the operation of wiring plate, and,
To aforementioned processing with carrying out the operation of electroless plating nickel-palladium-gold with the surperficial discontiguous part of aforementioned ditch at least a portion zone of the conductor circuit of wiring plate;
Aforementioned conductor circuit in the zone that will carry out electroless plating nickel-palladium-gold from the projecting height of area supported be made as X (wherein, X≤0 o'clock is regarded as X=0), when the minimum range between circuit pattern is made as Y, ratio (X/Y) is less than 0.8.
(12) like the manufacturing approach of above-mentioned (11) described printed wiring board, wherein, the live width/gap (L/S) of aforementioned conductor circuit in the zone of carrying out electroless plating nickel-palladium-gold is 5～100 μ m/5～100 μ m.
(13) like the manufacturing approach of above-mentioned (11) or (12) described printed wiring board, wherein, the zone of the enforcement nickel-palladium-gold plate of aforementioned conductor circuit is the zone that forms terminal.
(14) like the manufacturing approach of each described printed wiring board in above-mentioned (11) to (13); Wherein, handle in the operation with wiring plate, adopt laser to form ditch at the area supported of handling with wiring plate in aforementioned preparation; And in this ditch deposit, form conductor circuit thus.
(15) like the manufacturing approach of each described printed wiring board in above-mentioned (11) to (13); Wherein, Handle in the operation with wiring plate in aforementioned preparation,, be transferred to the thermoplastic area supported of handling with wiring plate that is able to the conductor circuit of conductor circuit transfer printing sheet.
The invention effect
Based on the present invention; Embed the metal superfine pattern of the base material of band metal superfine pattern at resin surface; And plating is carried out on the surface of the conductor circuit that exposes to be handled; Reduce the expose area of conductor circuit thus, therefore can reduce reactivity field (space that the reactivity of plating bath is high) because of existing the metal superfine pattern to cause to plating bath.
In addition, reduce the circuit concavo-convex (difference of height of circuit top, top and resin surface) of resin surface through embed the metal superfine pattern at resin surface, so improved the spatter property of resin surface, and improved the removal property of palladium catalyst.
Thereby,, can prevent around the metal superfine pattern of the base material of being with the metal superfine pattern, to take place separating out unusually of metal based on the present invention.
And, in the present invention, at resin surface embedded conductor circuit, therefore, there is no need to reduce the thickness (reducing the circuit sectional area) of metal superfine pattern in order to reduce the exposing area of metal superfine pattern.Thereby, based on the present invention, not only can prevent separating out unusually of metal, but also can avoid the slow problem of signal transmission speed.
The present invention is also surperficial applicable to the conductor circuit of the electronic unit except that printed wiring board; And; Also can in the every field beyond the electronic unit,, and can obtain colory plating face to suitable under the situation that is bearing in the metal superfine pattern enforcement plating on the resin base material.
Description of drawings
Fig. 1 is the sketch map of cross section of an example of printed wiring board of the present invention.
Fig. 2 is the plane graph that the part of the terminal area of amplification printed wiring board is observed.
Fig. 3 is the sketch map of the AA section of Fig. 2.
Fig. 4 is the sketch map of the cross section of the part of embedded conductor circuit layer in ditch.
Fig. 5 is the concept map of the relation of the explanation metal superfine pattern height X and the minimum range Y between pattern that protrude in area supported.
Fig. 6 is only to the sketch map of the cross section of the single face of semiconductor device of the present invention.
Fig. 7 A is the figure that only representes to explain the single face of laser processing step (first half).
Fig. 7 B is the figure that only representes to explain the single face of laser processing step (latter half).
Fig. 8 is the block diagram of the step of expression electroless plating nickel-palladium-gold.
The explanation of Reference numeral
1 printed wiring board
2 core substrates
The conductor circuit layer of 3 (3a, 3b, 3c, 3d) upper face side
4 (4a, 4b, 4c, 4d, 4e, 4f) interlayer insulating film
4c ' area supported
4c " insulating barrier
The conductor circuit layer of side below 5 (5a, 5b, 5c, the 5d)
6 solder masks
The 6a peristome
7 terminal area
The 7a welding disk
Near the 7b welding disk circuit
7b ' metal superfine pattern
The 7c welding disk
8 nickel-palladium-gold plate
9 ditches
10 semiconductor devices
11 semiconductor elements
12 electrode pads
13 chip join material cured layers
14 gold threads
15 encapsulants
16 carrier film
17 laser
18 through holes
19 electroless platings
20 electro depositions
Embodiment
When the conductor circuit of printed wiring board carries out electroless plating nickel-palladium-gold, around conductor circuit, take place to separate out unusually, following for its analysis of causes.
When the conductor circuit of printed wiring board carries out electroless plating nickel-palladium-gold; As preliminary treatment to after being processed face and giving palladium catalyst; Carry out electroless plating nickel; But,, remove Pd fully from resin surface as supporting mass making metal Pd fully under the situation attached to terminal surfaces selectively in the operation stage of giving palladium catalyst
2+Ion is difficult, thinks that this is one of reason.And, remain in the Pd of resin surface
2+Ion is reduced into 0 valency in the electroless plating palladium is bathed, this Pd that is reduced becomes nuclear and makes the growth of metal Pd grain.
And; The reason that resin surface limitation around conductor circuit takes place to separate out unusually is: near terminal; The reactivity of plating bath uprises and nickel is separated out from the dissolving of nickel overlay film, and near a large amount of generation of the resin surface nickel stripping position is replaced into Pd (stripping Ni+ resin surface Pd from Ni
2+→ Ni
2++ Pd) phenomenon.
Particularly, because the zone of clamping between the adjacent conductor circuit is the intensive space of conductor circuit, so the reactivity of plating bath is very high.And the circuit distance between miniaturization and conductor circuit more is more little, and then the dense degree of conductor circuit is high more, and therefore, in the zone of clamping, the reactivity of plating bath uprises between the adjacent conductor circuit.
The inventor finds, through at resin surface embedded conductor circuit, can suppress conductor circuit metal on every side and separate out, and particularly can suppress the metal in the zone of clamping between the adjacent conductor circuit and separate out.
Through at resin surface embedded conductor circuit, reduced the expose area of conductor circuit to plating bath, therefore, can reduce reactivity field (space that the reactivity of plating bath is high) because of existing conductor circuit to cause.
In addition,, reduced the circuit concavo-convex (difference of height of circuit top, top and resin surface) of resin surface, therefore can improve the spatter property of resin surface, and improve the removal property of palladium catalyst through at resin surface embedded conductor circuit.
Even at resin surface embedded conductor circuit not, the thickness (reducing height) through the attenuate conductor circuit also can reduce the expose area of conductor circuit to plating bath; And the circuit that can reduce resin surface is concavo-convex; But this moment is because the cross-sectional area of conductor circuit reduces, therefore; The increase that has a resistance, the problem that the signal transmission speed is slack-off.Particularly, circuit is got over miniaturization, and the slack-off problem of above-mentioned signal transmission speed is just serious more.
To this, in the present invention, to reduce the area that exposes of conductor circuit, therefore there is no need to reduce the thickness of conductor circuit at resin surface embedded conductor circuit.Thereby, based on the present invention, not only can prevent separating out unusually of metal, and can avoid the slack-off problem of signal transmission speed.
In addition; As stated; Separating out unusually when the conductor circuit of printed wiring board carries out electroless plating nickel-palladium-gold, because the miniaturization of conductor circuit and distance between conductor circuit is more little just takes place more easily, and; The cross-sectional area of circuit is more little owing to the miniaturization of conductor circuit, and then the signal transmission speed also becomes slow more.But in the present invention, when the miniaturization conductor circuit carries out electroless plating nickel-palladium-gold, can prevent effectively that metal from separating out, and can avoid the slack-off problem of signal transmission speed.
The present invention is also surperficial applicable to the conductor circuit of the electronic unit beyond the printed wiring board; And; In each field beyond the electronic unit, also can under to the situation that is bearing in the metal superfine pattern enforcement plating on the resin base material, be suitable for, and can obtain colory plating face.
Based on above-mentioned cognition, following invention is provided.
The base material of band metal superfine pattern of the present invention is characterized in that,
At least the bottom of metal superfine pattern is embedded in the ditch set on the area supported that is made up of resin,
Cover the part that does not contact at least a portion zone of aforementioned metal fine pattern by nickel-palladium-gold plate with the surface of aforementioned ditch,
The height that metal superfine pattern in the zone that will have aforementioned nickel-palladium-gold plate protrudes in area supported is made as X (wherein, X≤0 o'clock is regarded as X=0), when the minimum range between pattern is made as Y, ratio (X/Y) is less than 0.8.
In addition, printed wiring board of the present invention is characterized in that,
At least the bottom of conductor circuit be embedded into core substrate or the area supported that constitutes by insulating barrier in the set ditch,
Cover the part that does not contact at least a portion zone of aforementioned conductor circuit with the surface of aforementioned ditch by nickel-palladium-gold plate,,
The height that metal superfine pattern in the zone that will have aforementioned nickel-palladium-gold plate protrudes in area supported is made as X (wherein, X≤0 o'clock is regarded as X=0), when the minimum range between pattern is made as Y, ratio (X/Y) is less than 0.8.
In addition, semiconductor device of the present invention is characterized in that, semiconductor element mounted thereon on the printed wiring board of the invention described above, and connect the terminal of this printed wiring board and the output input part of semiconductor element.
In addition, the manufacturing approach of the base material of band metal superfine pattern of the present invention is characterized in that, comprising:
At least the bottom of preparing the metal fine pattern is embedded into the processing that forms in the ditch set on the area supported that is made up of the resin operation with base material, and
Aforementioned processing is carried out the operation of electroless plating nickel-palladium-gold with the part that does not contact with the surface of aforementioned ditch at least a portion zone of the metal superfine pattern of base material;
And, in the zone of the aforementioned metal fine pattern being carried out electroless plating nickel-palladium-gold from the projecting height of area supported be made as X (wherein, X≤0 o'clock is regarded as X=0), when the minimum range between pattern is made as Y, ratio (X/Y) is less than 0.8.
In addition, the manufacturing approach of printed wiring board of the present invention is characterized in that, comprising:
At least the bottom of preparing conductor circuit be embedded into core substrate or the area supported that constitutes by insulating barrier on the processing that forms in the set ditch with the operation of wiring plate, and
To aforementioned processing with carrying out the operation of electroless plating nickel-palladium-gold with the surperficial discontiguous part of aforementioned ditch at least a portion zone of the conductor circuit of wiring plate;
And, in the zone of aforementioned conductor circuit being carried out electroless plating nickel-palladium-gold from the projecting height of area supported be made as X (wherein, X≤0 o'clock is regarded as X=0), when the minimum range between circuit pattern is made as Y, ratio (X/Y) is less than 0.8.
Below, forming copper circuit, and be that example is explained the present invention in the situation that its terminal area is carried out plating at the outermost layer of printed wiring board.
The structure of printed wiring board at first, is described.
Fig. 1 is the sketch map of cross section of an example of printed wiring board of the present invention.Printed wiring board 1 has core substrate 2, and has the conductor circuit layer on its two sides.At the upper face side of core substrate 2, through interlayer insulating film 4a, 4b, 4c, stacked gradually four layers of conductor circuit layer 3a, 3b, 3c, 3d, side then through interlayer insulating film 4d, 4e, 4f, has stacked gradually four layers of conductor circuit layer 5a, 5b, 5c, 5d below.Conductor circuit layer 3a～3d and 5a～5d are formed on core substrate or by area supported that interlayer insulating film constituted.And outermost layer circuit 3d then is embedded in interlayer insulating film 4c and goes up in the set ditch, conductor circuit layer (3a～3c, 5a～5d), both can be embedded in area supported and can not embed area supported beyond the outermost layer circuit 3d.Each conductor circuit layer of top and bottom can realize that interlayer connects through through hole.As far as the outermost layer circuit 3d of core substrate upper face side, its major part is covered by solder mask 6, but terminal area 7 is to expose from solder mask.The outermost layer circuit 3d of terminal area 7, part outstanding from ditch is covered by nickel-palladium-gold plate 8.The outermost layer circuit 5d of side below the core substrate is to have the mode of the peristome 6a that is used for being connected with mother board (mother board) etc., to be covered by solder mask 6.Printed wiring board 1 through the contact component of solder ball etc. is set at the welding disk 7c that exposes from aforementioned peristome 6a, can be connected with mother board etc.Aforementioned peristome 6a can be between welding disk 7c and soldering-resistance layer 6, gapped structure to be set, and also can be the structure on every side that is covered welding disk 7c by soldering-resistance layer 6.Between welding disk 7c and soldering-resistance layer 6, be provided with the peristome 6a of the structure in gap shown in Fig. 1.Different with aforementioned terminal area 7; Aforementioned peristome 6a does not contain a plurality of splicing ears; Can not produce the short circuit that causes because of separating out unusually, therefore, the surface treatment of aforementioned peristome 6a (not shown); Can be that non-electrolytic ni plating-palladium-gold is handled, also can be the processing of adopting other known surface treatment method.
In addition; Printed wiring board 1 is the stepped construction that has interlayer insulating film on the two sides of core substrate; But printed wiring board of the present invention is not limited thereto, and can be the structure that only has interlayer insulating film at the single face of core substrate, also can be not have interlayer insulating film and the structure of having only core substrate.
Fig. 2 is the part of enlarged ends subregion 7 and the plane graph observed.Terminal area among the present invention is meant by solder mask 6 insulating material such as grade to cover and expose so that circuit layer and the zone that electronic unit (element, circuit etc.) is connected comprise becoming the welding disk of electric connection point 7a and near the circuit 7b of welding disk.
Fig. 3 is the sketch map of the AA section (that is, ditch 9 and the cross section that is embedded near the circuit 7b of terminal in this ditch) among Fig. 2.On interlayer insulating film 4c, be provided with ditch 9, the lower portion of circuit 7b is embedded in the ditch near the terminal.
In addition, the profile of circuit shown in Figure 3 is a rectangle, but limits for circuit profile shape that printed wiring board of the present invention had is not special, is preferably rectangle or square, for example also can be trapezoidal etc.
Among the present invention, so-called " embedding ", the meaning is meant and adopts the material that forms the metal superfine pattern to fill the state of the ditch of area supported.And the metal superfine pattern of conductor circuit etc. is embedded in the state in the ditch, and the pattern that is metal superfine pattern and ditch is consistent and overlapped, and the outward appearance of undercut at least in area supported of metal superfine pattern.
Among the present invention, the height of metal superfine pattern (thickness) can more than or equal to or less than the degree of depth of ditch.At this, the height of so-called metal superfine pattern (thickness) is meant from the height at the top of bottom surface to the metal superfine pattern of ditch, is not " projecting height " from area supported.
The height of metal superfine pattern is meant state as shown in Figure 3 greater than the situation of the degree of depth of ditch.That is, be meant the material complete filling that forms metal superfine pattern (near the circuit 7b of terminal in this example) in the ditch 9 of area supported (interlayer insulating barrier 4c in this example), and the metal superfine pattern is from the outstanding state of area supported.
In addition, the height of metal superfine pattern equals the situation of the degree of depth of ditch, is meant the state shown in Fig. 4 (A).That is, be meant the material complete filling that forms the metal superfine pattern in the ditch 9 of area supported, and be in conplane state with area supported 4c ' above the top of metal superfine pattern 7b '.With the surperficial discontiguous part of ditch, have only above the top of metal superfine pattern 7b ', and have only above this top by nickel-palladium-gold plate 8 coverings.
In addition, the height of metal superfine pattern is meant the state shown in Fig. 4 (B) less than the situation of the degree of depth of ditch.That is, be meant that the material that forms metal superfine pattern 7b ' is fills up in the degree of depth way of ditch of area supported 4c ', and the state that falls in from area supported of metal superfine pattern 7b '.Have only above the top of metal superfine pattern 7b ' with the surperficial discontiguous part of ditch, and have only above this top by nickel-palladium-8 coverings of gold plate.
Separate out the projecting height that limits the conductor circuit in the terminal area 7 for effectively suppressing conductor circuit metal on every side.
Promptly; As shown in Figure 5; In the present invention; The height that metal superfine pattern 7b ' in the zone that will have nickel-palladium-gold plate 8 protrudes in area supported 4c ' is made as X (wherein, X≤0 o'clock is regarded as X=0), when the minimum range between pattern is made as Y, regulate size so that ratio (X/Y) less than 0.8.At this, the situation that projecting height X equals 0 is meant the situation (Fig. 4 (A)) of deep equality of height and the ditch of metal superfine pattern.In addition, projecting height X is regarded as 0 situation, is meant the situation (Fig. 4 (B)) of the height of metal superfine pattern less than the degree of depth of ditch.In addition, not special qualification of actual projecting height X to the height of metal superfine pattern during less than the degree of depth of ditch, but be preferably-20 μ m≤X＜0, be preferably-15 μ m≤X＜0 especially.At this, when projecting height X is negative value, mean that the metal superfine pattern falls in respect to area supported.
In addition, the minimum range Y between pattern is for example under the situation of plane graph shown in Figure 2; Be meant with the distance shown in the lowercase character y, and under the situation of profile shown in Figure 5, be meant with the distance shown in the upper case character Y; That is, be meant and circuit that circuitry shapes is irrelevant between minimum range.For example, if circuitry shapes is meant the distance between the circuit of bottom surface when being trapezoidal, if circuitry shapes is meant the distance between top circuit when being down trapezoidal, if circuitry shapes is meant the distance between the central circuit of circuit when being cylindrical.
As far as above-mentioned printed wiring board 1 and since terminal area 7 around resin surface, particularly adjacent circuit between the clamping position resin surface separate out fewly unusually, therefore, plating treated side best in quality is difficult to be short-circuited.Unusually separate out what cause by nickel plating-palladium-gold; Distance along with the miniaturization of conductor circuit between conductor circuit is more little just to be taken place more easily, and also the circuit cross-sectional area is more little along with the miniaturization of conductor circuit just becomes slow more for the signal transmission speed; But; Based on the present invention, carry out in hope that live width/gap (L/S) is in the scope of 5～100 μ m/5～100 μ m in the zone of electroless plating nickel-palladium-gold of conductor circuit, can prevent effectively that metal from separating out.In above-mentioned live width/gap (L/S), L representes to have the width of the line (pattern) of width, and S representes the gap of line and line.In addition, among the present invention, embedded conductor circuit at resin surface, therefore, there is no need to reduce the thickness of conductor circuit in order to reduce the exposing area of conductor circuit.Therefore, not only separating out unusually of metal can be prevented, and the slack-off problem of signal transmission speed can be avoided.In addition, the live width/gap (L/S) in zone of hoping to carry out the electroless plating nickel-palladium-gold of conductor circuit is preferably 5～50 μ m/5～50 μ m, more preferably 5～25 μ m/5～25 μ m.
Fig. 6 is the figure of cross section that only schematically representes to adopt the semiconductor device single face of above-mentioned printed wiring board 1.Semiconductor device 10 is that semiconductor element mounted thereon 11 forms on printed wiring board 1.
The outermost layer circuit 3d of the upper face side of printed wiring board 1 is covered by solder mask 6, but terminal area exposes from solder mask, and from the ditch of this terminal area outstanding part, then covered by nickel-palladium-gold plate 8.
The encapsulant 15 of employing epoxy resin etc., the mounting semiconductor element side of sealed semiconductor device 10.
Fig. 6 is the example that expression employing wire-bonded connects semiconductor element, but the present invention is applicable to that also the area array type is encapsulated (area array package) waits the terminal part of other connected mode to carry out gold-plated situation.
The method of the printed wiring board 1 that is used for shop drawings 1 then, is described.Wiring plate is used in the processing of at first, preparing to carry out electroless plating nickel-palladium-gold.
Under the situation of printed wiring board 1, use wiring plate as handling, prepare to have the duplexer that printed wiring board shown in Figure 11 lacks the structure of nickel-palladium-gold plate 8.
At this; " handle and use wiring plate " when making printed wiring board; Be meant the intermediate products that become the object that carries out electroless plating nickel-palladium-gold; And have following structure: on the surface of core substrate or the surface that is being laminated on the core substrate and is covering the interlayer insulating film of conductor circuit layer ditch is set; And expose from the plating processing environment with at least a portion zone of the surperficial discontiguous part of ditch in the conductor circuit bottom at least of embedded conductor circuit in this ditch, handles can carry out nickel plating-palladium-gold.
In addition, " handle and use base material " the during base material of the band metal superfine pattern beyond the manufacturing printed wiring board is the base material with the area supported that is made up of resin, and has the structure of the bottom at least of embedded conductor circuit in the ditch that on this area supported, is provided with.In addition, as far as this base material, get final product so long as its surface is constituted and can be embedded the metal superfine pattern by resin, its deep is divided also and can be made up of the material beyond the resin.
As in the method that forms by the structure of the area supported embedded conductor circuit layer that resin constituted such as interlayer insulating film; For example can enumerate: through laser processing; At area supported by resin constituted; Formation has the ditch of the pattern identical with conductor circuit, and after the area supported that is formed with ditch forms conductor layer, removes the method (laser trench (laser trench) processing method) of ditch with the conductor layer of exterior domain.
As other method; Following method is arranged: the conductor circuit transfer printing sheet and base material of conductor circuit of preparing on carrier film, to be provided with the pattern form of regulation with the area supported that constitutes by resin; Overlapping aforementioned transfer printing sheet under the thermoplastic state of the area supported that makes aforementioned substrates; Employing is peeled off or method such as dissolving is removed carrier film, thus the method for transfer printing conductor circuit (transfer printing).
A kind of mode as transfer printing; Following method is arranged: adopt the photosensitive dry film resist; And, on nickel foil, form circuit, and carry out range upon range of with the face that is formed with circuit of this nickel foil and the contacted mode of area supported under the thermoplastic state through the electrolytic copper plating technology according to lithography process; And after carrying out extrusion forming, nickel foil is removed in etching.
Fig. 7 A, Fig. 7 B are the figure of the step of explanation laser processing.In addition, Fig. 7 A and Fig. 7 B are the ideographs of only representing the single face of printed wiring board.Below, specify and adopt the laser processing manufacturing to handle step with wiring plate.
At first, in step (a), prepare to pass through the range upon range of three layers of conductor circuit layer of interlayer insulating film (4a, 4b) (3a, 3b, 3c), and side forms conductor circuit layer 5 below, and each conductor circuit layer is carried out the duplexer that interlayer connects at the upper face side of core substrate 2.
Core substrate can adopt known substrates such as epoxy glass substrate.Lamination on core substrate (build-up) conductor circuit layer also can adopt material known and adopt semi-additive process known method such as (SAP) to carry out.
In addition, prepare at carrier film 16 laminated insulating barrier 4c " resin sheet.Resin sheet also can use can the transfer printing interlayer insulating film known resin sheet.
As far as constituting insulating barrier 4c " resin combination, preferably constitute by the resin combination that contains thermosetting resin.Can improve the thermal endurance of resin bed thus.
And aforementioned dielectric layer 4c " also can contain base materials such as fiberglass substrate.
As thermosetting resin, for example, can enumerate: the phenolic varnish type phenolic resins of phenol novolac resin, cresols novolac resin, bisphenol-A phenolic varnish gum etc.; Unmodified resol, carry out the phenolic resins of resol type phenol resin etc. of the oily modification resol etc. of modification by tung oil, linseed oil, walnut wet goods; The bisphenol-type epoxy resin of bisphenol A epoxide resin, bisphenol F epoxy resin, bisphenol E-type epoxy resin, bisphenol-s epoxy resin, bisphenol Z type epoxy resin, bis-phenol P type epoxy resin, bis-phenol M type epoxy resin etc.; The phenolic resin varnish type epoxy resin of phenol novolak type epoxy resin, cresols phenolic resin varnish etc.; The epoxy resin of biphenyl type epoxy resin, biphenyl aralkyl-type epoxy resin, aryl alkylene type epoxy resin, naphthalene type epoxy resin, anthracene type epoxy resin, phenoxy group type epoxy resin, dicyclopentadiene type epoxy resin, norbornene-type epoxy resin, adamantane type epoxy resin, fluorenes type epoxy resin etc.; The resin with triazine ring of urea (urea) resin, melmac etc.; Unsaturated polyester resin, bimaleimide resin, polyimide resin; Polyamide-imide resin, polyurethane resin, diallyl phthalate ester resin, silicone resin; Resin with benzoxazine ring, cyanate resin, benzocyclobutane olefine resin; Cyanate ester resin, bismaleimide compound etc.
Wherein, be preferably more than one the resin that is selected from epoxy resin, phenolic resins, cyanate ester resin, bismaleimide compound and the benzocyclobutane olefine resin, be preferably cyanate ester resin especially.Can reduce the thermal coefficient of expansion of resin bed thus.And electrical characteristics (low-k, the low-dielectric loss factor), mechanical strength that can make resin bed etc. are also good.
As cyanate ester resin, particularly, can enumerate the bisphenol type cyanate ester resin of phenolic varnish type cyanate ester resin, bisphenol A cyanate ester resin, bisphenol E-type cyanate resin, tetramethyl Bisphenol F type cyanate ester resin etc. etc.Wherein, be preferably the phenolic varnish type cyanate ester resin.The phenolic varnish type cyanate ester resin can reduce the thermal coefficient of expansion of resin bed, and can make the mechanical strength of resin bed, electrical characteristics (low-k, the low-dielectric loss factor) also good.
Do not limit for the weight average molecular weight of cyanate ester resin is special, but preferable weight-average molecular weight is 500～4500, is preferably 600～3000 especially.If weight average molecular weight is lower than aforementioned lower limit, then the mechanical strength of resin bed solidfied material can reduce sometimes, and produces viscosity under the situation of resin bed sometimes or resin transfer takes place being made into.In addition, if weight average molecular weight surpasses aforementioned higher limit, then curing reaction accelerates, and under the situation that forms substrate (particularly circuit substrate), the bad or reduction interlaminar strength of moulding takes place sometimes.In addition, the weight average molecular weight of cyanate ester resin etc. for example, can adopt GPC (gel permeation chromatography; Convert as standard substance with polystyrene) measure.
As bismaleimide compound, not special the qualification, for example; Can enumerate: 4; 4 '-diphenyl methane dimaleimide, 1,3-phenylene BMI (m-phenylene dimaleimide), 1,4-phenylene BMI (p-phenylenedimaleimide), 2; 2 '-two [4-(4-maleimide phenoxyl) phenyl] propane, two-(3-ethyl-5-methyl-4-dimaleoyl imino phenyl) methane, (4-methyl isophthalic acid; The 3-phenylene) BMI, 1,2-dimaleimide base ethane (N, N '-ethylenedimaleimide), 1; 6-dimaleimide base hexane (N, N '-hexamethylene dimaleimide) etc.; As maleimide, can enumerate polyphenylene methane maleimide (polyphenylmethane maleimide) etc.Wherein, consider from the low equal angles of water absorption rate, be preferably 2,2 '-two [4-(4-maleimide phenoxyl) phenyl] propane, two-(3-ethyl-5-methyl-4-dimaleoyl imino phenyl) methane.
Content for thermosetting resin does not limit especially, but is preferably 5～50 weight % of resin combination total amount, particularly is preferably 10～40 weight %.If content is lower than lower limit, then be difficult to form resin bed sometimes; If surpass higher limit, then the intensity of resin bed reduces sometimes.
When adopting cyanate ester resin (particularly phenolic varnish type cyanate ester resin), preferred and with epoxy resin (in fact not halogen atom) as thermosetting resin.
As epoxy resin; For example, can enumerate: the bisphenol-type epoxy resin of bisphenol A epoxide resin, bisphenol F epoxy resin, bisphenol E-type epoxy resin, bisphenol-s epoxy resin, bisphenol Z type epoxy resin, bis-phenol P type epoxy resin, bis-phenol M type epoxy resin etc.; The phenolic resin varnish type epoxy resin of phenol novolak type epoxy resin, cresols phenolic resin varnish etc.; Biphenyl type epoxy resin, xylylene type epoxy resin; The aryl alkylene type epoxy resin of biphenyl aralkyl-type epoxy resin etc.; Naphthalene type epoxy resin; Anthracene type epoxy resin; Phenoxy group type epoxy resin, dicyclopentadiene type epoxy resin, norbornene-type epoxy resin, adamantane type epoxy resin, fluorenes type epoxy resin etc.
As epoxy resin, both can use wherein a kind of separately, also can and with different two or more of weight average molecular weight, perhaps also can be with one or more prepolymer usefulness also with them.
For the content of epoxy resin, do not have special the qualification, but be preferably 1～55 weight % of resin combination total amount, be preferably 5～40 weight % especially.If content is lower than aforementioned lower limit, then the reactivity of cyanate ester resin reduces the perhaps moisture-proof reduction of the product that obtains sometimes; If said content surpasses aforementioned higher limit, then low heat expansion, thermal endurance reduce sometimes.
For the weight average molecular weight of epoxy resin, not special the qualification, but preferable weight-average molecular weight is 500～20000, is preferably 800～15000 especially.If weight average molecular weight is lower than aforementioned lower limit, then on resin layer surface, produce viscosity sometimes; If surpass aforementioned higher limit, then the scolding tin thermal endurance reduces sometimes.Through weight average molecular weight is in the above-mentioned scope, can make them good in balance of properties.The weight average molecular weight of epoxy resin for example, can adopt GPC (gel permeation chromatography converts as standard substance with polystyrene) to measure.
Constitute the resin combination of the resin bed of printed wiring board of the present invention, can be for containing the resin combination of inorganic filling material.As the average grain diameter of the inorganic filling material that in the resin combination that constitutes resin bed, can contain, be preferably more than the 0.05 μ m and below the 0.5 μ m.Thus, can form insulating reliability height, fine wiring that signal response property is good.
Mensuration about the average grain diameter of inorganic filling material for example, can adopt the laser diffraction and scattering method to measure.Can adopt ultrasonic wave that inorganic filling material is disperseed in water, and adopt laser diffraction formula particle size distribution device (LA-500, HORIBA makes), be the particle size distribution that benchmark is made inorganic filling material with the volume, with its median diameter (D50) as average grain diameter.
Maximum particle diameter as the inorganic filling material that in the resin combination that constitutes resin bed, can contain is preferably below the 2.0 μ m.Thus, can form insulating reliability height, fine wiring that signal response property is good.In addition, though not special the qualification, more preferably the maximum particle diameter of inorganic filling material is below the 1.8 μ m, and is preferably especially below the 1.5 μ m.Thus, can bring into play the effect that improves insulating reliability, signal response property effectively.
If the average grain diameter of the inorganic filling material that can contain in the resin combination of formation resin bed is higher than the maximum particle diameter of above-mentioned higher limit or inorganic filling material and is higher than above-mentioned higher limit; Then inorganic filling material hinders laser processing sometimes, and on resin bed, the position of ditch occurs forming.And, adopt the time of laser formation ditch elongated, therefore might reduce operability.In addition, because of after the laser processing on the ditch side wall surface residual inorganic filling material, cause that the concave-convex surface of the conductor layer behind the plating becomes big.Thus, the deterioration in accuracy of wiring, and damage the insulating reliability in the high density printed wiring board sometimes.And then, in surpassing the high-frequency region of 1GHz, damage signal response property because of kelvin effect sometimes.
Be lower than above-mentioned lower limit if constitute the average grain diameter of the inorganic filling material that can contain in the resin combination of resin bed, then reduce the physical propertys such as thermal coefficient of expansion, modulus of elasticity of resin combination, the installation reliability during the infringement semiconductor element mounted thereon.
As the inorganic filling material that can contain in the resin combination that constitutes resin bed, not special the qualification for example can be enumerated: talcum, calcined clay, the silicate of calcined clay, mica, glass etc. not; The oxide of titanium oxide, aluminium oxide, silicon dioxide, fused silica etc.; The carbonate of calcium carbonate, magnesium carbonate, hydrotalcite etc.; The hydroxide of aluminium hydroxide, magnesium hydroxide, calcium hydroxide etc.; The sulfate or the sulphite of barium sulfate, calcium sulfate, calcium sulfite etc.; The borate of Firebrake ZB, methyl-boric acid barium, aluminium borate, line borate, Boratex etc.; The nitride of aluminium nitride, boron nitride, silicon nitride, carbonitride etc.; The titanate of strontium titanates, barium titanate etc. etc.As inorganic filling material, both can use wherein a kind of separately, also can and with two or more.Wherein, particularly, be preferably silicon dioxide, more preferably fused silica from the good viewpoint of low heat expansion, anti-flammability and modulus of elasticity.Wherein, preferably it is shaped as spherical silicon dioxide.
The carrier film 16 of resin sheet, have can be with insulating barrier 4c the " release property of transfer printing (translocation is write) on the conductor circuit layer.Do not limit for carrier film is special, can use polymeric membrane or metal forming.As polymeric membrane, for example, can use mylar such as PETG, polybutylene terephthalate (PBT), fluorine-type resin, polyimide resin etc. have a stable on heating thermoplastic resin film.As metal forming; For example, can use copper and/or copper series alloy, aluminium and/or aluminum series alloy, iron and/or iron-based alloy, silver and/or silver is that alloy, gold and gold are that alloy, zinc and Zn based alloy, nickel and nickel system alloy, tin and tin are metal forming of alloy etc. etc.
Do not limit for the thickness of carrier film is special, but the good viewpoint of operability when making resin sheet, preferably adopt the carrier film of 10～70 μ m thickness.
Do not limit for the thickness of insulating layer on the carrier film is special, but be preferably 1～60 μ m, be preferably 5～40 μ m especially.As far as the thickness of resin bed, be preferably more than the aforementioned lower limit from the angle that improves insulating reliability, and, then be preferably below the aforementioned higher limit from the angle of the filmization that realizes multilayer printed-wiring board.
Do not limit for the manufacturing approach of resin sheet is special, for example can enumerate: make the resin combination dissolving, be scattered in the solvent etc. and prepare resin varnish, and adopt various apparatus for coating behind coating resin varnish on the carrier film, make its dry method; Perhaps, adopt sprayer unit behind spraying coating resin varnish on the carrier film, make its dry method etc.Wherein, preferably adopt comma coating machine (comma coater), compression mod coating machine various apparatus for coating such as (die coater) behind coating resin varnish on the carrier film, to make its dry method.Thus, can make the resin sheet that does not have the space and have even resin layer thickness efficiently.
In addition, the carrier film of resin sheet can be the carrier film of surface roughening, also can be the carrier film of roughening not.As the method for the carrier film surface roughening that makes resin sheet, for example, can enumerate and adopt the etching soup to carry out the method for chemical roughening, the method that the employing grinder carries out the physics roughening etc.
Then, in step (b), make the upper face side of the duplexer of preparing in insulating barrier side and the above-mentioned steps (a) of resin sheet overlapping face-to-face, then, in step (c), peel off carrier film, form interlayer insulating film 4c.
In addition, carrier film can not peeled off in step (c), and after peel off after stating the laser processing in the step (d).
Then, in step (d), irradiating laser 17 forms ditch 9 on interlayer insulating film 4c surface.When laser processing; Regulate size, the shape of ditch; So that plan is carried out in the zone that nickel plating-palladium-gold handles in the conductor circuit that finally forms along ditch, height X that circuit is given prominence to from area supported and the ratio (X/Y) of the minimum range Y between circuit pattern is less than 0.8.
In addition, do not limit for ditch 9 is special, but the degree of depth that is preferably formed to aforementioned ditch 9 is below 50% of interlayer insulating film 4c thickness.
Laser is preferably PRK or YAG (yttrium-aluminium-garnet) laser.Through adopting these laser, can form precision, the good fine wiring of shape.Do not limit for the optical maser wavelength of PRK is special, but be preferably 193nm, 308nm, 248nm, be preferably 193nm, 248nm especially.Thus, bring into play the effect that can form fine wiring effectively with good precision and shape.Preferred YAG Wavelength of Laser is 355nm.Under the situation of other wavelength, the resin combination that constitutes interlayer insulating film does not absorb laser, might can't form fine wiring.
Then, in step (e), on interlayer insulating film 4c, form the Lu Jinghou of through hole 18, adopt electroless plating to apply and form electroless plating 19 on the surface of interlayer insulating film 4c to guarantee that interlayer connects.For the metal species of electroless plating 19, not special the qualification, but be preferably copper, nickel etc.
In addition, after forming ditch 9 and through hole 18,, can suitably append the slag operation of removing photoresist in order to improve adhesiveness.
Then, implementation step (f) forms electro deposition 20 as required.In the electrolysis plating, can use copper sulphate electrolysis plating.
Then, in step (g),, thereby only form outermost layer circuit 3d in ditch 9 parts through the electroless plating 19 and electro deposition 20 of removal ditch with exterior domain.Do not limit the method for removing electroless plating 19 and electro deposition 20 is special, but be preferably chemical etching processing, milled processed, polishing etc.Thus, can only remove electroless plating 19 and electro deposition 20 on the resin surface effectively, and only keep conductor circuit in ditch 9 parts.
Then, in step (h), on outermost layer circuit 3d, form solder mask 6, at this moment,, obtain thus to handle to use wiring plate through from solder mask 6 part of bared end subregion 7 (not shown) only.
Use wiring plate through above-mentioned steps (a) to the processing that (h) obtained, in the outermost layer circuit, have only terminal area 7 to expose from solder mask, therefore, the terminal area that can be directed against the outermost layer circuit carried out electroless plating nickel-palladium-gold selectively.
Among the present invention; When only hoping that a part of zone of conductor circuit or metal superfine pattern carried out electroless plating nickel-palladium-gold; Except using the permanent resist such as solder mask, can also use other plating such as solubility resist, moulding article mask to handle and use mask.
Fig. 8 is the block diagram of expression electroless plating nickel-palladium-golden step.Below, specify the step of aforementioned electroless plating nickel-palladium-gold.
When the outermost layer copper circuit of printed wiring board being carried out plating,, can adopt one or more method that surface treatment is carried out in this terminal part as required as the preliminary treatment before the operation of giving palladium catalyst according to the present invention.In Fig. 8, show clean (S1a), soft etching (S1b), acid treatment (S1c), pre-preg (S1d) as preliminary treatment, handle processing in addition but also can carry out these.
After aforementioned preliminary treatment,, form nickel-palladium-gold (Ni-Pd-Au) overlay film through giving palladium catalyst, electroless plating nickel, electroless plating palladium and electroless plating gold in order.
In electroless plating nickel-palladium of the present invention-golden method, preliminary treatment (S1), the operation (S2) of giving palladium catalyst, electroless plating nickel handle that (S3), electroless plating palladium are handled (S4), the electroless plating gold is handled (S5), can with likewise carried out in the past.
Below, the processing stage of in order each of S1～S5 being described.
< preliminary treatment (S1) >
(1) clean (S1a)
Clean (S1a) as one of preliminary treatment; It is implemented purpose and is: the clean solution through making acid type or alkaline type contacts with terminal surfaces; Remove organic overlay film from terminal surfaces, make the metal activeization of terminal surfaces, improve the wettability of terminal surfaces.
The cleaning solution of acid type mainly is the cleaning solution that partly the carrying out etching as thin as a wafer of terminal surfaces is made surface activation.As to copper tip effective cleaning liquid, can adopt the solution (for example, ACL-007, C. Uyemura & Co Ltd's manufacturing) that contains hydroxycarboxylic acid, ammonia, sodium chloride, surfactant.As to effective other the acid type cleaning solution of copper tip, also can adopt the solution (for example, ACL-738, C. Uyemura & Co Ltd's manufacturing) that contains sulfuric acid, surfactant, sodium chloride, the wetability of this solution is high.
The cleaning solution of alkalescence type mainly is a cleaning solution of removing organic overlay film.As to copper tip effective cleaning liquid, can adopt the solution (for example, ACL-009, C. Uyemura & Co Ltd's manufacturing) that contains non-ionic surface active agent, 2-monoethanolamine, diethylenetriamine.
When carrying out clean, can adopt methods such as dipping, spraying to make above-mentioned cleaning solution arbitrarily and the terminal part contacts after, wash and get final product.
(2) soft etch processes (S1b)
As other pretreated soft etch processes (S1b), be to carry out to remove oxide-film for the part as thin as a wafer of terminal surfaces is carried out etching.As to the effective soft etching solution of copper tip, can adopt the acid solution that contains sodium peroxydisulfate and sulfuric acid.
When carrying out soft etch processes, adopt methods such as dipping, spraying to make above-mentioned soft etching solution and the terminal part contacts after, wash and get final product.
(3) pickling processes (S1c)
As other pretreated pickling processes (S1c), be in order to remove dirt (copper fine particle) from terminal surfaces or near the resin surface it and to carry out.
As to the effective pickle of copper tip, can adopt sulfuric acid.
When carrying out pickling processes, can adopt methods such as dipping, spraying to make above-mentioned pickle and the terminal part contacts after, wash.
(4) pre-preg (S1d)
As other pretreated pre-preg (S1d); Be meant before giving the operation of palladium catalyst; Give the processing of flooding in the essentially identical sulfuric acid of liquid in concentration and catalyst, it is implemented purpose and is: improve the hydrophily of terminal surfaces, thereby improve the tack of giving the Pd ion that contains in the liquid to catalyst; Or thereby avoiding washing water flow into catalyst and gives in the liquid and can utilize catalyst to give liquid repeatedly again, or removes oxide-film.As presoak, can adopt sulfuric acid.
When carrying out pre-preg, in above-mentioned presoak, flood the terminal part.In addition, after pre-preg, do not wash.
< giving the operation (S2) of palladium catalyst >
Make and contain Pd
2+The acid liquid (catalyst is given liquid) of ion contacts with terminal surfaces, and through ionization trend (Cu+Pd
2+→ Cu
2++ Pd), on terminal surfaces with Pd
2+Ion exchange is a metal Pd.Be attached to the Pd of terminal surfaces, the catalyst that applies as electroless plating plays a role.As Pd
2+The palladium salt of ion supply source can adopt palladium sulfate or palladium bichloride.
The absorption affinity of palladium sulfate than palladium bichloride a little less than, remove Pd easily, therefore be suitable for forming fine rule.As giving liquid to the effective palladium sulfate series catalysts of copper tip; Can adopt contain sulfuric acid, palladium salt and mantoquita strong acid liquid (for example; KAT-450, C. Uyemura & Co Ltd makes), perhaps can use contain hydroxycarboxylic acid (oxycarboxylic acid), sulfuric acid and palladium salt strong acid liquid (for example; MNK-4, C. Uyemura & Co Ltd makes).
On the other hand, the absorption affinity of palladium bichloride, displacement property are strong, are difficult to remove Pd, therefore, under causing the inadhering condition of plating easily, carry out electroless plating when applying, and can obtain to prevent the inadhering effect of plating.
When giving the operation of palladium catalyst, can adopt methods such as dipping, spraying to make above-mentioned catalyst give liquid and contact with the terminal part, wash then.
< electroless plating nickel is handled (S3) >
Bathe as electroless plating nickel, for example, can adopt the plating bath that contains water soluble nickel salt, reducing agent and complexing agent (complexing agent).The details of bathing about electroless plating nickel for example, has been recorded in the japanese kokai publication hei 8-269726 communique etc.
As water soluble nickel salt, adopt nickelous sulfate, nickel chloride etc., and its concentration is about 0.01～1 mol.
As reducing agent, adopt the hypophosphites of hypophosphorous acid, sodium hypophosphite etc.; Dimethylamino borine, trimethylamine groups borine, hydrazine etc., its concentration is about 0.01～1 mol.
As complexing agent, adopt the carboxylic acids of malic acid, butanedioic acid, lactic acid, citric acid etc. or their sodium salt etc., the amino acids of glycine, alanine, iminodiacetic acid, arginine, glutamic acid etc., and its concentration is about 0.01～2 mol.
This plating bath is adjusted to pH4～7, and in about 40～90 ℃ uses of bath temperature.When in this plating bath, using hypophosphorous acid as reducing agent, following main reaction is carried out in the effect on the copper tip surface through the Pd catalyst, and forms the Ni electroplated film.
Ni
2++H
2PO
2-+H
2O+2e
-→Ni+H
2PO
3-+H
2
< the electroless plating palladium is handled (S4) >
Bathe as the electroless plating palladium, for example, can adopt the plating bath that contains palladium compound, complexing agent, reducing agent, unsaturated carboxylic acid compounds.
As palladium compound, for example, adopt palladium bichloride, palladium sulfate, acid chloride, palladium nitrate, tetramino hydrochloric acid palladium etc., and be that its concentration of benchmark is about 0.001～0.5 mol with the palladium.
As complexing agent, adopt the amines of ammonia or methylamine, dimethylamine, methylene diamine, EDTA etc. etc., its concentration is about 0.001～10 mol.
As reducing agent, adopt the hypophosphites of hypophosphorous acid or sodium hypophosphite, ammonium hypophosphite etc. etc., and its concentration is about 0.001～5 mol.
As unsaturated carboxylic acid compounds; Adopt unsaturated carboxylic acids such as acrylic acid, methacrylic acid, maleic acid, their acid anhydrides, salt such as their sodium salt or ammonium salt; And the derivative of their ethyl ester, phenylester etc. etc., and its concentration is about 0.001～10 mol.
This plating bath is adjusted to pH4～10, and in about 40～90 ℃ uses of bath temperature.When in this plating bath, using hypophosphorous acid, carry out following main reaction on copper tip surface (in fact at nickel surface), and form the Pd electroplated film as reducing agent.
Pd
2++H
2PO
2-+H
2O→Pd+H
2PO
3-+2H
+
< the electroless plating gold is handled (S5) >
Bathe as the electroless plating gold, for example, can adopt the plating bath that contains water-soluble gold compound, complexing agent and aldehyde compound.The detailed content of bathing for electroless plating gold for example, has been recorded in the TOHKEMY 2008-144188 communique etc.
As water-soluble gold compound, for example, adopt gold cyanide salt such as gold cyanide, potassium auricyanide, gold sodium cyanide, gold cyanide ammonium, its concentration is about 0.0001～1 mol when being benchmark with the gold.
As complexing agent, for example, adopt phosphoric acid, boric acid, citric acid, gluconic acid, tartaric acid, lactic acid, malic acid, ethylenediamine, triethanolamine, ethylenediamine tetra-acetic acid etc., and its concentration is about 0.001～1 mol.
As aldehyde compound (reducing agent), for example, adopt the aliphat saturated aldehyde of formaldehyde, acetaldehyde etc.; Aliphatic dialdehydes such as glyoxal, butanedial class; Aliphat unsaturated aldehydes such as crotonaldehyde; The aromatic aldehyde of benzaldehyde, o-nitrobenzaldehyde, m-nitrobenzaldehyde or paranitrobenzaldehyde etc.; Glucose, galactolipin etc. contain aldehyde radical (carbohydrate CHO) etc., and its concentration is about 0.0001～0.5 mol.
This plating bath is adjusted to pH5～10, and in about 40～90 ℃ uses of bath temperature.When adopting this plating bath, (be actually surperficial) on the copper tip surface and carry out following two displacement reactions, and form the Au electroplated film at palladium.
Pd+Au
+→Pd
2++Au+e
-
e
-+ Au
+→ Au (wherein, e
-Be under the effect of Au autocatalyst, the composition in the plating bath to be carried out oxidation to obtain)
In addition, in above-mentioned electroless plating nickel-palladium-gold, can give the operation of palladium catalyst (S2) back, carry out electroless plating palladium processing (S4) preceding any stage, remove operation (back dipping (post dip) operation) attached to the Pd catalyst of resin surface.As back dipping operation, for example, following method is arranged: adopt KCN to make Pd
2+Ion and KCN reaction forms complex ion and makes the method for catalyst deactivation, perhaps adopts acid liquid to wash Pd
2+The method of ion etc.
Through above-mentioned steps, on the circuit of printed wiring board, form colory Ni-Pd-Au electroplated film, and the resin surface around terminal is guaranteed no abnormal plating treated side that separate out, colory.
Can on printed wiring board of the present invention, semiconductor element be installed, produce the high semiconductor device of connection reliability with the said method manufacturing.
Embodiment
Below, come further explain the present invention through showing embodiment, but the present invention is not limited to these.
< embodiment 1 >
(making of test film)
With following substance dissolves, be scattered in the MEK: 20 weight portion phenolic varnish type cyanate ester resins (Primaset PT-30, weight average molecular weight is about 700, Long Sha Amada Co., Ltd. (Lonza Japan Ltd.) makes); 35 weight portion methoxynaphthalene ethylene type epoxy resin (EXA-7320, Dainippon Ink. & Chemicals Inc's (Dainippon Ink and Chemicals Inc.) makes); 5 weight portion phenoxy resins (jER4275, japan epoxy resin Co., Ltd. (Japan Epoxy Resins Co.Ltd.) makes); 0.2 weight portion imidazolium compounds (Curezol (trade mark) 1B2PZ (1-benzyl-2-phenylimidazole), four countries change into industrial strain formula society and make).And; With fusion spherical silicon dioxide (SFP-20M; Deuki Kagaku Kogyo Co., Ltd makes) adopt cascade type cartridge filter (manufacturing of Sumitomo 3M Co., Ltd.) isolated by filtration to surpass the particle of maximum particle diameter 2.0 μ m, make average grain diameter reach 0.4 μ m, add 40 weight portions then.And; Add 0.2 weight portion epoxy silane coupling agent (A-187, organosilicon Co., Ltd. of General Electric Toshiba (GE Toshiba Silicones Co. Ltd.) makes); Adopt high-speed stirring apparatus to stir then 10 minutes, prepare the resin varnish that solid constituent is 50 weight %.
Adopt comma coating machine (comma coater) device; On the single face of the PET (PETG) of 25 μ m thickness carrier film; So that dried thick resin film becomes the mode of 40 μ m; Be coated with the above-mentioned resin varnish that obtains, and make its drying in 160 ℃ drying device produce resin sheet in 10 minutes.
Be superimposed in the table with this resin sheet and internal layer circuit substrate; And adopt vacuum pressure type laminater under 100 ℃ of temperature, 1MPa pressure, it to be carried out the heating in vacuum extrusion forming; Then, adopt hot-air drying device under 180 ℃, to be heating and curing 45 minutes, obtain the substrate of band resin bed.
In addition, as the internal layer circuit substrate, adopted following substrate.
● insulating barrier: Halogen FR-5 material, thickness are 0.4mm
● conductor layer: copper thickness is 18 μ m, L/S=120/180 μ m, and clearance hole (clearance hole) is 1mm Φ, 3mm Φ, the slit is 2mm Φ
After peeling off carrier film (PET), adopt the PRK with 193nm wavelength, on the resin bed of the substrate of being with resin bed, formation live width/gap (L/S)=40 μ m/40 μ m, target depth are the ditch of 15 μ m.
The duplexer that is obtained was flooded 10 minutes in 60 ℃ swelling liquid (Swelling Dip Securiganth P, Atotech Amada Co., Ltd. (Atotech Japan K.K.) make); And at 80 ℃ potassium permanganate solutions (コ Application セ Application ト レ one ト コ Application パ Network ト CP (trade name); Atotech Amada Co., Ltd. makes) in dipping after 20 minutes, neutralize and the slag of implementing to remove photoresist is handled.
After this being carried out degreasing, giving the operation of catalyst, activate, form the electroless plating copper layer of about 0.2 μ m.
Then, with electroless plating copper layer as electrode, with 3A/dm
2(TopLucina α, Okuno Chemical Industries Co., Ltd. (Okuno Chemical Industries Co., Ltd.) make) are the conductor layer of about 20 μ m thereby form from the thickness of resin surface layer to carry out 60 minutes electrolytic copper plating.
On the conductor layer surface, the range upon range of dry film photoresist of roll-in (AR320, Tokyo answers chemical industry society to make), and adopt the negative film (negative film) of regulation to make public, develop, formed the required platedresist of conductor circuit.After adopting sudden strain of a muscle erosion (flash etching) to handle the exposed division of (the SAC technology that weak former electricity produces Co., Ltd.) removal pattern form, dry film is peeled off (stripper: the R-100 that Mitsubishi Gas Chemical Co., Ltd (Mitsubishi Gas Chemical Company Inc.) makes; Splitting time: 240 seconds).
Then, make insulating resin layer under 200 ℃ of temperature, through after 60 minutes full solidification, implement the circuit roughened (roughened liquid: CZ8101, (MEC Co. Ltd.) makes in Mitsuku K.K.; 1 μ m roughening condition), produce the test film of the copper circuit of (the L/S)=40 μ m/40 μ m that has live width/gap, projecting height (X)=20 μ m, X/Y=0.50.
(electroless plating nickel-palladium-metal working preface (ENEPIG operation))
With following step, above-mentioned test film is carried out the ENEPIG operation, obtain four layers of printed wiring board of embodiment 1.
(1) clean
As cleaning solution, the ACL-007 that adopts C. Uyemura & Co Ltd to make floods above-mentioned test film 5 minutes in the cleaning solution of 50 ℃ of liquid temperature, washes then 3 times.
(2) soft etch processes
After the clean, the mixed liquor that adopts sodium peroxydisulfate and sulfuric acid floods above-mentioned test film 1 minute in the soft etching solution of 25 ℃ of liquid temperature as soft etching solution, washes then 3 times.
(3) pickling processes
After the soft etch processes, above-mentioned test film was flooded 1 minute in the sulfuric acid of 25 ℃ of liquid temperature, wash then 3 times.
(4) pre-preg
After the pickling processes, above-mentioned test film was flooded 1 minute in the sulfuric acid of 25 ℃ of liquid temperature.
(5) give the operation of palladium catalyst
After the pre-preg, in order to give palladium catalyst to wiring portion, palladium catalyst solution is given in the KAT-450 conduct of adopting C. Uyemura & Co Ltd to make.Gave in the palladium catalyst solution dipping 2 minutes with above-mentioned test film at this of 25 ℃ of liquid temperature, wash then 3 times.
(6) electroless plating Ni handles
After giving the operation of palladium catalyst, above-mentioned test film was bathed (NPR-4, C. Uyemura & Co Ltd makes) middle dipping 35 minutes at the electroless plating Ni of 80 ℃ of liquid temperature, wash then 3 times.
(7) electroless plating Pd handles
After electroless plating Ni handles, above-mentioned test film was bathed (TPD-30, C. Uyemura & Co Ltd makes) middle dipping 15 minutes at the electroless plating Pd of 50 ℃ of liquid temperature, wash then 3 times.
(8) electroless plating Au handles
After electrolysis plating Pd handles, above-mentioned test film was bathed (TWX-40, C. Uyemura & Co Ltd makes) middle dipping 18 minutes at the electroless plating Au of 80 ℃ of liquid temperature, wash then 3 times.
< embodiment 2 >
Except setting live width/gap (L/S)=20 μ m/20 μ m, projecting height (X)=15 μ m, the X/Y=0.75, likewise operating, produce four layers of printed wiring board with embodiment 1.
< embodiment 3 >
Except setting live width/gap (L/S)=25 μ m/25 μ m, removing (etch down) cathode copper 20 μ m so that projecting height (X)=0 μ m, the X/Y=0, likewise operate, produce four layers of printed wiring board with embodiment 1 at the electrolytic copper plating after etching.
< embodiment 4 >
Except setting live width/gap (L/S)=25 μ m/25 μ m, removing cathode copper 25 μ m so that projecting height (X)＜0 μ m (in fact X=-5 μ m), make the X/Y=0 at the electrolytic copper plating after etching; Likewise operate with embodiment 1, produce four layers of printed wiring board.
< comparative example 1 >
Except setting live width/gap (L/S)=25 μ m/25 μ m, projecting height (X)=20 μ m, the X/Y=0.80, likewise operating, produce four layers of printed wiring board with embodiment 1.
< comparative example 2 >
Except setting live width/gap (L/S)=25 μ m/25 μ m, projecting height (X)=25 μ m and the X/Y=1.00, likewise operating, produce four layers of printed wiring board with embodiment 1.
About the printed wiring board that is obtained in each embodiment and the comparative example, carried out following evaluation.Assessment item is illustrated with content, and the result who is obtained is shown in Table 1.
< that separates out unusually has or not >
Adopt electron microscope (reflected electron image), the terminal part of printed wiring board is observed, estimate having or not of separating out unusually.
Zero: no abnormal separating out
△: have in the limit of circuit and somely to separate out unusually
*: in whole interval, have unusually and separate out
< Insulation Test >
Have or not short circuit between the wiring of the printed wiring board that is obtained in adopted conduction test machine (X=YC Hightester1116, day puts Electric Co., Ltd (HIOKI) and makes) probatio inspectionem pecuoarem embodiment and the comparative example.
Zero: no conducting
*: conducting is arranged
Table 1
*Actual projecting height (X) is-5 μ m.
In the printed wiring board that embodiment 1～4 is obtained, do not separate out unusually between wiring or separate out unusually few, and the insulation between also can keeping after the ENEPIG operation connecting up.On the other hand, can confirm that the printed wiring board that is obtained in the comparative example 1,2 has separates out unusually and confirms to exist the short circuit between wiring.Hence one can see that; Embedded conductor circuit and this conductor circuit are the printed wiring board of the present invention of characteristic from the projecting height X of area supported and the ratio (X/Y) of the minimum range Y between circuit pattern less than 0.8 in resin surface, can prevent metal around the circuit separate out unusually and effective to the insulation between wiring.
< comparative example 3 >
Live width/gap (L/S) that the plan of conductor circuit will be carried out the zone of electroless plating nickel-palladium-gold is set at the 40 μ m/40 μ ms same with embodiment 1; And to adopt not conductor circuit embedded resin surface and the thickness that exists only in the conducting channel of resin surface be the conducting channel that the method in the past of 20 μ m is made; Compare with the conducting channel of embodiment 1; Its cross-sectional area only has an appointment 60%, and resistance increases to about 2 times.
Based on the present invention, not only can prevent separating out unusually of metal, and can avoid the slack-off problem of signal transmission speed.
Claims (15)
1. the base material with the metal superfine pattern is characterized in that,
At least the bottom of metal superfine pattern is embedded in the ditch set on the area supported that is made up of resin,
Cover at least a portion zone of aforementioned metal fine pattern and surperficial discontiguous part aforementioned ditch by nickel-palladium-gold plate,
When the metal superfine pattern in the zone that will have aforementioned nickel-palladium-gold plate from the projecting height of area supported be made as X, when the minimum range between pattern is made as Y, ratio X/Y is less than 0.8, wherein, X≤0 o'clock is regarded as X=0.
2. the base material of band metal superfine pattern as claimed in claim 1, wherein, the live width/gap of aforementioned metal fine pattern in the zone with nickel-palladium-gold plate is that L/S is 5～100 μ m/5～100 μ m.
3. a printed wiring board is characterized in that,
At least the bottom of conductor circuit be embedded into core substrate or the area supported that constitutes by insulating barrier in the set ditch,
Cover at least a portion zone of aforementioned conductor circuit and surperficial discontiguous part aforementioned ditch by nickel-palladium-gold plate,
When the conductor circuit in the zone that will have aforementioned nickel-palladium-gold plate from the projecting height of area supported be made as X, when the minimum range between pattern is made as Y, ratio X/Y is less than 0.8, wherein, X≤0 o'clock is regarded as X=0.
4. printed wiring board as claimed in claim 3, wherein, the live width/gap of aforementioned conductor circuit in the zone with nickel-palladium-gold plate is that L/S is 5～100 μ m/5～100 μ m.
5. like claim 3 or 4 described printed wiring boards, wherein, the zone with nickel-palladium-gold plate of aforementioned conductor circuit is the zone that forms terminal.
6. a semiconductor device is characterized in that, semiconductor element mounted thereon on the described printed wiring board of claim 5, and the terminal of this printed wiring board is connected with the output input part of semiconductor element.
7. the manufacturing approach with the base material of metal superfine pattern is characterized in that, comprising:
At least the bottom of preparing the metal fine pattern is embedded into the processing that forms in the ditch set on the area supported that is made up of the resin operation with base material, and
To aforementioned processing with the operation of carrying out electroless plating nickel-palladium-gold at least a portion zone of the metal superfine pattern of base material with the surperficial discontiguous part of aforementioned ditch;
Projecting height from area supported in the zone of the aforementioned metal fine pattern being carried out electroless plating nickel-palladium-gold is made as X, when the minimum range between pattern is made as Y, ratio X/Y is less than 0.8, wherein, X≤0 o'clock is regarded as X=0.
8. the manufacturing approach of the base material of band metal superfine pattern as claimed in claim 7, wherein, the live width/gap of aforementioned metal fine pattern in the zone of carrying out electroless plating nickel-palladium-gold is that L/S is 5～100 μ m/5～100 μ m.
9. like the manufacturing approach of the base material of claim 7 or 8 described band metal superfine patterns; Wherein, handle in the operation with base material, adopt laser to form ditch at the area supported of handling with base material in aforementioned preparation; And in this ditch deposit, form the metal superfine pattern thus.
10. like the manufacturing approach of the base material of claim 7 or 8 described band metal superfine patterns; Wherein, Handle in the operation with base material in aforementioned preparation, with the metal superfine pattern of metal superfine pattern transfer sheet, transfer printing is being handled with the area supported after the thermoplastic of base material.
11. the manufacturing approach of a printed wiring board is characterized in that, comprising:
At least the bottom of preparing conductor circuit be embedded into core substrate or the area supported that constitutes by insulating barrier on the processing that forms in the set ditch with the operation of wiring plate, and
To aforementioned processing with carrying out the operation of electroless plating nickel-palladium-gold with the surperficial discontiguous part of aforementioned ditch at least a portion zone of the conductor circuit of wiring plate;
Projecting height from area supported in the zone of aforementioned conductor circuit being carried out electroless plating nickel-palladium-gold is made as X, when the minimum range between circuit pattern is made as Y, ratio X/Y is less than 0.8, wherein, X≤0 o'clock is regarded as X=0.
12. the manufacturing approach of printed wiring board as claimed in claim 11, wherein, the live width/gap of aforementioned conductor circuit in the zone of carrying out electroless plating nickel-palladium-gold is that L/S is 5～100 μ m/5～100 μ m.
13. the manufacturing approach of printed wiring board as claimed in claim 11, wherein, the zone of carrying out nickel-palladium-gold plate of aforementioned conductor circuit is the zone that forms terminal.
14. manufacturing approach like each described printed wiring board in the claim 11 to 13; Wherein, handle in the operation with wiring plate, adopt laser to form ditch at the area supported of handling with wiring plate in aforementioned preparation; And in this ditch deposit, form conductor circuit thus.
15. like the manufacturing approach of each described printed wiring board in the claim 11 to 13, wherein, handle in the operation with wiring plate in aforementioned preparation, with the conductor circuit of conductor circuit transfer printing sheet, transfer printing is being handled with the area supported after the thermoplastic of wiring plate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010-141916 | 2010-06-22 | ||
| JP2010141916A JP2012009510A (en) | 2010-06-22 | 2010-06-22 | Base material with metal fine pattern, printed wiring board, and semiconductor device, and method of manufacturing base material with metal fine pattern and printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102316668A true CN102316668A (en) | 2012-01-11 |
Family
ID=45429366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101839778A Pending CN102316668A (en) | 2010-06-22 | 2011-06-21 | Substrate with fine metal pattern, print circuit board and semiconductor device, and production method of substrate with fine metal pattern, print circuit board and semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2012009510A (en) |
| KR (1) | KR20110139105A (en) |
| CN (1) | CN102316668A (en) |
| TW (1) | TW201230902A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111972052A (en) * | 2018-04-12 | 2020-11-20 | 株式会社富士 | Printed circuit board forming method and printed circuit board forming apparatus |
| CN112385022A (en) * | 2018-07-06 | 2021-02-19 | 高通股份有限公司 | High density interconnect in Embedded Trace Substrate (ETS) including core layer |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6013750B2 (en) * | 2011-08-17 | 2016-10-25 | 株式会社 大昌電子 | Printed wiring board and manufacturing method thereof |
| KR101410395B1 (en) * | 2013-01-17 | 2014-06-20 | 한진화학(주) | Method for plating an antenna according to double injection molding |
| KR101484938B1 (en) * | 2014-11-05 | 2015-01-21 | (주)오알켐 | Electroless Copper PLATING METHOD FOR MANUFACTURING MULTI LAYER PCB Using Ion Palladium Catalyst |
| US9881884B2 (en) | 2015-08-14 | 2018-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
| US11955409B2 (en) | 2021-01-13 | 2024-04-09 | Qualcomm Incorporated | Substrate comprising interconnects in a core layer configured for skew matching |
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| JP2000058986A (en) * | 1998-08-04 | 2000-02-25 | Matsushita Electric Ind Co Ltd | Wiring board and its manufacture |
| CN1674763A (en) * | 2004-03-25 | 2005-09-28 | Tdk株式会社 | Circuit assembly and method of manufacturing the circuit assembly |
| JP2006339609A (en) * | 2005-06-06 | 2006-12-14 | Kyocer Slc Technologies Corp | Wiring board and manufacturing method of the same |
| JP2007103648A (en) * | 2005-10-04 | 2007-04-19 | Hitachi Chem Co Ltd | Printed circuit board, manufacturing metehod thereof, semiconductor chip mounting substrate, manufacturing method thereof and semiconductor package |
| CN101469420A (en) * | 2007-04-16 | 2009-07-01 | 上村工业株式会社 | Electroless gold-plating method and electronic component |
| JP2010021302A (en) * | 2008-07-10 | 2010-01-28 | Kaneka Corp | Printed wiring board |
-
2010
- 2010-06-22 JP JP2010141916A patent/JP2012009510A/en active Pending
-
2011
- 2011-06-15 KR KR1020110058032A patent/KR20110139105A/en not_active Application Discontinuation
- 2011-06-17 TW TW100121202A patent/TW201230902A/en unknown
- 2011-06-21 CN CN2011101839778A patent/CN102316668A/en active Pending
Patent Citations (6)
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|---|---|---|---|---|
| JP2000058986A (en) * | 1998-08-04 | 2000-02-25 | Matsushita Electric Ind Co Ltd | Wiring board and its manufacture |
| CN1674763A (en) * | 2004-03-25 | 2005-09-28 | Tdk株式会社 | Circuit assembly and method of manufacturing the circuit assembly |
| JP2006339609A (en) * | 2005-06-06 | 2006-12-14 | Kyocer Slc Technologies Corp | Wiring board and manufacturing method of the same |
| JP2007103648A (en) * | 2005-10-04 | 2007-04-19 | Hitachi Chem Co Ltd | Printed circuit board, manufacturing metehod thereof, semiconductor chip mounting substrate, manufacturing method thereof and semiconductor package |
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| JP2010021302A (en) * | 2008-07-10 | 2010-01-28 | Kaneka Corp | Printed wiring board |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111972052A (en) * | 2018-04-12 | 2020-11-20 | 株式会社富士 | Printed circuit board forming method and printed circuit board forming apparatus |
| CN111972052B (en) * | 2018-04-12 | 2024-02-06 | 株式会社富士 | Printed board forming method and printed board forming apparatus |
| CN112385022A (en) * | 2018-07-06 | 2021-02-19 | 高通股份有限公司 | High density interconnect in Embedded Trace Substrate (ETS) including core layer |
| CN112385022B (en) * | 2018-07-06 | 2021-11-30 | 高通股份有限公司 | High density interconnect in Embedded Trace Substrate (ETS) including core layer |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201230902A (en) | 2012-07-16 |
| KR20110139105A (en) | 2011-12-28 |
| JP2012009510A (en) | 2012-01-12 |
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Application publication date: 20120111 |