KR20100114884A - 반도체 기판 표면 제조 방법 - Google Patents

반도체 기판 표면 제조 방법 Download PDF

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Publication number
KR20100114884A
KR20100114884A KR1020107016195A KR20107016195A KR20100114884A KR 20100114884 A KR20100114884 A KR 20100114884A KR 1020107016195 A KR1020107016195 A KR 1020107016195A KR 20107016195 A KR20107016195 A KR 20107016195A KR 20100114884 A KR20100114884 A KR 20100114884A
Authority
KR
South Korea
Prior art keywords
oxide
layer
substrate
semiconductor substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020107016195A
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English (en)
Korean (ko)
Inventor
라두안 칼리드
Original Assignee
에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 filed Critical 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지
Publication of KR20100114884A publication Critical patent/KR20100114884A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
KR1020107016195A 2008-02-13 2009-01-23 반도체 기판 표면 제조 방법 Withdrawn KR20100114884A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08290138A EP2091070A1 (en) 2008-02-13 2008-02-13 Semiconductor substrate surface preparation method
EP08290138.0 2008-02-13

Publications (1)

Publication Number Publication Date
KR20100114884A true KR20100114884A (ko) 2010-10-26

Family

ID=39638664

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020107016195A Withdrawn KR20100114884A (ko) 2008-02-13 2009-01-23 반도체 기판 표면 제조 방법

Country Status (6)

Country Link
US (1) US8062957B2 (enExample)
EP (2) EP2091070A1 (enExample)
JP (1) JP2011512040A (enExample)
KR (1) KR20100114884A (enExample)
CN (1) CN101952934A (enExample)
WO (1) WO2009101494A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160058816A (ko) * 2013-09-25 2016-05-25 에베 그룹 에. 탈너 게엠베하 기판 본딩 장치 및 방법

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4894390B2 (ja) * 2006-07-25 2012-03-14 信越半導体株式会社 半導体基板の製造方法
JP6030455B2 (ja) * 2013-01-16 2016-11-24 東京エレクトロン株式会社 シリコン酸化物膜の成膜方法
JP2015233130A (ja) * 2014-05-16 2015-12-24 株式会社半導体エネルギー研究所 半導体基板および半導体装置の作製方法
US10964664B2 (en) * 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
JP2020057810A (ja) * 2019-12-23 2020-04-09 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板をボンディングする装置および方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238865A (en) * 1990-09-21 1993-08-24 Nippon Steel Corporation Process for producing laminated semiconductor substrate
EP1179842A3 (en) * 1992-01-31 2002-09-04 Canon Kabushiki Kaisha Semiconductor substrate and method for preparing same
JP3116628B2 (ja) * 1993-01-21 2000-12-11 株式会社日本自動車部品総合研究所 吸着装置
JP2978748B2 (ja) * 1995-11-22 1999-11-15 日本電気株式会社 半導体装置の製造方法
US6007641A (en) * 1997-03-14 1999-12-28 Vlsi Technology, Inc. Integrated-circuit manufacture method with aqueous hydrogen-fluoride and nitric-acid oxide etch
TW460617B (en) * 1998-11-06 2001-10-21 United Microelectronics Corp Method for removing carbon contamination on surface of semiconductor substrate
US6709989B2 (en) * 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
JP2004266075A (ja) * 2003-02-28 2004-09-24 Tokyo Electron Ltd 基板処理方法
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
EP1667214B1 (en) * 2003-09-10 2012-03-21 Shin-Etsu Handotai Co., Ltd. Method for cleaning a multilayer substrate and method for bonding substrates and method for producing bonded wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160058816A (ko) * 2013-09-25 2016-05-25 에베 그룹 에. 탈너 게엠베하 기판 본딩 장치 및 방법
KR20200133282A (ko) * 2013-09-25 2020-11-26 에베 그룹 에. 탈너 게엠베하 기판 본딩 장치 및 방법
KR20210135624A (ko) * 2013-09-25 2021-11-15 에베 그룹 에. 탈너 게엠베하 기판 본딩 장치 및 방법

Also Published As

Publication number Publication date
US8062957B2 (en) 2011-11-22
JP2011512040A (ja) 2011-04-14
EP2091070A1 (en) 2009-08-19
CN101952934A (zh) 2011-01-19
EP2091074A1 (en) 2009-08-19
US20110053342A1 (en) 2011-03-03
WO2009101494A1 (en) 2009-08-20

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20100720

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid