KR20100068660A - 적층 웨이퍼 레벨 패키지 및 이의 제조 방법 - Google Patents
적층 웨이퍼 레벨 패키지 및 이의 제조 방법 Download PDFInfo
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- KR20100068660A KR20100068660A KR1020080127091A KR20080127091A KR20100068660A KR 20100068660 A KR20100068660 A KR 20100068660A KR 1020080127091 A KR1020080127091 A KR 1020080127091A KR 20080127091 A KR20080127091 A KR 20080127091A KR 20100068660 A KR20100068660 A KR 20100068660A
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- 229910000679 solder Inorganic materials 0.000 description 6
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (12)
- 재배열 배선층;상기 재배열 배선층 하부에 배치되며 상기 재배열 배선층과 전기적으로 접속하는 외부접속수단;상기 재배열 배선층 상부에 배치되며 상기 재배열 배선층과 전기적으로 접속된 칩 접속 패드;상기 칩 접속 패드와 접속되도록 상기 재배열 배선층상에 실장된 반도체 칩;상기 재배열 배선층과 전기적으로 연결된 금속 포스트;상기 금속 포스트의 일부를 노출하며 상기 반도체 칩을 밀봉하는 밀봉부재; 및상기 밀봉부재상에 적층되며 상기 노출된 금속포스트와 전기적으로 연결된 전자부품;을 포함하는 적층 웨이퍼 레벨 패키지.
- 제 1 항에 있어서,상기 전자부품은 반도체 칩, 모듈 및 패키지 중 어느 하나의 형태를 갖는 적층 웨이퍼 레벨 패키지.
- 제 1 항에 있어서,적어도 상기 칩 접속 패드와 반도체 칩의 연결부분을 덮는 버퍼부를 더 포함하는 웨이퍼 레벨 패키지.
- 제 1 항에 있어서,상기 전자부품과 상기 밀봉부재사이에 충진된 적층 버퍼부를 더 포함하는 적층 웨이퍼 레벨 패키지.
- 제 1 항에 있어서,상기 반도체 칩의 실장은 솔더링, 도전성 페이스트, 비전도성 페이스트(Non-Conductive Paste;NCP) 및 이방성 전도성 필름(Anisotropic Conductive Film;ACF) 중 어느 하나를 이용하는 적층 웨이퍼 레벨 패키지.
- 기판을 준비하는 단계;상기 기판상에 도전층을 형성하는 단계;상기 도전층과 전기적으로 연결된 금속 포스트를 형성하는 단계;상기 도전층상에 칩 접속 패드를 형성하는 단계;상기 칩 접속 패드와 접속되도록 상기 도전층상에 반도체 칩을 실장하는 단계;상기 금속포스트 및 상기 반도체 칩을 밀봉하는 밀봉부재를 형성하는 단계;상기 도전층으로부터 상기 기판을 분리하는 단계;상기 도전층을 식각하여 재배열 배선층을 형성하는 단계;상기 재배열 배선층에 외부 접속수단을 형성하는 단계; 및상기 밀봉부재상에 상기 금속포스트와 전기적으로 접속되도록 전자부품을 적층하는 단계;를 포함하는 적층 웨이퍼 레벨 패키지의 제조 방법.
- 제 6 항에 있어서,상기 반도체 칩과 상기 칩 접속 패드간의 접속은 솔더링, 도전성 페이스트, 비전도성 페이스트(Non-Conductive Paste;NCP) 및 이방성 전도성 필름(Anisotropic Conductive Film;ACF) 중 어느 하나를 이용하는 적층 웨이퍼 레벨 패키지의 제조 방법.
- 제 6 항에 있어서,적어도 상기 칩 접속 패드과 반도체 칩의 연결부분을 덮는 버퍼부를 더 형성하는 웨이퍼 레벨 패키지의 제조 방법.
- 제 6 항에 있어서,적어도 상기 금속포스트와 상기 전자부품의 연결부분을 감싸는 적층 버퍼부를 더 형성하는 적층 웨이퍼 레벨 패키지의 제조 방법.
- 제 6 항에 있어서,적어도 상기 금속포스트와 상기 전자부품의 연결부분을 감싸는 적층 버퍼부를 더 형성하는 적층 웨이퍼 레벨 패키지의 제조 방법.
- 제 6 항에 있어서,상기 재배열 배선층에 외부 접속수단을 형성하는 단계이후에 상기 밀봉부재에 상기 금속포스트를 노출하는 콘택홀을 형성하는 단계; 및상기 콘택홀에 접속부재를 충진하는 단계를 더 포함하는 웨이퍼 레벨 패키지의 제조 방법.
- 제 6 항에 있어서,상기 밀봉부재를 형성하는 단계에 있어서, 상기 밀봉부재는 상기 금속 포스트를 노출하도록 형성되는 웨이퍼 레벨 패키지의 제조 방법.
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KR1020080127091A KR101003658B1 (ko) | 2008-12-15 | 2008-12-15 | 적층 웨이퍼 레벨 패키지 및 이의 제조 방법 |
US12/458,454 US8704350B2 (en) | 2008-11-13 | 2009-07-13 | Stacked wafer level package and method of manufacturing the same |
US12/929,703 US8658467B2 (en) | 2008-11-13 | 2011-02-09 | Method of manufacturing stacked wafer level package |
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KR1020080127091A KR101003658B1 (ko) | 2008-12-15 | 2008-12-15 | 적층 웨이퍼 레벨 패키지 및 이의 제조 방법 |
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KR20100068660A true KR20100068660A (ko) | 2010-06-24 |
KR101003658B1 KR101003658B1 (ko) | 2010-12-23 |
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KR101476774B1 (ko) * | 2013-05-15 | 2014-12-26 | 삼성전기주식회사 | 패키지용 기판과 그 제조방법 및 전자소자 패키지와 그 제조방법 |
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US9991190B2 (en) * | 2012-05-18 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging with interposer frame |
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JP2002170921A (ja) * | 2000-12-01 | 2002-06-14 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
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KR101476774B1 (ko) * | 2013-05-15 | 2014-12-26 | 삼성전기주식회사 | 패키지용 기판과 그 제조방법 및 전자소자 패키지와 그 제조방법 |
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