KR20090086023A - Wiring substrate and method of manufacturing the same - Google Patents

Abstract

A capacitor (350) is formed of a dielectric layer (330), and a first electrode (310) and a second electrode (320), which confront each other across a dielectric layer (300). The capacitors (350) are laminated on a capacitor laminated body (450) through adhesive (340). A wiring board (900) is provided with a first resin insulating layer (200a) incorporating the capacitor laminated body (450), a first via conductor (411) which electrically connects the first electrodes (310), a second via conductor (412) which electrically connects the second electrodes (320), a first external terminal (427P) which is electrically connected to the first via conductor (411) and a second external terminal (427G) which is electrically connected to the second via conductor (412). The first electrode (310) and the second electrode (320) are dislocated and arranged in a face direction of the electrodes. ® KIPO & WIPO 2009

Description

Wiring board and its manufacturing method {WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a wiring board incorporating a capacitor and a method of manufacturing the same.

In response to the demand for miniaturization of electronic devices, it is desired to increase the mounting efficiency of the electronic components constituting the electronic devices. Therefore, in order to raise mounting efficiency, the wiring board which integrated the capacitor is disclosed by following patent document 1. As shown in FIG.

However, in the wiring board disclosed in this publication, it is difficult to achieve both high capacity of the capacitor built in the wiring board and securing of insulation resistance.

This is because, if the capacitor is to be made high in capacity, the dielectric layer of the capacitor is made thin. If the dielectric layer is made thin, the insulation resistance of the capacitor is reduced. On the other hand, if the insulation resistance of the capacitor is to be secured, the dielectric layer is made thick, and the capacity of the capacitor cannot be increased.

In addition, a wiring board including a plurality of capacitors formed by alternately stacking a dielectric layer and an electrode is disclosed in Patent Document 2 below. In the wiring board disclosed in this publication, the thickness of the dielectric layer is set to a thickness necessary for obtaining the insulation resistance of the capacitor, and a plurality of capacitors are arranged to increase the capacity as a whole.

However, in the wiring board disclosed in this publication, if one capacitor is defective, a defect occurs in the entire capacitor laminate.

[Patent Document 1] Japanese Unexamined Patent Publication No. 2005-191559

[Patent Document 2] Japanese Unexamined Patent Publication No. 2004-228190

The present invention has been made to solve the above problems, and an object thereof is to provide a wiring board having a capacitor having a high capacity and an insulation resistance. In addition, an object of the present invention is to provide a wiring board having a capacitor having a high capacitance and an insulation resistance secured by securing a yield of a wiring board having a capacitor laminate in which capacitors are stacked. Moreover, an object of this invention is to provide the manufacturing method of such a wiring board.

In order to achieve the above object, the wiring board according to the first aspect of the present invention,

A capacitor stack formed by laminating a dielectric layer, a capacitor formed by opposing first and second electrodes with the dielectric layer interposed therebetween, using an adhesive;

A first resin insulating layer containing the capacitor laminate;

A first via conductor electrically connecting the first electrodes to each other,

A second via conductor electrically connecting the second electrodes to each other,

A first external terminal electrically connected to the first via conductor;

It has a 2nd external terminal electrically connected with the said 2nd via conductor, It is characterized by the above-mentioned.

In order to achieve the above object, a wiring board according to a second aspect of the present invention,

A plurality of resin insulating layers having at least the lowest resin insulating layer and the highest resin insulating layer;

A plurality of conductor circuits formed between the resin insulating layers,

Condenser lamination, which is embedded in one resin insulating layer among the plurality of resin insulating layers, and is formed by laminating a capacitor formed of a dielectric layer and a first electrode and a second electrode facing each other with the dielectric layer interposed therebetween by an adhesive. Chewwa,

A first via conductor electrically connecting the first electrodes to each other,

A second via conductor electrically connecting the second electrodes to each other,

A first external connection terminal formed on the lowest resin insulating layer, the first external terminal comprising a first external terminal electrically connected to the first via conductor, and a second external terminal electrically connected to the second via conductor; ,

A second external connection terminal formed on the resin insulating layer of the uppermost layer and having a third external terminal electrically connected to the first via conductor and a fourth external terminal electrically connected to the second via conductor; Have,

The first external connection terminal is embedded in the resin insulating layer of the lowermost layer, and the external terminal surface of the first external connection terminal is located on substantially the same plane as the first surface of the resin insulating layer of the lowest layer.

The second external connection terminal is formed on the resin insulating layer of the uppermost layer.

Moreover, in order to achieve the said objective, the manufacturing method of the wiring board which concerns on the 3rd viewpoint of this invention is

A capacitor making step of preparing a capacitor having a dielectric layer and a first electrode and a second electrode opposing each other with the dielectric layer interposed therebetween;

A capacitor laminate-forming step of creating a capacitor laminate by laminating the capacitor through an adhesive;

A lamination step of laminating a first resin insulating layer on the base substrate,

A embedding step of embedding the capacitor laminate in the first resin insulating layer;

A through-hole forming step of forming a through-hole penetrating the first electrodes and a through-hole penetrating the second electrodes in the capacitor laminate;

Filling the through-holes with a metal conductor, a via conductor creation step of creating a first via conductor electrically connecting the first electrodes and a second via conductor electrically connecting the second electrodes;

It has an external terminal creation process which produces the 1st external terminal electrically connected with the said 1st via conductor, and the 2nd external terminal electrically connected with the said 2nd via conductor.

Moreover, in order to achieve the said objective, the manufacturing method of the wiring board which concerns on the 4th viewpoint of this invention is

A capacitor making step of producing a capacitor having a dielectric layer and a first electrode and a second electrode opposing each other with the dielectric layer interposed therebetween;

A capacitor laminate-forming step of creating a capacitor laminate by laminating the capacitor through an adhesive;

A first external connection terminal forming step of forming a first external connection terminal having a first external terminal and a second external terminal on a support plate;

A build-up step of alternately stacking a plurality of resin insulating layers and a plurality of conductor circuits on the first external connection terminal and the support plate;

A embedding step of embedding the capacitor laminate in one of the plurality of resin insulating layers;

A through-hole forming step of forming a through-hole in the capacitor stack, through which the first electrode or the second electrode passes;

Filling the through-holes with a metal conductor, a via conductor creation step of creating a first via conductor electrically connecting the first electrodes and a second via conductor electrically connecting the second electrodes;

A second external connection terminal forming step of forming a second external connection terminal having a third external terminal and a fourth external terminal on the uppermost resin insulating layer positioned on the opposite side to the support plate among the plurality of resin insulating layers;

It has a support plate removal process of removing the said support plate,

The first external terminal and the third external terminal are electrically connected to the first via conductor, and the second external terminal and the fourth external terminal are electrically connected to the second via conductor. do.

Effect of the Invention

According to the present invention, it is possible to obtain a wiring board in which a capacitor having a high capacity and an insulation resistance is secured.

1 is a cross-sectional view of a wiring board according to a first embodiment of the present invention.

2A is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment in which the first electrode, the dielectric layer, and the second electrode are laminated.

2B is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment in which the positions of the first electrode and the second electrode are shifted.

FIG. 2C is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment in which the capacitor is laminated to form a capacitor laminate. FIG.

2D is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment, showing the capacitor laminate in which the capacitor is laminated via an adhesive.

2E is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment, in which a resin insulating layer is laminated on the base substrate.

2F is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment, in which the capacitor laminate is embedded in the resin insulating layer.

2G is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment, showing the resin insulating layer in which the capacitor laminate is embedded.

2H is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment, in which a capacitor laminate is laminated on a resin insulating layer.

2I is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment, in which a second resin insulating layer is further laminated on the resin insulating layer.

FIG. 2J is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment in which through holes for the via conductor are formed in the capacitor stack. FIG.

It is a figure explaining the capacitor laminated body of the wiring board which concerns on Embodiment 1 from an upper surface.

2L is an explanatory diagram illustrating the capacitor laminate of the wiring board according to the first embodiment, from an upper surface thereof.

It is a figure explaining the manufacturing process of the wiring board which concerns on Embodiment 1 which forms a conductor pattern in a 2nd resin insulating layer.

It is a figure explaining the manufacturing process of the wiring board which concerns on Embodiment 1 which further laminate | stacks a 3rd resin insulating layer.

It is a figure explaining the manufacturing process of the wiring board which concerns on Embodiment 1 which forms a conductor pattern in a 3rd resin insulating layer.

2P is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment, in which a plurality of openings are formed in the solder resist.

FIG. 2Q is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment in which the IC chip is mounted via solder bumps. FIG.

2R is an explanatory diagram illustrating the manufacturing process of the wiring board according to the first embodiment, in which a resin insulating layer is also formed on the lower surface of the base substrate.

3 is a cross-sectional view of a wiring board according to a second embodiment of the present invention.

4A is an explanatory diagram illustrating the manufacturing process of the wiring board according to the second embodiment, wherein through holes for via conductors are formed in the capacitor stack.

4B is an explanatory diagram illustrating the manufacturing process of the wiring board according to the second embodiment, in which a conductor pattern is formed on the upper surface of the capacitor laminate and the resin insulating layer.

4C is an explanatory diagram illustrating the manufacturing process of the wiring board according to the second embodiment, further forming a second resin insulating layer.

4D is an explanatory diagram illustrating the manufacturing process of the wiring board according to the second embodiment, in which a resin insulating layer is also formed on the lower surface of the base substrate.

Fig. 5 is a sectional view of a wiring board according to Embodiment 3, showing a capacitor stack in which via conductors are formed in openings of the first electrode and the second electrode.

6A is an explanatory diagram illustrating a via conductor penetrating a capacitor stack of a wiring board according to the third embodiment in a lattice shape.

6B is an explanatory diagram illustrating the via conductor penetrating the capacitor stack of the wiring board according to the third embodiment in a zigzag shape.

FIG. 7A is an explanatory diagram illustrating a capacitor single body of a wiring board according to Embodiment 3 in which a first electrode, a dielectric layer, and a second electrode are laminated; FIG.

FIG. 7B is an explanatory diagram illustrating the capacitor single body of the wiring board according to the third embodiment in which the first electrode and the second electrode are patterned. FIG.

FIG. 7C is a plan view for explaining a capacitor on which a wiring board according to Embodiment 3 is patterned from the first electrode side; FIG.

FIG. 7D is a plan view illustrating the capacitor on which the wiring board according to the third embodiment is patterned from the second electrode side; FIG.

FIG. 7E is an explanatory diagram illustrating the manufacturing process of the wiring board according to the third embodiment, in which a capacitor laminate is prepared by laminating the patterned capacitor. FIG.

FIG. 7F is an explanatory diagram illustrating the manufacturing process of the wiring board according to the third embodiment, showing the capacitor laminate in which the patterned capacitor is laminated via an adhesive; FIG.

FIG. 7G is an explanatory diagram illustrating the manufacturing process of the wiring board according to the third embodiment, in which the capacitor laminate in which the patterned capacitor is laminated is embedded in a resin insulating layer. FIG.

FIG. 7H is an explanatory diagram illustrating the manufacturing process of the wiring board according to the third embodiment, wherein through holes are formed in the capacitor stack in which the patterned capacitor is laminated. FIG.

FIG. 7I is an explanatory diagram illustrating the manufacturing process of the wiring board according to the third embodiment in which a via conductor and a conductor pattern are formed in a capacitor laminate in which the patterned capacitor is laminated. FIG.

8 is a cross-sectional view of a wiring board according to a fourth embodiment of the present invention.

9A is an explanatory diagram illustrating a supporting plate that supports a resin insulating layer in a manufacturing step of a wiring board according to the fourth embodiment.

9B is an explanatory diagram illustrating the step of forming a plating resist on a support plate in the manufacturing process of the wiring board according to the fourth embodiment.

FIG. 9C is an explanatory diagram illustrating a step of forming a plurality of openings in a plating resist formed on a support plate in a manufacturing step of a wiring board according to the fourth embodiment. FIG.

9D is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which external terminals are formed in opening portions of the plating resist.

9E is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment, in which a first resin insulating layer is formed on the support plate.

9F is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which through holes are formed in the first resin insulating layer formed on the support plate.

9G is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment, in which a conductor pattern is formed on the upper surface of the first resin insulating layer.

9H is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment, in which a second resin insulating layer is formed on the first resin insulating layer.

9I is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which the capacitor laminate is embedded in the second resin insulating layer.

9J is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment, illustrating the second resin insulating layer in which the capacitor laminate is embedded.

9K is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which through holes are formed in the second resin insulating layer in which the capacitor laminate is embedded.

9L is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which a via conductor and a conductor pattern are formed in a second resin insulating layer.

9M is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment, in which a third resin insulating layer is formed on the second resin insulating layer.

FIG. 9N is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which through holes are formed in the third resin insulating layer. FIG.

9O is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which a via conductor and a conductor pattern are formed in a third resin insulating layer.

9P is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which a solder resist is formed on the third resin insulating layer.

9Q is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which external terminals are formed in a plurality of opening portions formed in the solder resist.

9R is an explanatory diagram illustrating the manufacturing process of the wiring board according to the fourth embodiment in which the supporting plate is removed by etching.

10 is a diagram showing a modification of the wiring board according to the fourth embodiment of the present invention.

11 is a cross-sectional view of a wiring board according to Embodiment 5 in which a capacitor laminate is also embedded in a resin insulating layer formed below the base substrate.

<Description of the symbols for the main parts of the drawings>

100: base substrate

200: resin insulation layer

310: first electrode

320: second electrode

330: dielectric layer

340: adhesive

350: condenser

411: Via Conductor

412: via conductor

413: Via Conductor

414: Via Conductor

421: Conductor Pattern

423: Conductor Pattern

425 conductor pattern

450: condenser laminate

710: alignment mark

720: alignment mark

730: alignment mark

900: wiring board according to the present invention

Best Mode for Carrying Out the Invention

<1st embodiment of the wiring board in one specific embodiment of this invention>

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described, referring drawings.

As shown in FIG. 1, the wiring board 900 according to the present embodiment includes a first resin insulating layer 200a, a base substrate 100 supporting the first resin insulating layer 200a, and a first substrate. The capacitor laminated body 450 embedded in the resin insulating layer 200a is provided.

The second resin insulating layer 200b is formed on the first resin insulating layer 200a. The third resin insulating layer 200c is formed on the second resin insulating layer 200b.

The upper surface of the capacitor laminate 450 is on the upper surface of the first resin insulating layer 200a, and the upper surface of the capacitor laminate 450 and the upper surface of the first resin insulating layer 200a are the same surface.

The capacitor stack 450 is obtained by stacking the capacitors 350a, 350b, and 350c through the adhesive 340. The adhesive 340 is an insulating resin, for example, an epoxy resin.

The thickness of the capacitor | condenser laminated body 450 is 30 micrometers-100 micrometers, for example. If it is thicker than 100 μm, it may be difficult to embed the capacitor laminate 450 in the first resin insulating layer 200a. On the other hand, if it is thinner than 30 μm, the structure becomes excessively fine and the wiring substrate 900 This is because there may be a possibility of inhibiting the production efficiency.

The capacitors 350a, 350b, and 350c each have a dielectric layer 330, a flat plate-shaped first electrode 310, and a second electrode 320. The first electrode 310 and the second electrode 320 are formed of flat rectangular conductors of the same size. The first electrode 310 and the second electrode 320 are shifted by a predetermined distance from each other in the planar direction of the electrode, and overlap with each other. The 1st electrode 310 and the 2nd electrode 320 are 0.2 mm-8 mm in length, 0.1 mm-8 mm in width, and 3 micrometers-15 micrometers in thickness, for example. The first electrode 310 and the second electrode 320 are made of copper.

The thickness of the dielectric layer 330 is 0.5 micrometer-10 micrometers, for example. This is because if the thickness of the dielectric layer 330 is smaller than 0.5 mu m, the insulation resistance of the capacitor may deteriorate. On the other hand, if the thickness of the dielectric layer 330 is larger than 10 mu m, the capacitor may not be a value that can satisfy the high capacity of the capacitor.

The distance between the capacitors 350, for example, the distance between the second electrode 320 of the capacitor 350a and the first electrode 310 of the capacitor 350b (that is, the thickness of the adhesive layer formed by the adhesive 340). ) Is 2 to 12 µm, for example. This is because if it is smaller than 2 µm, the amount of the adhesive 340 filled between the capacitors 350 becomes insufficient, and the adhesive force between the capacitors 350 may be weakened. This is because, if the thickness of the adhesive 340 is thin, there is a possibility that the insulation resistance becomes small between the capacitors (between 350a and 350b or between 350b and 350c). On the other hand, when larger than 12 micrometers, since the thickness of the capacitor | condenser laminated body 450 increases, there exists a possibility that the fine wiring structure of the wiring board 900 may be inhibited.

The dielectric layer 330 is a dielectric layer made of ceramic. The dielectric layer 330 is formed of, for example, barium titanate (BaTiO ₃ ). As the dielectric layer 330, one containing a dielectric filler in a thermoplastic resin or a thermosetting resin can be used. As a thermoplastic resin, a polyester, for example, a thermosetting resin can use a phenol resin, for example. The dielectric filler is formed of, for example, strontium titanate (SrTiO ₃ ).

The via conductor 411 electrically connects the first electrodes 310 of the capacitors 350a, 350b, and 350c to each other. In addition, the via conductor 412 electrically connects the second electrodes 320 of the capacitors 350a, 350b, and 350c to each other.

A plurality of conductor patterns (conductor circuits) 421 (421P, 421G, 421S) are formed on the base substrate 100, and a plurality of conductor patterns 423 (423P, 423G,) on the second resin insulating layer 200b. 423S)). A plurality of conductor patterns 425 (425P, 425G, 425S) are formed on the third resin insulating layer 200c.

The via conductor 411 electrically connects the conductor pattern 421P and the conductor pattern 423P. The via conductor 412 electrically connects the conductor pattern 421G and the conductor pattern 423G. The conductor pattern 423G connected to the via conductor 412 is connected to the ground line, and the conductor pattern 423P connected to the via conductor 411 is connected to the power supply line. The via conductor 441P electrically connects the conductor pattern 423P and the conductor pattern 425P. The via conductor 441G electrically connects the conductor pattern 423G and the conductor pattern 425G.

The thickness of the base substrate 100 is 200 micrometers-800 micrometers. The base substrate 100 is made of glass epoxy resin, for example. Glass epoxy resin is the glass cloth impregnated with the epoxy resin to which the glass filler was added (glass epoxy substrate).

The thickness of the 1st resin insulating layer 200a, the 2nd resin insulating layer 200b, and the 3rd resin insulating layer 200c is 40 micrometers-120 micrometers, for example. The resin insulating layers 200a, 200b, and 200c are made of thermosetting resin such as epoxy resin, for example. The resin insulating layers 200a, 200b, and 200c may be made of inorganic particles such as glass, alumina, barium carbonate, and thermosetting resin. In the glass epoxy substrate, a glass epoxy substrate in which two pieces of glass cloth are stacked may be used.

The wiring board 900 can perform various electric signal processing, such as transmitting an electric signal through the conductor pattern 421S etc., for example.

In addition, since the capacitor laminate 450 is formed in the first resin insulating layer 200a, the wiring board 900 can decouple the noise while achieving space saving.

In addition, since a capacitor can be formed in the vicinity of the IC chip mounted on the wiring board 900, the delay of supplying power to the IC can be prevented.

In addition, the capacitor stack 450 built in the first resin insulating layer 200a is a stack of capacitors 350. Therefore, by maintaining the thickness of the dielectric layer 330 of each capacitor 350 to a predetermined thickness, the plurality of capacitors 350 are laminated while maintaining the insulation resistance value of each capacitor 350 to a certain degree. Therefore, it is possible to achieve an increase in the capacitor capacity as a whole of the capacitor stack 450. Therefore, it is possible to make both the capacitance of the capacitor high and the insulation of the capacitor high.

In addition, the capacitor 350 is formed by the first electrode 310 having a flat plate shape, the second electrode 320 at a position shifted from the first electrode 310 in the plane direction of the electrode, and the dielectric layer 330. Doing. As described above, since the first electrode 310 and the second electrode 320 of each capacitor 350 are alternately formed, the first electrodes 310 of the capacitors 350a, 350b, and 350c are electrically connected to each other. It is easy to form the via conductor 412 which electrically connects the via conductor 411 and the 2nd electrode 320 mutually connected. Therefore, since the via conductor does not have to be formed in the region where the first electrode 310 and the second electrode 320 face each other, the electrode area can be increased and the capacitor can be increased in capacity. Furthermore, since the number of via conductors penetrating the electrodes of the capacitor can be reduced, crack generation to the dielectric layer due to thermal expansion of the via conductor can be suppressed as much as possible.

In addition, the capacitor stack 450 is formed by stacking the capacitor 350. Therefore, in forming the capacitor | condenser laminated body 450, the insulation resistance value of each capacitor 350 can be examined beforehand, and only the capacitor | condenser 350 of the good quality with favorable insulation resistance can be selected and laminated | stacked. Therefore, a good thing can also be obtained as a whole of the capacitor | condenser laminated body 450, and the insulation reliability of the capacitor laminated body 450 can be ensured. If the capacitor laminate is formed by alternately stacking the electrode and the dielectric layer, it is difficult to check whether the insulation resistance of each capacitor portion is good in advance. Therefore, it is difficult to ensure the insulation reliability of a capacitor | condenser laminated body at a manufacturing stage.

The capacitor laminate 450 embedded in the resin insulating layer 200a is laminated with the capacitor 350 via an adhesive 340 such as resin. The coefficient of thermal expansion of the resin used for the adhesive 340 and the coefficient of thermal expansion of the resin insulating layer 200a may be made of the same material. Therefore, the coefficient of thermal expansion of the entire capacitor laminate 450 is determined by the resin insulating layer ( The thermal expansion coefficient of 200a) can be approximated. Therefore, even if heat is applied to the capacitor stack 450, the possibility of cracking at the interface between the resin insulating layer 200a and the capacitor stack 450 is low. For this reason, cracks are less likely to occur in the dielectric layer 330.

<The manufacturing method of the wiring board which concerns on 1st Embodiment of this invention>

First, the high electrode material made of BaTiO ₃ is printed on a first electrode 310 made of copper having a thickness of 5 μm using a printing machine such as a doctor blade to form a thin film having a thickness of 5 to 10 μm to form an unbaked layer. . In addition, in order to form a thinner dielectric layer (0.5-5 micrometers), the sol-gel method, sputtering method, etc. which are mentioned later can be used.

Next, the unbaked layer is baked in a non-oxidizing atmosphere such as vacuum or N ₂ gas at a temperature range of 600 to 950 ° C. to obtain the dielectric layer 330. Thereafter, a metal layer made of copper is formed on the dielectric layer 330 using a vacuum deposition apparatus such as a sputter, and the second electrode 320 is formed by adding about 5 μm of copper on the metal layer by electroplating or the like. do. In this way, as shown in FIG. 2A, a capacitor is obtained which sandwiches the dielectric layer 330 formed of BaTiO ₃ between the first electrode 310 and the second electrode 320 made of copper.

Next, as shown in FIG. 2B, the first electrode 310 is removed by removing the necessary portions of the first electrode 310 and the second electrode 320 by an etching process using a cupric chloride etching solution. ) And the second electrode 320 are formed to be in a position shifted in the plane direction (ie, the horizontal direction) to form a single unit of the capacitor 350. In this case, the overlap between the first electrode 310 and the second electrode 320 above and below the dielectric layer 330 is about 0.4 to 1.0 cm 2, so that the first electrode 310 and the second electrode 320 are in a horizontal direction. To shift. In addition, the alignment mark 710 is formed in the 1st electrode 310 by the etching process, and the alignment mark 720 is formed in the 2nd electrode 320 further.

Next, as shown in Fig. 2C, three capacitors 350a, 350b and 350c are laminated in the vertical direction. When the capacitors 350a, 350b, and 350c are laminated, an epoxy resin as an adhesive is interposed between the capacitors 350. The single capacitors 350a, 350b, and 350c are aligned with respect to the alignment mark 710 or the alignment mark 720 formed in each capacitor.

As shown in FIG. 2D, the capacitor stack 450 is obtained with the three capacitors 350a, 350b, 350c interposed between the capacitors with the adhesive 340.

Next, as shown in FIG. 2E, on the base substrate (core substrate) 100 on which the alignment mark 730 is formed, a thermosetting resin film is used at a temperature of 50 to 170 ° C. and a pressure of 0.4 to 50 ° C. using a vacuum laminator. Adhesion is carried out under a laminate condition of 1.5 MPa. Conductor patterns 421 (421P, 421G, and 421S) are formed on the base substrate 100. The base substrate 100 is a glass epoxy substrate having a thickness of 0.6 mm. Although the thermosetting resin film at the time of sticking is a semi-cured state, it becomes a 1st resin insulating layer (lower resin insulating layer) 200a by hardening. As a resin film, two sheets of ABF-45SH by Ajinomoto Co., Ltd. can be used, for example.

Next, as shown in FIG. 2F, the capacitor laminate 450 is positioned and laminated on the first resin insulating layer 200a in a semi-cured state. Positioning of both is performed by recognizing the alignment mark 710 in the capacitor 350a and the alignment mark 730 of the base substrate 100 among the capacitor stack 450. Alternatively, the alignment mark 720 in the capacitor 350c and the alignment mark 730 of the base substrate 100 are recognized by the camera in the capacitor stack 450. Only one of the alignment marks 710 and the alignment marks 720 may be formed, or both may be formed.

After that, as shown in FIG. 2G, the vacuum press is performed under a press condition of 0.4 MPa, 170 ° C. for 2 hours, and the capacitor laminate 450 is embedded in the first resin insulating layer 200a, and the first is pressed. The resin insulating layer 200a is cured. The capacitor laminate 450 is embedded in the first resin insulating layer 200a so that the upper surface of the capacitor laminate 450 and the upper surface of the first resin insulating layer 200a are the same surface.

In addition, as shown in FIG. 2H, the capacitor laminate may be laminated on the first resin insulating layer 200a in a state where a part of the capacitor 350c is embedded. Even in this case, the alignment mark 720 formed on the capacitor 350c of the capacitor stack 450 or the alignment mark 710 formed on the capacitor 350a, and the alignment mark 730 formed on the base substrate 100, A cover for positioning the capacitor stack 450 and the first resin insulating layer 200a.

Next, as shown in FIG. 2I, the resin film is laminated on the first resin insulating layer 200a and the capacitor laminate 450 using a vacuum laminator under a temperature of 50 to 170 ° C. and a pressure of 0.4 to 1.5 MPa. Stick. As the resin film, ABF-45SH manufactured by Ajinomoto Co., Ltd. can be used. Thereafter, the resin film is cured by heat treatment at 170 ° C. for 2 hours to form a second resin insulating layer (upper resin insulating layer) 200b.

Next, as shown in FIG. 2J, the base substrate 100 is penetrated through the second resin insulating layer 200b, the first resin insulating layer 200a, and the capacitor laminate 450 by a carbon dioxide laser. Through-holes 470 (470P, 470G, 470S) reaching the above conductor pattern 421 (power conductor pattern 421P, ground conductor pattern 421G, signal conductor pattern 421S) are formed.

The through hole 470P is a power supply through hole that reaches the power conductor pattern 421P. The through hole 470G is a ground through hole that reaches the ground conductor pattern 421G. The diameter of the through holes 470 (470P, 470G, 470S) is 20 to 100 µm. The through holes 470 (470P, 470G, 470S) can also be formed by a drill, not a carbon dioxide gas laser. Here, the position of the through hole 470 (470P, 470G, 470S) is the alignment mark 730 of the base substrate 100, the alignment mark 710 of the capacitor 350a in the capacitor stack 450, and the capacitor. It is determined by recognizing any one of the alignment marks 720 of the capacitor 350c in the laminated body 450 with a camera or X-rays.

As shown in FIGS. 2K and 2L, which are plan views, a capacitor is formed at an overlapping portion of the first electrode 310 and the second electrode 320. As shown in FIG. 2K, the first electrode 310 and the second electrode 320 may be shifted only in the lateral direction, and as shown in FIG. 2L, the first electrode 310 and the second electrode may be shifted. The electrode 320 can also be shifted in the transverse direction and the longitudinal direction. In addition, the part where the 1st electrode 310 and the 2nd electrode 320 overlap is shown with the diagonal line. The first electrode 310 and the second electrode 320 are shifted in parallel to each other in the plane direction, and portions which do not overlap exist. The through holes 470P and 470G are formed in the part which does not overlap. As described above, since the through holes 470P and 470G are not formed in the portion where the first electrode 310 and the second electrode 320 face each other, the first electrode 310 and the second electrode 320 are not formed. The opposing area can be enlarged. The power supply through hole 470P is in contact with the first electrode 310 (power supply electrode), but is not in contact with the second electrode 320 (ground electrode). The ground through hole 470G is in contact with the second electrode 320 but is not in contact with the first electrode 310.

As shown in Fig. 2J, in addition to the through holes 470P and 470G, signal through holes 470S reaching the signal conductor pattern are formed. The signal through hole 470S is formed in a region where the capacitor stack 450 does not exist.

Next, surface treatment with a catalyst is performed on the surface of the second resin insulating layer 200b.

Next, an electroless plating film (electroless copper plating film) is formed on the surface of the second resin insulating layer 200b and the inner wall surfaces of the through holes 470P, 470G, and 470S. Thereafter, an electrolytic plating film (electrolytic copper plating film) is formed on the electroless plating film. Subsequently, an etching resist is formed on an electroplating film. Thereafter, the etching resist is patterned through the exposure and development steps. Moreover, the photolithographic method which covers the part which forms the pattern on a resin layer, and the part which protects through-hole plating with a resist in this way is called a tenting method. Then, by etching away the electrolytic plating film and the electroless plating film of the portion where the etching resist is not formed, as shown in Fig. 2M, the conductor pattern 423 (power supply pattern 423P, grounding conductor pattern 423G). ), The signal conductor pattern 423S) and the via conductors 411, 412, and 413 are formed.

The via conductor 411 is a via conductor for a power supply, and as shown in FIG. 2M, the capacitor 350a, the capacitor 350b, and the first electrodes 310 of the capacitor 350c are electrically connected to each other. In addition, the via conductor 412 is a ground via conductor, and as shown in FIG. 2M, the second electrodes 320 of the capacitor 350a, the capacitor 350b, and the capacitor 350c are electrically connected to each other. .

The power supply via conductor 411 connects the power supply conductor pattern 421P on the base substrate 100 with the power supply conductor pattern 423P on the second resin insulating layer 200b. The ground via conductor 412 connects the ground conductor pattern 421G on the base substrate 100 and the ground conductor pattern 423G on the second resin insulating layer 200b.

Next, as shown in FIG. 2N, a third resin insulating layer 200c is formed on the second resin insulating layer 200b and the conductor patterns 423 (423P, 423G, and 423S). The material of the third resin insulating layer 200c is the same as that of the second resin insulating layer 200b and the first resin insulating layer 200a.

Next, a through hole is formed in the third resin insulating layer 200c by a carbon dioxide gas laser. The through hole can also be formed by a drill.

Next, surface treatment with a catalyst is performed on the surface of the third resin insulating layer 200c. After surface treatment with a catalyst, an electroless plated film is formed on the surface of the substrate. Thereafter, a plating resist is formed on the electroless plating film. Subsequently, the plating resist is exposed and developed to pattern the plating resist. Then, an electroplating film is formed in the non-forming region of the plating resist. After the plating resist is peeled off, the electroless plating film between the electroplating films is removed, so that the outermost conductor pattern 425 made of the electroless plating film and the electroplating film formed on the electroless plating film as shown in FIG. 2O. ) (The outermost conductor pattern 425P, the outermost ground conductor pattern 425G, and the outermost signal conductor pattern 425S) are formed.

Next, a solder resist 700 is formed on the third resin insulating layer 200c and the outermost conductor patterns 425 (425P, 425G, 425S). Thereafter, as shown in FIG. 2P, an opening is formed in the solder resist 700 to expose a portion of the conductor patterns 425 (425P, 425G, and 425S) to form a pad 427 (pad for power supply (first external terminal). 427P), a ground pad (second external terminal) 427G, and a signal pad 427S. The part exposed by the opening portion becomes the pads 427 (427P, 427G, 427S).

As shown in FIG. 2P, the first electrode 310 and the power pad 427P are connected via the via conductor 411, the conductor pattern 423P, and the via conductor 441P. The second electrode 320 and the ground pad 427G are connected via the via conductor 412, the conductor pattern 423G, and the via conductor 441G.

Next, a corrosion resistant metal film was formed on the pads 427 (427P, 427G, and 427S). As a metal film, the film which consists of Ni, Au, Pd, Ag, Pt etc. can be formed, for example. In this embodiment, Ni films, Pd films, and Au films are formed in this order. In addition, one layer of a metal film may be sufficient, and it may consist of a some metal film. For example, it can form in order of a Ni film and Au film on a pad.

Next, a solder paste is printed on the metal film. Thereafter, by reflowing to form the solder bumps 429, the wiring board 900 shown in FIG. 1 can be obtained.

When the IC chip 800 is mounted, as shown in FIG. 2Q, the IC chip 800 is mounted through the solder bumps 429.

In addition, in this embodiment, the resin insulating layer, the conductor pattern, and the via conductor are formed only on one side of the base substrate 100, but as shown in FIG. 2R, the resin insulating layer and the conductor are formed on both sides of the base substrate 100. It is also possible to form patterns and via conductors.

In addition, it is preferable to roughen the surface of the resin insulating layers 200a, 200b, and 200c, the surface of the conductor patterns 421, 423, and 425, the surface of the first electrode 310, and the surface of the second electrode 320. Do. In addition, when mounting the IC chip 800 on the surface of the wiring board 900, it is preferable to close the distance between the capacitor stack 450 and the IC chip 800.

<2nd embodiment of the wiring board in one specific embodiment of this invention>

In the first embodiment, the resin insulating layer 200 was formed of the first resin insulating layer 200a, the second resin insulating layer 200b, and the third resin insulating layer 200c. As shown in FIG. 3, the wiring board 900 according to the second embodiment differs from the first embodiment in that the resin insulating layer 200 includes the first resin insulating layer 200a and the second resin insulating layer ( 200b).

The electrode located on the uppermost layer of the capacitor stack 450 is formed by integrating the first electrode 310 of the capacitor 350a and the power conductor pattern 423P on the first electrode 310. . Therefore, in the wiring board 900 which concerns on 2nd Embodiment, the thickness of the electrode in the surface layer of the capacitor laminated body 450 is thicker than the wiring board 900 which concerns on 1st Embodiment. Therefore, the rigidity of the capacitor stack 450 is increased. Therefore, cracks are less likely to occur in the dielectric layer of the capacitor stack 450.

As shown in FIG. 3, the power supply pad (first external terminal) 427P and the first electrodes 310 of the capacitors 350a, 350b, and 350c include the via conductor 441P and the conductor pattern 423P. It is electrically connected via the via conductor 411. The ground pad (second external terminal) 427G and the second electrodes 320 of the capacitors 350a, 350b, and 350c are connected via the via conductor 441G, the conductor pattern 423G, and the via conductor 412. It is electrically connected.

On the second resin insulating layer 200b, an outermost power conductor pattern 425P, an outermost ground conductor pattern 425G, and an outermost signal conductor pattern 425S are formed.

An opening is formed in the solder resist 700 to expose a part of the conductor patterns 425 (425P, 425G, and 425S) to form a pad 427 (power pad (first external terminal) 427P) and a ground pad (made of 2 external terminals) 427G and signal pads 427S are formed.

<The manufacturing method of the wiring board which concerns on 2nd Embodiment of this invention>

Next, another manufacturing method of the wiring board which concerns on 2nd Embodiment is shown.

First, from FIG. 2A to FIG. 2G, it is the same as the manufacturing method of the wiring board mentioned above.

Next, as shown in FIG. 4A, the substrate manufactured in the process up to FIG. 2G is provided with a through hole 470 (through hole 470P reaching the conductor pattern for power supply on the core substrate, and ground on the core substrate). A through hole 470G reaching the conductive conductor pattern and a through hole 470S reaching the signal conductor pattern on the core substrate are formed. In the manufacturing method according to the first embodiment, through holes are also formed in the second resin insulating layer 200b at the same time. In the manufacturing method according to the present embodiment, the capacitor laminate 450 and the first resin insulating layer 200a are used. Since only the through hole penetrating the hole is formed, the hole processing becomes easy and the yield is improved. Then, a surface treatment is performed with a catalyst on the surface of the first resin insulating layer 200a on which the through holes 470 are formed.

Next, as shown in Fig. 4B, the ground via conductor 412, the power via via 411, the signal via conductor 413, and the conductor pattern 423 (power supply conductor pattern 423P) by the tenting method. , The ground conductor pattern 423G, and the signal conductor pattern 423S.

As shown in FIG. 4B, the first electrode 310 of the capacitor 350a and the power supply conductor pattern 423P on the first electrode 310 of the electrode disposed on the uppermost layer of the capacitor stack 450 are formed. It is formed integrally. Here, the electrode located on the uppermost layer of the capacitor stack 450 is an electrode on the surface layer of the capacitor stack 450 located on the side closer to the IC chip 800 to be mounted. The conductor pattern 423P for power supply on the first electrode 310 is formed of an electroless plating film and an electrolytic plating film on the electroless plating film.

The via conductor 412 connects the capacitor 350a, the capacitor 350b, and the second electrodes 320 of the capacitor 350c to each other. The via conductor 412 connects the ground conductor pattern 421G on the base substrate 100 and the ground conductor pattern 423G on the first resin insulating layer 200a.

The via conductor 411 connects the capacitor 350a, the capacitor 350b, and the first electrodes 310 of the capacitor 350c to each other. The via conductor 411 connects the power supply conductor pattern 421P on the base substrate 100 with the power supply conductor pattern 423P on the first resin insulating layer 200a.

Next, as shown in FIG. 4C, the second resin insulating layer 200b is formed on the first resin insulating layer 200a, the capacitor stack 450, and the conductor patterns 423 (423P, 423G, and 423S). do. Then, a through hole is formed in the second resin insulating layer 200b. And a surface treatment is performed with a catalyst on the surface of the board | substrate which provided the through hole.

After surface treatment with a catalyst, an electroless plated film is formed on the surface of the substrate. Thereafter, a plating resist is formed on the electroless plating film. Subsequently, the plating resist is exposed and developed to pattern the plating resist. Then, an electroplating film is formed in the non-forming region of the plating resist. After the plating resist is peeled off, the electroless plating film between the electroplating films is removed, thereby forming a conductor pattern 425 (425P, 425G, 425S) consisting of the electroless plating film and the electroplating film on the electroless plating film. Next, similarly to the first embodiment, the wiring resist 900 shown in FIG. 3 is obtained by forming the solder resist 700, the pad 427, and the solder bumps 429.

According to the manufacturing method of the wiring board which concerns on this embodiment, since one resin insulation layer can be manufactured less compared with 1st embodiment, it is possible to manufacture the wiring board 900 at low cost.

In addition, in the above-described embodiment, the resin insulating layer, the conductor pattern, and the via conductor are formed only on one side of the base substrate 100, but as shown in FIG. 4D, the resin insulating layers, It is also possible to form conductor patterns and via conductors.

<3rd embodiment of the wiring board in one specific embodiment of this invention>

5 shows a third embodiment of the present invention. In the third embodiment, unlike the first embodiment, the first electrode 310 and the second electrode 320 are not shifted from each other in the plane direction of the electrode. A plurality of first openings 311 are formed in the first electrode 310, and a plurality of second openings 322 are formed in the second electrode 320.

The plurality of first via conductors 411 electrically connect the first electrodes 310 to each other while passing the second opening portion 322 through the second electrode 320 in a non-contact manner. In addition, the plurality of second via conductors 412 electrically connect the second electrodes 320 to each other while penetrating the first opening 311 through the first electrode 310 in a non-contact manner.

In this manner, the plurality of first via conductors 411 and the plurality of second via conductors 412 penetrate the capacitor stack 450. Therefore, in the wiring board 900 which concerns on 3rd Embodiment, the some 1st via conductor 411 and the some 2nd via conductor 412 can suppress the deformation | transformation of the adhesive agent 340, and the capacitor The crack resistance of the laminated body 450 is easy to improve.

That is, when the thermal expansion coefficients of the dielectric layers 330 of the capacitors 350a, 350b, and 350c and the adhesive 340 bonding the capacitors 350a, 350b, and 350c are different from each other, the capacitor stack 450 has a temperature. When the change is received, forces such as bending, warping, and bending are applied to the dielectric layer 330. Under such a force, the ceramic dielectric layer 330 is thin and fragile, so that cracks are likely to occur. However, in the present embodiment, the plurality of first via conductors 411 and the plurality of second via conductors 412 penetrate the capacitor stack 450 to physically connect the capacitors 350a, 350b, 350c. Since it prevents that, the deformation | transformation of the adhesive agent 340 can be suppressed. As a result, forces such as bending, distortion, and bending acting on the dielectric layer 330 are reduced.

As shown in Figs. 6A and 6B, the power via conductor 411 and the ground via conductor 412 are preferably arranged in a lattice shape or a zigzag shape. The spacing between adjacent power supply via conductors 411 is approximately equal. The spacing between adjacent ground via conductors 412 is approximately equal.

<The manufacturing method of the wiring board which concerns on 3rd embodiment of this invention>

First, as shown in FIG. 7A, a capacitor including a first electrode 310, a second electrode 320, and a dielectric layer 330 sandwiched between the first electrode 310 and the second electrode 320 ( 350). The capacitor 350 is created in the same manner as in the first embodiment.

Next, as shown in FIG. 7B, FIG. 7C which is a plan view of the capacitor 350 from the first electrode 310 side, and FIG. 7D which is a plan view of the capacitor 350 from the second electrode 320 side, The first electrode 310 and the second electrode 320 are patterned. At this time, alignment marks 710 and 720 are also formed.

An opening 311 is formed in the first electrode 310, and a ground via conductor 412 is formed in the opening 311. The first electrode 310 and the ground via conductor 412 are noncontact. An opening 322 is formed in the second electrode 320, and a via conductor 411 for a power source is formed in the opening 322. The second electrode 320 and the via via conductor 411 for power are non-contact.

Next, as shown in FIG. 7E, three sets of capacitors 350 obtained in the previous step are prepared and laminated through the adhesive 340. The capacitors 350a, 350b, 350c are positioned based on the alignment marks 710, 720 of each capacitor 350.

Next, as shown in FIG. 7F, the capacitor stack 450 made of the capacitors 350a, 350b, 350c and the adhesive 340 disposed between the capacitors is prepared. The capacitor laminate 450 is produced by a vacuum press. The conditions of a vacuum press are the temperature of 50-170 degreeC, and a pressure of 0.4-1.5 Mpa.

The opening 311 of each capacitor constituting the capacitor stack 450 is shorted by the via conductor 412 penetrating through the capacitor stack 450 and the first electrode 310 and the second electrode 320 are short-circuited. In order not to be, it is formed in substantially the same position in a cross-sectional direction. That is, as shown in FIG. 7F, the openings 311 formed in the capacitors 350a, 350b, and 350c are formed at positions overlapped in the cross-sectional direction.

The opening 322 of each capacitor constituting the capacitor stack 450 is shorted by the via conductor 411 penetrating the capacitor stack 450 so that the first electrode 310 and the second electrode 320 are short-circuited. In order not to be, it is formed in substantially the same position in a cross-sectional direction. That is, in FIG. 7F, the openings 322 formed in the capacitors 350a, 350b, and 350c are formed at positions overlapped in the cross-sectional direction.

Next, as shown in FIG. 7G, the capacitor laminate 450 is embedded in the first resin insulating layer 200a.

Next, as shown in Fig. 7H, through holes 470 (470P, 470G, 470S) are formed. The through holes 470 (470P, 470G, and 470S) penetrate the capacitor stack 450 and the first resin insulating layer 200a, and the conductor patterns 421 (421P, 421G, and 421S) of the base substrate 100 are used. Is reaching. The formation position of the through hole 470 (470P, 470G, 470S) is in any one of the alignment mark 730 of the base substrate 100, and the alignment mark 710, 720 formed in the condenser laminated body 450. It forms by laser processing on the basis.

The power supply through hole 470P penetrates through the first electrode 310 and the dielectric layer 330. In addition, the power supply through hole 470P is formed in the opening 322 of the second electrode 320 and is not in contact with the inner wall of the opening 322.

The ground through hole 470G penetrates through the second electrode 320 and the dielectric layer 330. In addition, the ground through hole 470G is formed in the opening 311 of the first electrode 310 and is not in contact with the inner wall of the opening 311.

Next, as shown in Fig. 7I, the ground via conductor 412, the power via conductor 411, the signal via conductor 413, the conductor pattern 423 (power conductor pattern 423P), the ground conductor. Pattern 423G and signal conductor pattern 423S are formed by a tenting method. The conductor pattern 423 (power conductor pattern 423P, ground conductor pattern 423G, signal conductor pattern 423S) is composed of an electroless plating film and an electrolytic plating film on the electroless plating film.

The electrode of the uppermost layer of the capacitor stack 450 is formed on the first electrode 310 of the capacitor 350a and the conductor pattern 423P (the first electrode 310) on the power supply and on the electroless plating film. Electrolytic plating film) is formed integrally. The electrode of the uppermost layer of the capacitor stack 450 is an electrode of the surface layer of the capacitor stack 450 located on the side close to the IC chip to be mounted.

Next, after the via conductor and the conductor pattern are formed, the wiring substrate 900 as shown in FIG. 5 is obtained through the steps shown in FIGS. 4C and 4D.

<4th embodiment of the wiring board in one specific embodiment of this invention>

The wiring board 900 concerning 4th Embodiment of this invention is shown in FIG. In the wiring board 900 according to the fourth embodiment, unlike the wiring board 900 according to the first embodiment, a base substrate (core substrate) 100 having a core material such as glass cloth or glass fiber is formed. Not. Therefore, all the insulating layers can be made into a resin insulating layer (resin film). Therefore, the capacitor embedded substrate can be made thin. According to the wiring board 900 which concerns on 4th Embodiment, the chip capacitor mounted on the surface of the wiring board 900 and the distance between the external power supply and the capacitor laminated body 450 built in the wiring board 900 is included. (Not shown) and the distance between the capacitor | condenser laminated body 450 can be shortened.

<The manufacturing method of the wiring board which concerns on 4th embodiment of this invention>

First, as shown in FIG. 9A, the support plate 150 is prepared. The support plate 150 is a copper plate, for example. In addition, the material of the support plate 150 can use metal plates, such as a nickel plate, an aluminum plate, and an iron plate, in addition to a copper plate.

Next, as shown in FIG. 9B, the plating resist 160 is formed on the support plate 150.

Next, as shown in FIG. 9C, a plurality of openings are formed in the plating resist 160 by patterning the plating resist 160 by performing an exposure and development process.

Next, as shown in FIG. 9D, electrolytic plating is performed in the order of the gold plating film 911, the nickel plating film 912, and the copper plating film 913 in the openings of the formed plating resist 160. 1 External connection terminal 600 (external terminal (first external terminal) 600P for power supply, external terminal (second external terminal) 600G for ground, and external signal terminal 600S) for signals are formed. At the same time, an alignment mark (first alignment mark) 621 is formed on the support plate 150. It is also possible to form a palladium film between the gold plating film 911 and the nickel plating film 912.

Next, as shown in FIG. 9E, the plating resist 160 is peeled off, and a resin film (first lower resin insulating layer) 400d is formed. This first lower resin insulating layer (lowest layer resin insulating) 400d is located below the first resin insulating layer 400a in which the capacitor laminate 450 is incorporated, as shown in FIG. 8. As shown in Fig. 9E, the first external connection terminal 600 (600P, 600G, 600S) has a bottom surface resin insulating layer (first lower resin) having a first surface and a second surface opposite to the first surface. Insulation layer). In addition, the surface of the 1st external connection terminal 600 is located in substantially the same plane as the 1st surface of the resin insulating layer of the lowest layer.

Next, as shown in FIG. 9F, a through hole reaching the first external connection terminal 600 (600P, 600G, 600S) is formed in the first lower resin insulating layer 400d.

Next, as shown in Fig. 9G, the first conductor pattern (on the surface opposite to the surface on which the external terminals are formed) of the first lower resin insulating layer 400d is formed by the semi-additive method. 610 (the first conductor pattern 610P for power supply, the first conductor pattern 610G for ground, and the first conductor pattern 610S for signal) are formed.

At the same time, the first via conductor 611 (the first via conductor 611P for power supply) connecting the first external connection terminal 600 (600P, 600G, 600S) and the first conductor pattern 610 (610P, 610G, 610S). ), A ground first via conductor 611G, and a signal first via conductor 611S. At this time, the second alignment mark 622 is also formed at the same time.

The first via conductor 611P for power supply connects the external terminal 600P for power supply (the first external terminal for power supply) and the first conductor pattern 610P for power supply on the first surface side. The ground first via conductor 611G (ground first external terminal) connects the ground external terminal 600G on the first surface side with the ground first conductor pattern 610G. The signal first via conductor 611S (signal first external terminal) connects the signal external terminal 600S on the first surface side with the signal first conductor pattern 610S.

Next, as shown in FIG. 9H, the first surface on the first conductor pattern 610 (610P, 610G, and 610S) and the first lower resin insulating layer 400d is opposite to the first surface and the first surface. A resin film (first resin insulating layer 400a) having a film is formed. In formation of the 1st resin insulating layer 400a, two sheets of ABF-45SH by Ajinomoto Co., Ltd. can be piled up and laminated, for example. The first surface of the first resin insulating layer 400a is laminated on the second surface of the first lower resin insulating layer 400d.

Next, as shown in FIG. 9I, the capacitor laminate 450 is positioned and laminated on the first resin insulating layer 400a. The stacking position of the capacitor stack 450 may be determined using, for example, the second alignment mark 622 formed on the first resin insulating layer 400a and the alignment mark 720 of the capacitor stack 450. . In addition, the capacitor | condenser laminated body 450 can be formed by the manufacturing method similar to 1st Embodiment.

Next, as shown in FIG. 9J, the capacitor laminate 450 is embedded in the second surface side of the first resin insulating layer 400a. The surface of the first electrode 310 of the capacitor 350a and the second surface of the first resin insulating layer 400a are located on substantially the same plane. The embedding method of the capacitor stack 450 is the same as the method described with reference to FIG. 2G.

Next, as shown in Fig. 9K, a through hole is formed.

Next, as shown in FIG. 9L, the via conductor (second via conductor) 651 (the second via conductor 651P for power supply, the second via conductor 651G for ground, and the second via conductor 651S for signal). ). In addition, a second conductor pattern 650 (second conductor pattern 650P for power supply, second conductor pattern 650G for ground, and second conductor pattern 650S for signal) is prepared.

The second via conductor 651P for the power supply connects the first electrodes 310 of the capacitors 350a, 350b, 350c of the capacitor stack 450. The via conductor 651P connects the second conductor pattern 650P for power supply and the first conductor pattern 610P for power supply.

The ground second via conductor 651G connects the second electrodes 320 of the capacitors 350a, 350b, and 350c of the capacitor stack 450. The via conductor 651G connects the second conductor pattern 650G for ground and the first conductor pattern 610G for ground.

The signal second via conductor 651S connects the signal second conductor pattern 650S and the signal first conductor pattern 610S.

Through the first via conductor 611P, the conductor pattern 610P, and the via conductor 651P for the power supply, the first electrode 310 and the first external terminal 600P of each capacitor 350a, 350b, 350c are electrically connected to each other. Connected. In addition, the second electrode 320 and the second external terminal 600G of the capacitors 350a, 350b, and 350c are connected through the ground first via conductor 611G, the conductor pattern 610G, and the via conductor 651G. Is electrically connected.

Next, as shown in FIG. 9M, a resin film (second resin insulating layer) 400b is formed on the second conductor patterns 650 (650P, 650G, and 650S) and the first resin insulating layer 400a. .

Next, as shown in Fig. 9N, a through hole is formed in the second resin insulating layer (the resin insulating layer of the uppermost layer) 400b.

Next, as shown in FIG. 9O, on the second resin insulating layer 400b, a third conductor pattern 660 (the third conductor pattern 660P for power, the third conductor pattern 660G for ground, and the third for a signal) Conductor pattern 660S).

At the same time, the third via conductor 661 (the third via conductor 661P for the power supply) connecting the second conductor pattern 650 (650P, 650G, 650S) and the third conductor pattern 660 (660P, 660G, 660S). , The third via conductor 661G for ground and the third via conductor 661S for signal are formed.

The third via conductor 661P for the power supply connects the third conductor pattern 660P for the power supply and the second conductor pattern 650P for the power supply. The ground third via conductor 661G connects the ground third conductor pattern 660G with the ground second conductor pattern 650G. The signal third via conductor 661S connects the signal second conductor pattern 650S and the signal third conductor pattern 660S. These connections can be formed by a semi-additive process, for example.

Next, as shown in FIG. 9P, the soldering resist 700 is formed on the 2nd resin insulating layer 400b and the 3rd conductor pattern 660 (660P, 660G, 660S).

Next, as shown in FIG. 9Q, a plurality of openings are formed in the solder resist 700. The opening partially opens the third conductor pattern 660 (660P, 660G, 660S). The portion of the third conductor pattern 660 (660P, 660G, 660S) exposed by the opening becomes the second external connection terminal 670 (670P, 670G, 670S). The second external connection terminal 670 is formed on the second resin insulating layer (the resin insulating layer of the uppermost layer) 400b, and the second external connection terminal (third external terminal) 670P for the power supply and the second external for ground are provided. The connection terminal (fourth external terminal) 670G and the signal second external connection terminal 670S.

Next, the metal is formed of three layers by plating on the second external connection terminals 670 (670P, 670G, 670S) in the order of the nickel plating film 912, the palladium plating film 914, and the gold plating film 911. To form a film. The metal film may be one gold plated film, or may be a nickel plated film and two gold plated films on the nickel plated film.

Next, as shown in FIG. 9R, the support plate 150 is etched away with the cupric chloride etching solution. At this time, since the metal film is formed on the second external connection terminals 670 (670P, 670G, 670S) and the first external connection terminals 600 (600P, 600G, 600S), the external connection terminals are not etched away. Instead, the support plate 150 can be removed. By removing the support plate 150, the external terminal surface (exposed portion of the metal film) of the first external connection terminal 600 is exposed.

Thereafter, the second solder bumps and the first external connection terminals 600 (600P, 600G, 600S) are applied to the external terminal surfaces (exposed portions of the metal film) of the second external connection terminals 670 (670P, 670G, 670S). By forming the first solder bumps on the external terminal surface, the wiring board 900 shown in FIG. 8 is obtained.

In addition, electronic components such as an IC chip may be mounted through the first solder bumps. You may connect with another board | substrate (motherboard) via 2nd solder bump. In addition, although solder bumps are formed in the external terminal surface of the first external connection terminal 600 and the external terminal surface of the second external connection terminal 670 in FIG. 8, the external terminal surface of the second external connection terminal 670 is formed. The conductive bumps may be mounted (mounted) on the solder bumps and the external terminal surfaces of the first external connection terminals 600 via solder. A conductive bump may be mounted (mounted) on the external terminal surface of the first external connection terminal 600 via solder and on the external terminal surface of the second external connection terminal 670. Although the IC chip may be mounted on the upper surface side or the lower surface side of the wiring board, the IC chip is preferably mounted on the surface of the capacitor-embedded substrate on the side of which the distance from the external terminal to the capacitor (the distance in the cross-sectional direction of the substrate) is short. .

In this embodiment, although the resin insulation layer (resin film) is three layers, multilayering of four or more layers is possible by repeating the process of FIG. 9M to FIG. 9O.

Moreover, it is also possible to form the soldering resist which has an opening which exposes the 1st external connection terminals 600 (600P, 600G, 600S) on the lower surface of the 1st lower resin insulating layer 400d.

Unlike the wiring board 900 shown in FIG. 8, the wiring board 900 illustrated in FIG. 10 is an example in which the first external connection terminal 600 and the capacitor laminate 450 are embedded in the same resin insulating layer. to be. The wiring board 900 shown in FIG. 10 includes a first resin insulating layer (lowest resin insulating layer) 400a, a first surface, and a first surface having a first surface and a second surface opposite to the first surface. It is a two-layer structure of the 2nd resin insulating layer (resin insulation of uppermost layer) 400b which has a 2nd surface on the opposite side to a surface. The capacitor | condenser laminated body 450 is embedded in the 2nd surface side of the 1st resin insulating layer 400a. The surface of the first electrode 310 of the capacitor 350a and the second surface of the resin insulating layer 400a of the lowest layer are located on substantially the same plane. On the other hand, the 1st external connection terminal 600 is embedded in the 1st surface side (1st surface of the wiring board 900) of the 1st resin insulating layer 400a. The surface of the 1st external connection terminal 600 and the 1st surface of the resin insulating layer 400a of the lowest layer are located in substantially the same plane. The 1st surface of the resin insulating layer 400b of the uppermost layer is laminated | stacked on the 2nd surface of the resin insulating layer 400a of the lowest layer. On the second surface of the second resin insulating layer 400b, a second external connection terminal (third external terminal) 670P for the power supply, a second external connection terminal (fourth external terminal) 670G for ground, and a second external for signal The second external connection terminal 670 made of the connection terminal 670S is formed. In addition, a via conductor is formed in the second resin insulating layer 400b.

The manufacturing method of the wiring board 900 shown in this FIG. 10 first performs the process shown in FIGS. 9A-9E. Thereafter, the plating resist 160 is removed by performing the steps shown in FIGS. 9I to 9R, and the first solder bumps are formed in the first external connection terminals 600 (600P, 600G, and 600S), thereby FIG. 10. The wiring board 900 shown in the figure is obtained.

In addition, the wiring board of 4th Embodiment may contain the capacitor laminated body which laminated | stacked the capacitor | condenser by which the 1st electrode and the 2nd electrode did not shift in the surface direction similarly to 3rd Embodiment.

<5th embodiment of the wiring board in one specific embodiment of this invention>

Unlike the wiring board 900 according to the first embodiment, the wiring board 900 according to the fifth embodiment of the present invention has a resin insulating layer 200a on the base substrate 100 as shown in FIG. 11. The lower resin insulating layer 270d is formed below this. The capacitor stack 450a is embedded in the resin insulating layer 200a, and the capacitor stack 450b is embedded in the lower resin insulating layer 270d.

By configuring in this way, not only noise reduction on the base substrate 100 but also noise reduction can be efficiently aimed under the base substrate 100.

In the method of manufacturing the wiring board 900, for example, after FIG. 2Q, the lower resin insulating layer 270d is formed on the lower surface of the base substrate 100, and the capacitor laminate ( It is possible to create by embedding 450b).

<Other embodiments in the present invention>

In the above-described embodiment, the capacitor stack 450 is formed by stacking three capacitors 350a, 350b, and 350c, but is not limited thereto. The capacitor stack 450 may be laminated with, for example, two or four to thirty or more capacitors via the adhesive 340.

In the above embodiment, the dielectric layer 330 is formed of barium titanate (BaTiO ₃ ). However, it is not limited to this. The dielectric layer 330 is, for example, strontium titanate (SrTiO ₃ ), tantalum oxide (TaO ₃ , Ta ₂ O ₅ ), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), lead niobate zirconate titanate It is also possible to use any one or mixtures of (PNZT), lead calcium zirconate titanate (PCZT) and lead strontium zirconate titanate (PSZT).

In the above embodiment, strontium titanate (SrTiO ₃ ) was used as the dielectric filler. However, it is not limited to this. As the dielectric filler, for example, calcium titanate (CaTiO ₃ ), magnesium titanate (Mg ₂ TiO ₃ ), neodymium titanate (Nd ₂ Ti ₂ O ₇ ), or the like can be used.

In addition, in embodiment mentioned above, epoxy resin was used as resin which comprises a resin insulating layer (resin film). However, it is not limited to this. As the resin constituting the resin insulating layer, for example, polyimide, polycarbonate, modified polyphenylene ether, polyphenylene oxide, polybutylene terephthalate, polyacrylate, polysulfone, polyphenylene sulfide, polyether ether Ketones, polysulfones, polyethersulfones, polyphenylsulfones, polyphthalamides, polyamideimides, polyketones, polyacetals and the like can be used alone or in combination with epoxy resins.

In the above-described embodiment, copper was used as the metal for forming the first electrode 310 and the second electrode 320. However, it is not limited to this. As a metal which forms the 1st electrode 310 and the 2nd electrode 320, platinum, gold, nickel, tin, silver, etc. can be used individually or in mixture, for example. Furthermore, it is also possible to use different kinds of metals in the first electrode 310 and the second electrode 320, respectively.

In the above-described embodiment, the high dielectric material is printed on the first electrode 310 made of copper and fired to form the dielectric layer 330, and then the dielectric layer 330 using a vacuum deposition apparatus such as sputtering. ), A metal layer made of copper was formed to form a second electrode 320 to form a capacitor. However, it is not limited to this.

That is, it is also possible to create a capacitor by the following process. First, diethoxy barium and bitetriisopropoxide titanium are dissolved in a mixed solvent of dehydrated methanol and 2-methoxyethanol, and stirred for 3 days under a nitrogen atmosphere at room temperature to prepare a solution of an alkoxide precursor composition of barium and titanium. Adjust Subsequently, the precursor composition solution is stirred while maintaining at 0 ° C., and the pre-decarbonized water is hydrolyzed by spraying in a nitrogen stream at a rate of 0.5 μl / min. The precipitate or the like is filtered by passing the sol-gel solution thus prepared through a filter. The obtained filtrate is spin coated on a first electrode 310 made of copper having a thickness of 12 μm. Thereafter, the dielectric layer 330 is obtained by inserting into an electric furnace maintained at 850 ° C. and firing. The second electrode 320 can be obtained by forming a copper layer on the dielectric layer 330 using a vacuum deposition apparatus such as a sputter, and adding about 10 μm of copper on the copper layer by electroplating or the like.

This application is based on US Provisional Patent Application 60/980969, filed October 18, 2007. In the present specification, the specification, claims, and drawings are incorporated by reference.

INDUSTRIAL APPLICABILITY The present invention can be used for a wiring board in which a built-in capacitor has a high capacity and an insulation resistance is also secured.

Claims (25)

A capacitor stack formed by laminating a dielectric layer, a capacitor formed by opposing first and second electrodes with the dielectric layer interposed therebetween, using an adhesive; A first resin insulating layer containing the capacitor laminate; A base substrate for supporting the first resin insulating layer, A first via conductor electrically connecting the first electrodes to each other, A second via conductor electrically connecting the second electrodes to each other, A first external terminal electrically connected to the first via conductor; A second external terminal electrically connected to the second via conductor The wiring board which has a. The method of claim 1, The first electrode and the second electrode are arranged to be offset from each other in the surface direction of the electrode, The first via conductor electrically connects the first electrodes by passing through an end portion of the first electrode, The second via conductor electrically connects the second electrodes by passing through an end portion of the second electrode. A wiring board, characterized in that. The method of claim 1, An upper surface of the capacitor laminate is on an upper surface of the first resin insulating layer, and an upper surface of the capacitor laminate and an upper surface of the first resin insulating layer are the same surface. The method of claim 1, A wiring board further comprising a second resin insulating layer on the first resin insulating layer. The method of claim 4, wherein A conductor pattern is formed on the base substrate and on the second resin insulating layer. The via conductor is electrically connected to a conductor pattern on the base substrate and a conductor pattern on the second resin insulating layer. The method of claim 4, wherein A wiring board further comprising a third resin insulating layer on the second resin insulating layer. The method of claim 6, It has a conductor pattern on a said 2nd resin insulating layer, A wiring board having a conductor pattern on the third resin insulating layer. The method of claim 7, wherein A via board for electrically connecting the conductor pattern on the second resin insulating layer and the conductor pattern on the third resin insulating layer. The method of claim 3, A conductor pattern is formed on the base substrate and on the first resin insulating layer. The via conductor is electrically connected to a conductor pattern on the base substrate and a conductor pattern on the first resin insulating layer. The method of claim 9, A conductor pattern on the first resin insulating layer and a first electrode of the capacitor on the top surface of the capacitor stack are integrated to form an electrode. The method of claim 1, The first electrode has a plurality of first openings, The second electrode has a plurality of second openings, The first via conductor electrically connects the first electrodes to each other while penetrating the second opening without contacting the second electrode. The second via conductor electrically connects the second electrodes to each other while non-contacting the first opening with the first electrode. A wiring board, characterized in that. A plurality of resin insulating layers having at least the lowest resin insulating layer and the highest resin insulating layer; A plurality of conductor circuits formed between the resin insulating layers, A capacitor laminated body embedded in one resin insulating layer of the plurality of resin insulating layers, and formed by laminating a dielectric layer and a capacitor formed by opposing first and second electrodes with the dielectric layer interposed therebetween through an adhesive. Wow, A first via conductor electrically connecting the first electrodes to each other, A second via conductor electrically connecting the second electrodes to each other, A first external connection terminal formed on the lowest resin insulating layer, the first external terminal comprising a first external terminal electrically connected to the first via conductor, and a second external terminal electrically connected to the second via conductor; , A second external connection terminal formed on the resin insulating layer of the uppermost layer and having a third external terminal electrically connected to the first via conductor and a fourth external terminal electrically connected to the second via conductor; Has, The first external connection terminal is embedded in the resin insulating layer of the lowest layer, and the external terminal surface of the first external connection terminal is located on substantially the same plane as the first surface of the resin insulating layer of the lowest layer. The second external connection terminal is formed on the resin insulating layer of the uppermost layer. The method of claim 1, The said adhesive agent is resin which forms the said 1st resin insulating layer, The wiring board characterized by the above-mentioned. A capacitor making step of preparing a capacitor having a dielectric layer and a first electrode and a second electrode opposing each other with the dielectric layer interposed therebetween; A capacitor laminate creation step of creating a capacitor laminate by laminating the capacitor through an adhesive; A lamination step of laminating a first resin insulating layer on the base substrate, A embedding step of embedding the capacitor laminate in the first resin insulating layer; A through-hole forming step of forming a through-hole penetrating the first electrodes and a through-hole penetrating the second electrodes in the capacitor laminate; Filling the through-holes with a metal conductor, a via conductor creation step of creating a first via conductor electrically connecting the first electrodes and a second via conductor electrically connecting the second electrodes; An external terminal creation step of creating a first external terminal electrically connected to the first via conductor and a second external terminal electrically connected to the second via conductor. It has a manufacturing method of the wiring board characterized by the above-mentioned. The method of claim 14, In the capacitor stack creation step, the capacitor stack is prepared by disposing the first electrode and the second electrode in a plane direction of the electrode. In the through hole forming step, a through hole penetrating the end of the first electrode and a through hole penetrating the end of the second electrode are formed. The method of claim 14, In the embedding step, the capacitor laminate is embedded in the first resin insulating layer so that the upper surface of the capacitor laminate and the upper surface of the resin insulating layer are the same plane. The method of claim 14, And a step of further laminating a second resin insulating layer on the first resin insulating layer after the embedding step. The method of claim 17, In the through hole forming step, a through hole that not only penetrates the first electrode or the second electrodes, but also penetrates the second resin insulating layer is formed, The said via conductor preparation process forms the via conductor which electrically connects the conductor pattern on the said base substrate, and the conductor pattern on a said 2nd resin insulating layer, The manufacturing method of the wiring board characterized by the above-mentioned. The method of claim 17, After the via conductor making step, a third resin insulating layer is further formed on the second resin insulating layer, A via conductor for electrically connecting the conductor pattern on the second resin insulating layer and the conductor pattern on the third resin insulating layer is formed. The method of claim 14, In the embedding step, the alignment mark formed on the capacitor of the uppermost layer of the capacitor laminate or the alignment mark formed on the capacitor of the lowest layer and the alignment mark formed on the base substrate are aligned with the capacitor laminate and the first resin insulating layer. Method for producing a wiring board characterized in that the cover for. The method of claim 16, The said via conductor preparation process forms the via conductor which electrically connects the conductor pattern on the said base substrate, and the conductor pattern on a said 1st resin insulating layer, The wiring board manufacturing method characterized by the above-mentioned. The method of claim 21, The conductor pattern on the said 1st resin insulating layer, and the 1st electrode of the capacitor in the uppermost surface of the said capacitor laminated body are integrated, and the electrode manufacturing method of the wiring board characterized by the above-mentioned. The method of claim 14, In the capacitor stack creation step, the first electrode has a plurality of first openings, and the second electrode has a plurality of second openings, In the through hole forming step, the through hole penetrates the first electrodes while the second opening is contacted with the second electrode in a non-contact manner, and the first opening is not in contact with the first electrode. The through-hole which penetrates the said 2nd electrode, penetrating is formed, The manufacturing method of the wiring board characterized by the above-mentioned. The method of claim 14, The said adhesive agent is resin which forms the said 1st resin insulating layer, The wiring board characterized by the above-mentioned. A capacitor making step of producing a capacitor having a dielectric layer and a first electrode and a second electrode opposing each other with the dielectric layer interposed therebetween; A capacitor laminate creation step of creating a capacitor laminate by laminating the capacitor through an adhesive; A first external connection terminal forming step of forming a first external connection terminal having a first external terminal and a second external terminal on a support plate; A build-up step of alternately stacking a plurality of resin insulating layers and a plurality of conductor circuits on the first external connection terminal and the support plate; A embedding step of embedding the capacitor laminate in one of the plurality of resin insulating layers; A through-hole forming step of forming a through-hole in the capacitor stack, through which the first electrode or the second electrode passes; Filling the through-holes with a metal conductor, a via conductor creation step of creating a first via conductor that electrically connects the first electrodes and a second via conductor that electrically connects the second electrodes; A second external connection terminal forming step of forming a second external connection terminal having a third external terminal and a fourth external terminal on the uppermost resin insulating layer positioned on the opposite side to the support plate among the plurality of resin insulating layers; Support plate removal process of removing the support plate With The first external terminal and the third external terminal are electrically connected to the first via conductor, and the second external terminal and the fourth external terminal are electrically connected to the second via conductor. The manufacturing method of the wiring board.

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