JP4339781B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board provided with a capacitor, and more particularly to a wiring board in which a capacitor is built in a core board and a resin insulating layer and a wiring layer are stacked on the top and bottom of the wiring board so that noise can be reliably removed.

  With the progress of integrated circuit technology, the operation of an IC chip is increasingly speeded up, but with this, noise may be superimposed on the power supply wiring and the like to cause malfunction. In order to eliminate noise, for example, as shown in FIG. 15, a chip capacitor 3 is separately mounted on the upper surface 2A or the lower surface 2B of the wiring board 2 on which the IC chip 1 is mounted, and is connected to the two electrodes of the capacitor 3, respectively. The capacitor connection wiring 4 is provided inside the wiring board 2. Thus, the chip capacitor 3 is connected to the IC chip 1 via the capacitor connection wiring 4 and the flip chip pad 5.

  However, in the above method, since it is necessary to separately mount the chip capacitor 3 after the wiring board 2 is completed, man-hours are required and the cost is increased. Further, depending on the connection reliability of the chip capacitor 3, the reliability of the wiring substrate may be lowered, such as the quality of the entire wiring substrate being affected by the connection of the chip capacitor. In addition, it is necessary to secure a region for mounting the chip capacitor 3 in advance, which reduces the degree of freedom of fixing of the reinforcing member for mounting other electronic components or reinforcing the wiring board. Furthermore, the length of the capacitor connection wiring 4 that connects the IC chip 1 and the chip capacitor 3 is long and is likely to be narrowed by being limited to other wirings, etc., so that the resistance and inductance of the capacitor connection wiring 4 itself increase. Therefore, it cannot fully meet the demand for low resistance and low inductance.

  Therefore, among the wiring substrates, a resin insulating layer formed on the top and bottom of the core substrate and a part of the wiring layer are formed in a capacitor structure in which the resin insulating layer is sandwiched between opposing wiring layers (electrode layers) as a dielectric layer, It is conceivable to incorporate a capacitor. However, if the capacitor becomes defective due to a short circuit or defective insulation resistance, the entire wiring board with added value will be discarded, resulting in a large loss amount and eventually manufacturing the wiring board at a low cost. Is difficult. Moreover, even if a high dielectric constant ceramic powder or the like is mixed, the relative dielectric constant of the resin insulating layer is generally expected to be about 40 to 50 at most, so it is difficult to sufficiently increase the capacitance of the built-in capacitor. .

The present invention has been made in view of the above problems, and by incorporating a capacitor, it is possible to reliably remove noise, and to further reduce the resistance and inductance of wiring connected to the capacitor, and An object of the present invention is to provide a wiring board that has a small amount of loss even if a defect occurs in a capacitor, is inexpensive, and can incorporate a capacitor having a large capacitance.

The solution includes a wiring board upper surface and a wiring board lower surface, and a plurality of IC connection terminals for connecting to an IC chip on the wiring board upper surface, and a plurality of lower surface connection terminals on the wiring board lower surface, A wiring board containing a capacitor, the core board body upper surface, the core board body lower surface, a capacitor built-in through-hole penetrating between the core substrate body upper surface and the core substrate body lower surface, and the core substrate body upper surface; A core substrate body including a plurality of core through-hole conductors formed so as to penetrate between the lower surface of the core substrate body, a capacitor upper surface, a capacitor lower surface, a pair of electrodes or a group of electrodes insulated from each other, and formed on the capacitor upper surface A plurality of upper surface connection pads respectively conducting to any one of the pair of electrodes or the electrode group, the pair of electrodes Alternatively, each of the electrode groups is formed on a plurality of upper surface connection pads that are electrically connected to at least one of the plurality of upper surface connection pads, and on the lower surface of the capacitor, and is either one of the pair of electrodes or the electrode group Or a plurality of lower surface connection pads that respectively conduct with the electrode group, wherein each of the pair of electrodes or electrode groups includes a plurality of lower surface connection pads that conduct with at least one of the plurality of lower surface connection pads, The capacitor built in and fixed in the capacitor built-in through-hole of the core substrate body, the upper surface of the core substrate body and one or more upper resin insulation layers stacked above the capacitor upper surface, and the lower surface of the core substrate body And one or a plurality of lower resin insulation layers laminated below the capacitor lower surface, and the upper resin insulation layer or a layer thereof A plurality of upper capacitor connection wires respectively connecting the plurality of IC connection terminals on the upper surface of the wiring board and the corresponding plurality of upper surface connection pads of the capacitor, and passing through or between the lower resin insulating layers A plurality of lower capacitor connection wires respectively connecting the plurality of lower surface connection pads of the capacitor and the corresponding lower surface connection terminals on the lower surface of the wiring board, and passing through the upper resin insulating layer or between the layers A plurality of upper core connection wirings respectively connecting the plurality of IC connection terminals on the upper surface of the wiring board and the corresponding core through-hole conductors on the upper surface of the core substrate body, and the lower resin insulating layer. A plurality of core through-hole conductors on the lower surface of the core substrate body and corresponding lower surfaces of the wiring substrate are passed through or through the layers. A plurality of lower core connection wires that respectively connect the lower surface connection terminals of the plurality of IC connection terminals, wherein at least a part of the plurality of IC connection terminals is located above the capacitor, via the upper capacitor connection wires, The wiring board is characterized by being connected to the upper surface connection pad of the capacitor .

  In the wiring board of the present invention, a capacitor built-in through hole is formed in a core substrate body, a capacitor is built therein, an upper resin insulating layer and a lower resin insulating layer are formed, and an IC connection terminal such as a flip chip pad and the like The upper surface connection pad is connected with the upper capacitor connection wiring, and the lower surface connection pad and the lower surface connection terminal are connected with the lower capacitor connection wiring. Further, each of the pair of electrodes or the electrode group is electrically connected to at least one of the plurality of upper surface connection pads. The lower surface connection pads are also the same. For this reason, both poles of the capacitor can be taken out above and below the capacitor. Therefore, both poles of the capacitor can be connected from the upper surface connection pad to the IC connection terminal and further to the IC chip through the upper capacitor connection wiring. Similarly, both poles of the capacitor can be connected from the lower surface connection pad to the lower surface connection terminal through the lower capacitor connection wiring. For this reason, the capacitor can be disposed at a very close distance from an IC connection terminal connected to the IC chip or a lower surface connection terminal connected to a power supply wiring or a ground wiring of another wiring board such as a mother board. Therefore, both the upper capacitor connection wiring and the lower capacitor connection wiring can be formed very short.

Furthermore, since a power supply potential and a ground potential are usually required at various locations in an IC chip, the power supply terminals and grounding are sometimes made closer to half the number of connection terminals (connection pads and connection bumps) formed on the IC chip. A large number of terminals are formed. On the other hand, the upper surface and the lower surface of the capacitor are provided with a plurality of upper surface connection pads and lower surface connection pads. Therefore, if a large number of upper surface connection pads are formed corresponding to the power supply terminals and ground terminals of the IC chip, and a large number of upper capacitor connection wires are formed in parallel so as to connect them, the inductance and resistance of the upper capacitor connection wires can be obtained. Can be further reduced as a whole. Similarly, the inductance and resistance as a whole can be further reduced similarly for the lower capacitor connection wiring that connects the lower surface connection pads corresponding to the lower surface connection pads and the connection terminals on the lower surface of the wiring board in parallel. In other words, the length of both the upper capacitor connection wiring and the lower capacitor connection wiring can be shortened and the number thereof can be increased, so that the resistance and inductance can be reduced, and the noise can be effectively and reliably removed by the capacitor. .

  In addition, since the capacitor is built in the wiring board, it is not necessary to attach the capacitor later, and the cost for mounting the chip capacitor is not required, so that an inexpensive wiring board can be obtained. In addition, the degree of freedom of mounting other electronic components and the like and fixing the reinforcing plate is high. Furthermore, since the capacitor is built in the capacitor built-in through hole formed in the core substrate body, the upper resin insulating layer, the lower resin insulating layer or the upper capacitor connecting wiring, the lower capacitor connecting wiring, the upper core connecting wiring, and the lower The core connection wiring can be made inexpensive in that any core connection wiring can be formed using a known resin insulation layer or wiring layer manufacturing method. In addition, since the capacitance of the capacitor to be incorporated can be freely selected, a capacitor having a large capacitance using a high dielectric constant ceramic can be incorporated, and the noise removal capability can be further improved.

In addition , at least a part of the plurality of IC connection terminals is located above the capacitor, and is connected to the upper surface connection pad of the capacitor via an upper capacitor connection wiring . When an IC connection terminal such as a flip chip pad is positioned above the capacitor, the length of the upper capacitor connection wiring connecting the IC connection terminal and the upper surface connection pad of the capacitor can be particularly shortened. Therefore, since the inductance and resistance of the upper capacitor connection wiring can be further reduced, the noise removal capability can be further improved.

  Further, in the above wiring board, the core substrate body includes a capacitor receiving portion projecting radially inward at either end of the capacitor built-in through hole, A wiring board characterized by being in contact with the inward surface of the capacitor receiving portion is preferable.

  In the wiring board of the present invention, a capacitor receiving portion protruding inward in the radial direction (plane direction) is formed, and the capacitor receiving portion is formed on the inward surface of the capacitor receiving portion of the core substrate body, that is, the capacitor receiving portion of the through hole for incorporating a capacitor. When formed on the upper end, the capacitor is brought into contact with the lower surface, and when the capacitor receiving portion is formed at the lower end of the capacitor built-in through hole, the capacitor is brought into contact with the upper surface. As a result, the capacitor can be easily and reliably positioned in the vertical direction within the capacitor built-in through hole. Therefore, a highly reliable wiring board that does not cause poor connection between the upper surface connection pad and the upper capacitor connection wiring or poor connection between the lower surface connection pad and the lower capacitor connection wiring due to the positional misalignment in the vertical direction of the capacitor. It can be.

  Further, in the above wiring board, the capacitor is formed with at least one of a notch portion and a convex portion on a peripheral edge of the capacitor upper surface and the capacitor lower surface on the side in contact with the capacitor receiving portion, The wiring board may be characterized in that the capacitor is fitted into the capacitor receiving portion by at least one of the notched portion and the convex portion.

The wiring board of the present invention has at least one of a notch portion and a convex portion on the periphery of the surface of the upper surface and the lower surface of the capacitor that contacts the capacitor receiving portion of the core substrate body. It abuts on the inward surface of the part, and further fits with the capacitor receiving part by at least one of the notch part and the convex part. Therefore, the capacitor is positioned in the vertical direction by contacting the capacitor receiving portion, and is also positioned in the radial direction (planar direction) of the through hole for incorporating a capacitor perpendicular to the vertical direction by fitting with the capacitor receiving portion. The For this reason, it is possible to easily and reliably position the capacitor in the planar direction as well as the vertical direction in the capacitor built-in through hole. Therefore, it does not cause poor connection between the upper surface connection pad and the upper capacitor connection wiring or poor connection between the lower surface connection pad and the lower capacitor connection wiring due to misalignment in the vertical direction or planar direction of the capacitor. It can be set as a highly reliable wiring board.

Furthermore, in the wiring board according to claim 1, the core board body may be a wiring board in which the dimension in the planar direction of the capacitor built-in through hole is not changed from the upper end to the lower end.
In the above-described wiring board, the capacitor may be a wiring board having a thickness that is substantially the same as the thickness of the core substrate body .

Also, the core substrate main body top surface, a core substrate main body lower surface, and a core substrate body with a through-hole, a capacitor built penetrating between the core substrate main body upper surface and the core substrate main body bottom surface, the capacitor top, capacitor lower surface, A pair of electrodes or electrode groups insulated from each other, a plurality of upper surface connection pads formed on the upper surface of the capacitor and respectively conducting with any one of the electrodes or electrode groups of the pair of electrodes or electrode groups, Any one of the pair of electrodes or electrode groups is formed on the lower surface of the capacitor and the plurality of upper surface connection pads that are electrically connected to at least one of the plurality of upper surface connection pads. A plurality of lower surface connection pads respectively conducting to the electrode or the electrode group, wherein each of the pair of electrodes or the electrode group is A plurality of lower surface connection pads that are electrically connected to at least one of the connection pads, and a capacitor built in and fixed in the capacitor built-in through hole of the core substrate body. The capacitor is fixed in the capacitor built-in through hole with a filled resin filled, and an upper filling resin layer is formed on the capacitor upper surface, or on the core substrate main body upper surface and the capacitor upper surface, on the capacitor lower surface, or It is preferable to use a capacitor built-in core substrate having a lower filling resin layer on the lower surface of the core substrate body and the lower surface of the capacitor.

In this core substrate with a built-in capacitor, a capacitor built-in through hole is formed in the core substrate body, and the capacitor is built therein. Further, the capacitor is configured such that any of the pair of electrodes or the electrode group is electrically connected to at least one of the plurality of upper surface connection pads. The lower surface connection pads are also the same. Therefore, both poles of the capacitor can be taken out above and below the core substrate through the upper surface connection pad on the upper surface of the capacitor and the lower surface connection pad on the lower surface of the capacitor. Therefore, if this core board with a built-in capacitor is used, a wiring board with a built-in capacitor can be easily formed by using a known method for forming a resin insulating layer or a wiring layer. Further, when the wiring board is formed in this way, capacitors can be arranged at a very close distance from other wiring boards such as an IC chip and a mother board mounted on the wiring board, and can be connected to each other with very short wiring. Therefore, the characteristics of the built-in capacitor can be fully exhibited and noise can be reliably removed.

Further, as described above, in a normal IC chip, a large number of power terminals and ground terminals are formed. On the other hand, the capacitor of the core substrate with built-in capacitor according to the present invention includes a plurality of upper surface connection pads and lower surface connection pads on the capacitor upper surface and the capacitor lower surface. Therefore, a large number of upper surface connection pads (or a lower surface connection pad when used upside down) are formed corresponding to the power supply terminal and ground terminal of the IC chip, and a large number of wirings are formed in parallel so as to connect them. Then, the inductance and resistance of these wirings can be further reduced as a whole. Similarly, regarding the wiring for connecting the lower surface connection pad (or the upper surface connection pad in the case of being inverted upside down) and another wiring board in parallel, the inductance and resistance can be further reduced as a whole. . In other words, the length of the wiring formed above and below the capacitor built-in core substrate can be shortened and the number of wires can be increased, so that the resistance and inductance can be lowered, and the noise can be effectively and reliably removed by the capacitor. . In addition, since the capacitance of the capacitor to be incorporated can be freely selected, a capacitor having a large capacitance using a high dielectric constant ceramic can be incorporated, and the noise removal capability can be further improved.

In addition, since the capacitor is built in the core substrate, there is no need to install a separate capacitor after the resin insulation layer or wiring layer is formed, and the cost for mounting the chip capacitor is not required. Can be manufactured.
Moreover, since the quality of the built-in capacitor can be judged through the upper surface connection pad or the lower surface connection pad, the core substrate with the capacitor having a defect such as a short circuit can be removed before forming the resin insulating layer or the like. . For this reason, resin insulation layers and wiring layers that require man-hours are formed, and the risk of discarding high value-added wiring boards can be reduced, and the loss due to capacitor defects as a whole is also reduced, resulting in an inexpensive wiring board. be able to.

  Furthermore, a capacitor built-in core substrate is characterized in that the capacitor is fixed in the capacitor built-in through hole with a filling resin filled in the capacitor built-in through hole.

For this reason, in the core board with a built-in capacitor according to the present invention, the capacitor can be easily and surely fixed because the capacitor is fixed in the through hole for the built-in capacitor with the filling resin. In addition, the built-in capacitor can be prevented from being misaligned or dropped due to vibration generated when drilling through-holes for core through-hole conductors. Can do.
Furthermore, a capacitor-embedded core comprising an upper filling resin layer on the upper surface of the capacitor or on the upper surface of the core substrate body and the upper surface of the capacitor, and a lower filling resin layer on the lower surface of the capacitor or on the lower surface of the core substrate body and the lower surface of the capacitor. It is a substrate.

  Further, in any one of the above-described capacitor-embedded core substrates, the upper filling resin layer on the capacitor upper surface and the upper surface of the core substrate body or the upper filling resin layer on the core substrate body upper surface are substantially flush with each other. The plurality of upper surface connection pads are substantially flush with each other, and the lower filling resin layer on the lower surface of the capacitor and the lower filling resin layer on the lower surface of the core substrate body or the lower surface of the core substrate body are substantially in plane. Preferably, the capacitor-embedded core substrate is characterized in that the plurality of lower surface connection pads are substantially flush with each other.

In this core substrate with a built-in capacitor, the upper filling resin layer on the upper surface of the capacitor and the upper filling resin layer on the upper surface of the core substrate body or the upper surface of the core substrate body are substantially flush, and a plurality of upper surface connection pads are substantially omitted. It is exposed to the same level. Further, the lower filling resin layer on the lower surface of the capacitor and the lower filling resin layer on the lower surface of the core substrate body or the lower surface of the core substrate body are substantially flush, and a plurality of lower surface connection pads are substantially flush with each other. Yes.
For this reason, when forming a wiring board by laminating resin insulation layers and wiring layers on the top and bottom of this core substrate, the height difference between the top surface of the core substrate body and the capacitor top surface due to the formation of the capacitor built-in through hole It is possible to prevent the occurrence of a step in the resin insulating layer and the wiring layer formed above and below due to the difference in height or the difference in height between the lower surface of the core substrate body and the lower surface of the capacitor. Therefore, the resin insulating layer and the wiring layer can be easily formed, and the wiring layer is not broken or short-circuited. Further, the coplanarity of the IC connection terminals and the lower surface connection terminals formed on the upper surface and the lower surface of the wiring board can be improved, and the connectivity with the IC chip and other wiring boards can be improved.

  Furthermore, in any one of the above-described capacitor-embedded core substrates, the core substrate body includes a capacitor receiver that protrudes radially inwardly at an end portion on the lower surface side of the core substrate body among the through holes for incorporating capacitors. The capacitor is preferably a core substrate with a built-in capacitor, wherein the capacitor is in contact with the upper surface of the capacitor receiving portion.

The wiring board of this, form a capacitor receiving portion in the core substrate main body, and is brought into contact with the capacitor to the top surface. As a result, the capacitor can be easily and reliably positioned in the vertical direction within the capacitor built-in through hole. Therefore, when the height of the upper surface connection pad fluctuates due to the vertical misalignment of the capacitor, or when the residue of the filling resin remains on the upper surface connection pad and a via conductor or the like connected to this remains formed In addition, there is no inconvenience such as poor conduction between the upper surface connection pad and the via conductor. The same applies to the lower surface connection pads. Therefore, when a resin insulating layer, a wiring layer, and a via conductor are formed above and below, a highly reliable core substrate with a built-in capacitor that does not cause poor connection with the wiring or via conductor can be obtained.

  Further, in the core substrate with a built-in capacitor, the capacitor is formed with at least one of a notch and a protrusion on a peripheral edge of the lower surface of the capacitor, and the capacitor is formed by at least one of the notch and the protrusion. A capacitor-embedded core substrate is preferable in which a capacitor is fitted in the capacitor receiving portion.

The capacitor built core substrate this, the capacitor is in contact with the part receiving the capacitor, moreover, at least one notch and a convex portion formed on the capacitor, the capacitor is fitted to the portion receiving the capacitor. Therefore, the capacitor is positioned in the vertical direction by contacting the capacitor receiving portion, and is also positioned in the radial direction (planar direction) of the through hole for incorporating a capacitor perpendicular to the vertical direction by fitting with the capacitor receiving portion. The For this reason, it is possible to easily and reliably position the capacitor in the planar direction as well as the vertical direction in the capacitor built-in through hole. Therefore, when the height of the upper surface connection pad and the position in the planar direction fluctuate, or when a via conductor or the like is formed on the upper surface connection pad, the residue of the filling resin remains and is connected to the upper surface connection pad. There are no problems such as poor conduction. The same applies to the lower surface connection pads. Therefore, when a resin insulating layer, a wiring layer, and a via conductor are formed on the upper and lower sides, a highly reliable core substrate with a built-in capacitor that does not cause poor connection with the wiring or the via conductor can be obtained.

Alternatively, in the above-described core board with a built-in capacitor, the core board body may be a core board with a built-in capacitor in which the planar dimension of the through hole for built-in capacitor does not change from the upper end to the lower end.
The capacitor-embedded core substrate may be a capacitor-embedded core substrate whose thickness is substantially the same as the thickness of the core substrate body.

  And a capacitor built-in through-hole penetrating between the core substrate body upper surface and the core substrate body lower surface, wherein the capacitor built-in through hole has its core It is preferable to provide a core substrate body characterized by including a capacitor receiving portion that protrudes radially inward at the lower end portion of the substrate main body, and that can be brought into contact with at least the upper surface thereof.

Since the core substrate body includes a capacitor built-in through-hole penetrating between the upper and lower surfaces, the wiring substrate incorporating the capacitor can be easily formed by incorporating the capacitor in the through-hole. Further, the capacitor built in the through-hole can be easily and shortly connected from any of the upper surface of the core substrate body and the lower surface of the core substrate body.
Further, since the capacitor receiving portion is provided, when the capacitor is built in, the capacitor comes into contact with the upper surface of the capacitor receiving portion. For this reason, the vertical positioning of the capacitor in the capacitor built-in through hole can be ensured.

  Furthermore, in the core substrate body, the capacitor receiving portion has a shape that can be fitted to at least one of a notch portion and a convex portion formed on a surface on the contact side of the capacitor to be built-in. It is preferable to use a core substrate body.

  In this core substrate body, when the capacitor is built in, the capacitor receiving portion abuts on the upper surface thereof, and further fits with at least one of the notch portion and the convex portion formed on the abutting side surface of the capacitor. Therefore, the capacitor can be reliably positioned not only in the vertical direction but also in the plane direction perpendicular to the vertical direction (the radial direction of the capacitor built-in through hole).

  Further, the upper surface of the capacitor, the lower surface of the capacitor, a pair of electrodes or electrode groups insulated from each other, and formed on the upper surface of the capacitor, are electrically connected to any one of the pair of electrodes or electrode groups. A plurality of upper surface connection pads, each of the pair of electrodes or electrode groups being formed on the lower surface of the capacitor, the plurality of upper surface connection pads electrically connected to at least one of the plurality of upper surface connection pads; A plurality of lower surface connection pads that respectively conduct with any one of the electrodes or electrode groups, and each of the pair of electrodes or electrode groups conducts with at least one of the plurality of lower surface connection pads. A plurality of lower surface connection pads, and a capacitor built-in through hole formed in the periphery of the lower surface of the capacitor. Diameter and a capacitor receiving portion projecting in a direction inwardly with at least one of contact with fittable notches and protrusions, may be a capacitor comprising at.

The capacitor includes a plurality of upper surface connection pads on the upper surface of the capacitor and a plurality of lower surface connection pads on the lower surface of the capacitor, and both of the pair of electrodes or the electrode group are electrically connected to at least one of the plurality of upper surface connection pads. Further, each of the pair of electrodes or the electrode group is electrically connected to at least one of the plurality of lower surface connection pads. For this reason, both poles of the capacitor can be taken out from the upper surface of the capacitor. Similarly, both poles of the capacitor can be taken out from the lower surface of the capacitor.
Therefore, it is possible to connect between the connection surface of the IC chip, the wiring board, and other electronic components on which the pads and bumps are formed, both on the upper surface and the lower surface of the capacitor.

Further, both poles of the capacitor can be taken out from both the upper surface and the lower surface of the capacitor. For this reason, for example, by interposing between the wiring board and the IC chip, it can serve as a part of the power wiring and the ground wiring for supplying power from the wiring board to the IC chip, and the power wiring and the ground. The capacitor is connected to the wiring by this capacitor, and the role of removing noise superimposed on these wirings can also be fulfilled.
Furthermore, by incorporating and fixing in the capacitor built-in through hole of the core substrate body provided with the capacitor built-in through hole, a capacitor built-in core substrate is formed, and a resin insulating layer and a wiring layer are formed to incorporate the capacitor. It can be set as a wiring board. In particular, positioning in the through hole of the capacitor is possible by contacting the capacitor receiving part protruding inward in the radial direction in this capacitor built-in through hole and fitting with the notch or convex part of the capacitor. Easy to do.

The upper surface connection pads and the lower surface connection pads may be formed at positions and numbers corresponding to the terminals and wiring layers of IC chips to be connected, but as the number of terminals and wiring layers connected in parallel increases, Since resistance and inductance generated between the IC chip and the like can be suppressed as a whole, a large number of upper surface connection pads and lower surface connection pads are preferably formed.

  Furthermore, since at least one of a notch and a protrusion is provided on the periphery of the lower surface of the capacitor, when the capacitor is built in the capacitor built-in through hole of the core substrate body, the capacitor receiving portion is abutted and fitted. The capacitor can be reliably positioned both in the vertical direction and in the plane direction orthogonal thereto within the capacitor built-in through hole.

  Further, the wall core substrate body lower surface of the wall core substrate body having a wall core substrate body upper surface and a wall core substrate body lower surface, and including a wall through hole penetrating between them. And the core substrate main body for the receiving portion of the core substrate main body for the receiving portion provided with a through hole for the receiving portion that penetrates between the upper surface of the core substrate main body for the receiving portion and the lower surface of the core substrate main body for the receiving portion. A core substrate body comprising a bonding step of exposing at least a part of a periphery of the through hole for the receiving portion of the core substrate for the receiving portion in the through hole for the wall portion It is good to use this manufacturing method.

  In this method of manufacturing a core substrate body, a wall core substrate body having a wall through hole and a receiving core substrate body having a receiving through hole are connected to the receiving core in the wall through hole. A core substrate body is manufactured by exposing and bonding at least a part of the periphery of the through hole for receiving portion of the substrate. In this way, when the wall core substrate body and the receiving core substrate body are separately manufactured and then bonded together, the through hole for built-in capacitor is easily formed by the through hole for the wall portion and the through hole for the receiving portion. In addition, a part of the core substrate body for receiving portion can be a capacitor receiving portion protruding radially inward at the end of the capacitor built-in through hole.

  In addition, in the through-hole for a capacitor built-in of the core board body provided with a core board main body upper surface, a core substrate main body lower surface, and a capacitor built-in through-hole penetrating between the core substrate main body upper surface and the core substrate main body lower surface A capacitor upper surface, a capacitor lower surface, a pair of electrodes or electrode groups insulated from each other, and a plurality of upper surfaces formed on the capacitor upper surface and respectively conducting with any one of the pair of electrodes or electrode groups A plurality of upper surface connection pads that are electrically connected to at least one of the plurality of upper surface connection pads, and the lower surface of the capacitor. A plurality of lower surface connection pads that are electrically connected to any one of the electrodes or each of the electrode groups, and each of the pair of electrodes. Each of the electrode groups includes a capacitor placement step of placing a capacitor having a plurality of bottom surface connection pads that are electrically connected to at least one of the plurality of bottom surface connection pads, and injecting a filling resin into at least the capacitor built-in through hole A capacitor fixing step of curing the filling resin and fixing the capacitor with the filling resin in the capacitor built-in through hole, and a core through that penetrates at least between the upper surface of the core substrate body and the lower surface of the core substrate body. And a core through-hole forming step of forming a hole conductor.

  In this method of manufacturing a core substrate with a built-in capacitor, a capacitor is disposed in the through-hole for built-in capacitor, and a filling resin is injected into the through-hole for built-in capacitor and cured to fix the capacitor. For this reason, it can be easily fixed, and the defects such as displacement and dropout of the capacitor due to vibration generated when drilling through holes for core through-hole conductors, etc. are suppressed, and the reliability of the core board with a built-in capacitor is reduced. Can be improved.

Furthermore, in the method of manufacturing the capacitor built-in core substrate, the capacitor fixing step includes the capacitor upper surface, the capacitor lower surface, the core substrate body upper surface, and the core substrate body lower surface in addition to the inside of the capacitor built-in through hole. A capacitor fixing-filling resin coating / curing step in which at least the capacitor upper surface and the capacitor lower surface are coated and cured, and prior to the core through hole forming step, on the capacitor upper surface, or on the capacitor upper surface and the capacitor The filling resin on the upper surface of the core substrate body is polished to expose the plurality of upper surface connection pads substantially flush with each other, and the filling resin layer on the capacitor upper surface and the upper surface of the core substrate body are used. The filling resin layer on the upper surface and the filling resin layer on the upper surface of the core substrate body are substantially flush with each other. And polishing the filler resin on the capacitor lower surface or on the capacitor lower surface and the core substrate body lower surface to expose the plurality of lower surface connection pads substantially flush with each other and on the capacitor lower surface. Polishing step for leveling the filling resin layer and the lower surface of the core substrate body, or the filling resin layer on the lower surface of the capacitor and the filling resin layer on the lower surface of the core substrate body to a substantially flat surface. It is preferable to provide a method of manufacturing a core substrate with a built-in capacitor.

  In this method of manufacturing a core board with a built-in capacitor, the capacitor is built in the through hole for built-in the capacitor and further fixed with a filling resin, and at least the filling resin is applied to the capacitor upper surface and the capacitor lower surface to be cured. Further, the plurality of upper surface connection pads are exposed to be substantially flush by polishing, and the filling resin layer on the capacitor upper surface and the upper surface of the core substrate main body, or the filling resin layer on the capacitor upper surface and the upper surface of the core substrate main body are exposed. The filling resin layer is leveled to a substantially flat surface. Further, the plurality of lower surface connection pads are exposed to be substantially flush by polishing, and the filling resin layer on the capacitor lower surface and the upper surface of the core substrate main body, or the filling resin layer on the capacitor upper surface and the upper surface of the core substrate main body are exposed. The filling resin layer is leveled to a substantially flat surface. Thereafter, a core through-hole conductor is formed.

  For this reason, when one or a plurality of resin insulation layers or wiring layers are formed above the upper surface of the core substrate body and the upper surface of the capacitor, there is no step between the upper surface of the core substrate body and the upper surface of the capacitor. Similarly, when one or a plurality of resin insulating layers or wiring layers are formed below the core substrate main body lower surface and the capacitor lower surface, no step is generated between the lower surface of the core substrate main body and the lower surface of the capacitor lower surface. For this reason, a resin insulation layer, a wiring layer, etc. can be formed easily, or generation | occurrence | production of malfunctions, such as a disconnection of each wiring layer and a short circuit, can be suppressed. Furthermore, the coplanarity of the IC connection terminal and the lower surface connection terminal can be kept small, and the connectivity with the IC chip and other wiring boards can be improved.

(Embodiment 1)
DESCRIPTION OF EMBODIMENTS Embodiments of a wiring board and the like of the present invention will be described with reference to the drawings. A wiring board 100 incorporating the capacitor of the present invention shown in FIG. 1 has a substantially square plate shape, and a flip chip which is an IC connection terminal for connecting to an IC chip 1 indicated by a broken line on its upper surface (wiring board upper surface) 100A. A large number of pads 101 are formed, and each flip chip pad 101 is formed with a substantially hemispherical flip chip bump 102 made of high-temperature solder. On the other hand, on the lower surface 100B of the wiring board, a large number of LGA pads 103 which are lower surface connection terminals for connecting to other wiring boards such as a mother board are formed. Further, the wiring substrate 100 includes a core substrate body 10 including the capacitor 20, resin insulating layers 41, 42, 43, 51, 52, and 53 stacked on the upper and lower sides thereof, and between these layers and the resin insulating layers. Each wiring layer 60, 70, 80, 90 formed through the layer is provided.

Among these, the core substrate body 10 is a substantially square plate shape and is made of a glass-epoxy resin composite material, and has a substantially square shape in plan view that penetrates between the core substrate body upper surface 10A and the core substrate body lower surface 10B. A capacitor built-in through hole (hereinafter also simply referred to as a through hole) 11 is provided. In the through hole 11 for incorporating a capacitor, the radial direction (planar direction, left and right in the figure) of the through hole 11 orthogonal to the axial direction (up and down direction in the figure) of the through hole 11 is located at the end on the core substrate main body lower surface 10B side. In the direction, a capacitor receiving portion (hereinafter also simply referred to as a receiving portion) 12 that protrudes into the through hole 11 is formed over the periphery of the through hole 11. A capacitor 20 is built in the through hole 11. Further, a large number of core through-hole conductors 33 are formed on the peripheral edge of the core substrate body 10 so as to penetrate between the core substrate body upper surface 10A and the core substrate body lower surface 10B.

As shown in the plan view of FIG. 2A and the perspective view seen from the lower surface side of FIG. 2B, the capacitor 20 is a dielectric having a high dielectric ceramic, specifically, BaTiO ₃ as a main component. This is a substantially square plate-shaped multilayer ceramic capacitor in which body layers 24 and electrode layers 25 mainly composed of Pd are alternately stacked. However, as can be seen from FIG. 2 (b), the periphery of the capacitor lower surface 20B is lowered by one step in a step shape by the notch 20P, leaving a square area in the center, as will be described later. A contact surface 20 </ b> C with the capacitor receiving portion 12 of the main body 10 is formed. That is, the capacitor 20 has a substantially convex shape on the lower surface 20B. The capacitor 20 is used for a chip capacitor or the like, and is connected to a normal multilayer ceramic capacitor in which two electrodes (common electrodes) that form both electrodes of the capacitor are taken out from the side surfaces of the laminated dielectric layer and electrode layer. The method of taking out the electrodes for the purpose is different. That is, as shown in FIG. 2 (c), a large number of upper surface connection pads 21 (21A, 21B, 21C in FIG. 2 (c)) and lower surface connection pads 22 (FIG. 2) are formed on the capacitor upper surface 20A and the capacitor lower surface 20B, respectively. (C) includes 22A, 22B, and 22C), and these pads 21 and 22 enable connection to the upper or lower side in FIG. 2C within the capacitor upper surface 20A and capacitor lower surface 20B. Yes.

  2C, the electrode layer 25 of the capacitor 20 is divided into a pair of electrode layers 25E and 25F which are electrically connected to every other layer by via conductors 26E and 26F, respectively. It has been. Moreover, the electrode layer groups 25E and 25F are insulated from each other. Therefore, the two electrode groups 25 </ b> E and 25 </ b> F that face each other with each dielectric layer 24 interposed therebetween form two electrodes of the capacitor 20. Further, a part of the upper surface connection pad 21 (the right and left pads 21A and 21C in the figure) is located at the uppermost position of the electrode layer 25, the top electrode layer 25ET belonging to one electrode group 25E, and the dielectric layer. 24, via conductors 27E penetrating through the top dielectric layer 24T located at the uppermost position. Further, another part of the upper surface connection pad 21 (the center pad 21B in the figure) is connected to the electrode layer 25 located below the top electrode layer 25ET and belonging to the other electrode group 25F by the via conductors 27F and 26F. is doing. As described above, the large number of upper surface connection pads 21 are connected to one of a pair of electrode groups 25E and 25F forming two electrodes of the capacitor, and each of the pair of electrode groups 25E and 25F includes a plurality of electrodes. It is connected to at least one of the upper surface connection pads 21. That is, one upper surface connection pad 21 (for example, 21A) among the many upper surface connection pads 21 is connected to one electrode group 25E. A certain upper surface connection pad 21 (for example, 21B) is connected to the other electrode group 25F. For this reason, it is possible to conduct both the pair of electrode groups 25E and 25F from above the capacitor 20 through the upper surface connection pad 21.

Similarly, some of the lower surface connection pads 22 (right and left pads 22A and 22C in the figure) are located above the lowermost bottom electrode layer 25FD in the electrode layer 25, and belong to one electrode group 25E. The layer 25 and the dielectric layer 24 are connected by via conductors 28F and 26F penetrating the bottom dielectric layer 24D located at the lowermost position. Further, another part of the lower surface connection pad 22 (the center pad 22B in the figure) is connected to the bottom electrode layer 25FD belonging to the other electrode group 25F by the via conductor 28F. Thus, the large number of lower surface connection pads 22 are connected to one of a pair of electrode groups 25E and 25F forming two electrodes of the capacitor, and both of the pair of electrode groups 25E and 25F are connected to the lower surface. It is connected to at least one of the connection pads 22. That is, the lower surface connection pad 22 (for example, 22A) among the multiple lower surface connection pads 22 is connected to one electrode group 25E. A certain lower surface connection pad 22 (for example, 22B) is connected to the other electrode group 25F. For this reason, it is possible to conduct both of the pair of electrode groups 25 </ b> E and 25 </ b> F from below the capacitor 20 through the lower surface connection pad 22. As shown in FIG. 2B and described above, the bottom dielectric layer 24D on which the lower surface connection pads 22 are formed has a size in the plane direction (left and right direction in the drawing) larger than that of the other dielectric layers 24. By making it smaller, the notch 20P is formed, and thereby the dielectric layer 24 one layer above is exposed and the above-described contact surface 20C is formed. Also, the bottom electrode layer 25FD has a size smaller in the plane direction than the other electrode layers belonging to the electrode group 25F in accordance with the shape of the bottom dielectric layer 24D.

  As shown in FIG. 1, the vicinity of the capacitor lower surface 20 </ b> B, which is notched and formed in a convex shape, is fitted to the inner peripheral edge 12 </ b> H of the capacitor receiving portion 12. For this reason, the contact surface 20C and the inward surface 12S (upper surface in the drawing) of the receiving portion 12 are in contact with each other so that the capacitor 20 is positioned in the vertical direction in the drawing, and the receiving portion through hole 12H is notched. By positioning with 20P, positioning in the radial direction (planar direction, left-right direction in the figure) is performed. Further, the capacitor 20 is fixed in the capacitor built-in through hole 11 by a filling resin 32 made of an epoxy resin, and is integrated with the core substrate body 10. Thereby, the capacitor 20 built in the core substrate body 10 can be connected by the upper surface connection pad 21 in the upper part of the drawing and by the lower surface connection pad 22 in the lower part of the drawing.

  Further, three upper resin insulating layers 41, 42, 43 mainly composed of epoxy resin are provided above the core substrate main body upper surface 10A and the capacitor upper surface 20A. On the other hand, three lower resin insulating layers 51, 52, and 53 are provided below the core substrate main body lower surface 10B and the capacitor lower surface 20B. Further, between the upper resin insulating layers 41 and 42 and between the upper resin wiring layers 42 and 43, wiring layers 45 and 46 made of Cu plating are formed so as to penetrate the upper resin insulating layers 41 and 42, respectively. . Similarly, wiring layers 55 and 56 made of Cu plating are formed between the lower resin insulating layers 51 and 52 and between the lower resin wiring layers 52 and 53, respectively, through the lower resin insulating layers 51 and 52. ing.

  Among these, the wiring which penetrates between the upper resin insulation layers 41, 42 and 43 and the upper resin insulation layers 41 and 42, respectively, and connects the flip chip pad 101 and the upper surface connection pad 21 of the capacitor 20 corresponding thereto. The layers 45 and 46 constitute the upper capacitor connection wiring 60. Further, wiring layers 45, which pass through the upper resin insulation layers 41, 42, 43 and the upper resin insulation layers 41, 42, respectively, connect the flip chip pad 101 and the corresponding core through-hole conductor 33, respectively. 46 constitutes the upper core connection wiring 80. On the other hand, the wiring layers 55 and 56 that pass through the lower resin insulating layers 51, 52, and 53 and the upper resin insulating layers 51 and 52, respectively, and connect the lower surface connection pad 22 and the corresponding LGA pad 103, respectively. The lower capacitor connection wiring 70 is configured. In addition, wiring layers 55 and 56 that pass through the lower resin insulating layers 51, 52, and 53 and the lower resin insulating layers 51 and 52, respectively, and connect the core through-hole conductor 33 and the corresponding LGA pad 103, respectively. Constitutes the lower core connection wiring 90.

As a result, the IC chip 1 connected to the flip chip bump 102 is connected to the pair of electrode groups 25E and 25F of the capacitor 20 through the flip chip pad 101, the upper capacitor connection wiring 60, and the upper surface connection pad 21, respectively. .
Further, the LGA pad 103 is connected to the pair of electrode groups 25E and 25F of the capacitor 20 through the lower capacitor connection wiring 70 and the lower surface connection pad 22, respectively.
Therefore, as shown in FIG. 2D, the upper capacitor connection wiring 60 and the lower capacitor connection wiring 70 connected between the flip chip pad 101 and the LGA pad 103 and connected to one electrode group 25E, and the other The capacitor 20 is inserted between the upper capacitor connection wiring 60 and the lower capacitor connection wiring 70 connected to the electrode group 25F.

For this reason, the power supply potential and the ground potential supplied from the motherboard connected to the LGA pad 103 are transmitted from the LGA pad 103 to the lower capacitor connection wiring 70, the capacitor 20, the upper capacitor connection wiring 60, the flip chip pad 101, and the flip chip bump. Through 102, the IC chip 1 can be supplied. Furthermore, noise superimposed on the power supply potential and the ground potential can be removed by the capacitor 20.
In addition, since the capacitor 20 is built in the core substrate body 10, the capacitor 20 can be arranged very close to the IC chip 1, so that the length of the upper capacitor connection wiring 60 can be shortened. Therefore, the noise removal capability by the capacitor 20 can be further enhanced. In particular, in this embodiment, since the capacitor 20 is arranged directly under the IC chip 1 and therefore directly under the flip chip pad 101, the length of the upper capacitor connection wiring 60 can be extremely shortened. Therefore, since the distance between the IC chip 1 and the capacitor 20 can be made extremely short, noise is hardly superimposed between them, and this is particularly effective for noise removal.

  A large number of upper capacitor connection wirings 60 are formed, and a large number of flip chip pads 101 and a large number of upper surface connection pads 21 are connected in parallel. Therefore, by forming a large number of upper capacitor connection wirings 60, the resistance and inductance of the upper capacitor connection wiring 60 connecting the IC chip 1 (flip chip pad 101) and the capacitor 20 as a whole are also reduced. This is also advantageous for noise removal. Similarly, a large number of lower capacitor connection wires 70 are formed, and a large number of LGA pads 103 and a large number of lower surface connection pads 22 are connected in parallel. Accordingly, the formation of a large number of lower capacitor connection wirings 70 reduces the resistance and inductance of the lower capacitor connection wiring 70 connecting the LGA pad 103 and the capacitor 20 as a whole. Is advantageous.

On the other hand, the wiring connecting the IC chip 1 and the mother board etc. without being connected to the capacitor 20 such as a signal line is connected to the core through-hole conductor 33 from the flip chip pad 101 through the upper core connection wiring 80, and the core substrate body 10 is connected. It penetrates and is connected to the LGA pad 103 from the lower core connection wiring 90. This structure is the same as that of a normal build-up wiring board using a core board on which through-hole conductors are formed.
As described above, in the wiring board 100 according to the present embodiment, the capacitor 20 is built in very close to the IC chip 1 to effectively remove noise, and the signal lines and the like can have the same structure as the conventional one. it can.

  In the above description, the capacitor 20 has the bottom dielectric layer 24D provided with the cutout portion 20P by reducing the planar dimension of only one layer. However, a plurality of dielectric layers on the capacitor lower surface 20B side are shown. By reducing the plane dimension of the step, the step of the notch 20P can be increased. Further, the step of the notch 20P can be increased by making the bottom dielectric layer 24D thicker than the other dielectric layers 24, or by changing the thickness of the plurality of dielectric layers.

Next, the manufacturing method of the wiring board 100 will be described including the manufacturing method of the capacitor 20 and the core substrate body 10 which are individual members. First, a method for manufacturing the capacitor 20 will be described with reference to FIG. First, as shown in FIG. 3A, a number of high dielectric ceramic green sheets (hereinafter also simply referred to as “sheets”) 124 mainly composed of BaTiO ₃ powder are manufactured by a known green sheet manufacturing technique. Next, as shown in FIG. 3B, via holes 124H penetrating between the front and back surfaces 124A and 124B are formed at predetermined positions of the sheet 124 by punching.

  Further, as shown in FIG. 3C, the via holes 124H of each sheet 124 are filled with Pd paste to form unsintered via conductors 126, 127, 128, and further, the upper surface 124A side of each sheet 124 Then, unfired electrode layers 125E and 125F having a predetermined shape made of Pd paste are formed. Of these, one unfired electrode layer 125E is connected to the left and right two of the unfired via conductors 126 and 127 formed in FIG. 3C, and is connected to the unfired via conductors 126 and 127 at the center. It is formed in a pattern that does not. On the other hand, the other unfired electrode layer 125F is formed in a pattern that is connected to the unfired via conductor 126 at the center among the three unfired via conductors 126 formed and not connected to the left and right ones. Yes.

Note that the vias 126 and 127 that are not connected to the unfired via pads 125E or 125F are not connected above the unfired via conductors 126 and 127 in order to ensure that the via conductors are brought into contact with each other in the vertical direction at the time of later-described lamination. The cover pad 129 is preferably formed simultaneously with the fired electrode layers 125E and 125F.
In addition, the unfired dielectric layer 124D that is stacked on the top in the stacking described below is formed to have a slightly smaller dimension than the other unfired dielectric layers 124, and both of the unfired electrode layers 125E and 125F are formed. Instead, only the cover pad 122 is formed above each unfired via conductor 128.
Further, as will be described below, the non-fired electrode layer 125FD having a slightly smaller outer shape than the other non-fired electrode layers 125F is also formed on the non-fired dielectric layer 124D.

Next, as shown in FIG. 3D, the sheets 124 on which the unfired electrode layers 125E are stacked and the sheets 124 on which 125F (125FD) are stacked are stacked so as to be alternately stacked. Then, on the top, neither of the unfired electrode layers 125E and 125F is formed, and a sheet 124D in which only the cover pad 122 is formed is laminated, and these are pressed to form the laminated body 120. As a result, the unfired dielectric layers 124 and the unfired electrode layers 125E and 125F are alternately stacked, and the unfired electrode layers 125E and 125F are alternately disposed. Further, the unfired electrode layers 125E and 125E are connected to each other via unfired via conductors 126 and 127, respectively. Similarly, the unfired electrode layers 125F and 125F are also connected to each other via unfired via conductors 126 and 127, respectively. Connected. In addition, the group of unfired electrode layers 125E and the group of 125F are not in contact with each other and are insulative from each other.
Further, only the planar dimensions of the unfired dielectric layer 124D are made smaller than those of the other unfired dielectric layers 124, so that a stepped notch 120P is formed around the upper surface of the laminate 120 in the drawing. .

  Thereafter, the laminated body 120 is turned upside down to form a cover pad on the upper surface of the laminated body 120 where the unfired via conductor 127 is exposed, and then the laminated body 120 is fired (simultaneously fired). The capacitor 20 shown is formed. Since the capacitor 20 is formed in this way, for example, it is not necessary to form a common electrode for connecting to the electrode layer 25E or 25F on the side surface of the dielectric layer 24 after firing, and it is used as a capacitor immediately after firing. be able to. The via conductors 26, 27, and 28 (unfired via conductors 126, 127, and 128) are formed on the dielectric layer 24 in consideration of the positions of the upper and lower via conductors and the distance between adjacent via conductors 24. It can be formed at any position in the plane.

Accordingly, the ease of routing the upper capacitor connection wiring 60 and the lower capacitor connection wiring 70, the number of flip chip pads 101 connected to the upper capacitor connection wiring 60, the number of LGA pads 103 connected to the lower capacitor connection wiring 70, and the like. Accordingly, the positions and numbers of the upper surface connection pads 21 and the lower surface connection pads 22 can be arbitrarily selected and formed. The upper surface connection pad 21 or the lower surface connection pad 22 made of Pd is subjected to Ni—Au plating, Cu plating, or the like in consideration of the connectivity with the wiring layer 45 made of Cu or solderability. You can also. In addition, a solder resist layer made of ceramic, resin, or the like may be formed around the upper surface connection pad 21 and / or the lower surface connection pad 22 by a known method.

  The completed capacitor 20 has the presence or absence of a short circuit, the capacitance value, the insulation resistance value between the electrode groups 25E and 25F, the conduction between the upper surface connection pads 21 and the lower surface connection pads 22, and the electrode groups 25E and 25F. Various checks such as an insulation check are performed, and the defective capacitor 20 is discarded. Thereby, the danger of using the capacitor | condenser 20 with a malfunction at the process mentioned later can be reduced.

  Next, the core substrate body 10 and the manufacturing method thereof will be described. The core substrate body 10 is first brought into the state shown in FIG. 4 before the capacitor 20 is built therein. That is, the core substrate body 10 shown in FIGS. 4 (a) and 4 (b) has a substantially square plate shape in plan view, and has a substantially square-shaped through hole 11 at a substantially center. The through hole 11 is slightly smaller in the vicinity of the lower end thereof, and when viewed in plan from the core substrate upper surface 10A side, the through hole 11 has a substantially square through hole (inner peripheral edge) slightly smaller than this. ) The capacitor receiving portion 12 having 12H is exposed. As shown in FIG. 4B, the core substrate body 10 has a core substrate body upper surface 10A and a core substrate body lower surface 10B, and is a core substrate body 13 for a receiving portion made of a glass-epoxy resin composite material. Similarly, a wall core substrate body 16 made of a glass-epoxy resin composite material is adhered to the adhesive layer 17. Between the core substrate main body upper surface 10A and the core substrate main body lower surface 10B, the through hole 16H that penetrates the wall core substrate main body 16 and the receiving core substrate main body 13 pass, and have a diameter slightly larger than the through hole 16H. The capacitor built-in through-hole 11 is formed by the through-hole 13H having a small directional dimension.

  Therefore, at the lower end side of the through hole 11 in the figure, the vicinity of the peripheral edge of the through hole 13H protrudes inward in the plane direction (left and right direction in the figure) from the through hole 16H, and has an inner peripheral edge 12H (through hole 13H). A capacitor receiving portion 12 is configured. The inwardly facing surface (upper surface in the figure) 12S of the capacitor receiving portion 12 is in contact with the contact surface 20C of the capacitor 20 when the capacitor 20 is built in, so that the shaft in the through hole 11 of the capacitor 20 is provided. The direction (vertical direction) can be determined. Further, the capacitor receiving portion 12, more specifically, the inner peripheral edge 12 </ b> H, is fitted with the notch portion 20 </ b> P of the capacitor 20, thereby positioning in the planar direction (left-right direction) in the through hole 11 of the capacitor 20. Can do. On the other hand, the outward surface (lower surface in the drawing) 12T of the capacitor receiving portion 12 coincides with the core substrate main body lower surface 10B.

  The core substrate body 10 is not formed with a core through-hole conductor 33 penetrating between the core substrate body upper surface 10A and the core substrate body lower surface 10B. This is because the core through-hole conductor 33 is formed after the capacitor 20 is built in and fixed in the through hole 11 of the core substrate body 10.

  The core substrate body 10 is manufactured as follows. That is, first, as shown in FIG. 5 (a), it is made of a glass-epoxy resin composite material, and has a receiving portion core substrate main body upper surface 13A and a receiving portion core substrate main body lower surface 13B. The receiving portion core substrate body 13 having a through hole 13H is prepared. The through hole 13H has a size slightly smaller than a through hole 16H described below. The through hole 13 may be formed by a known method, and examples thereof include a drill, punching, and laser.

On the other hand, as shown in FIG. 5B, a wall core substrate body 16 is prepared which is also made of a glass-epoxy resin composite material and is thicker than the receiving portion core substrate body 13. In the wall core substrate body 16, a substantially square through hole 16 </ b> H is formed in advance at the center position corresponding to the through hole 11 by punching or the like.

  Next, as shown in FIG. 5C, the receiving portion core substrate main body upper surface 13A and the wall core substrate main body lower surface 16B are made of a semi-cured epoxy resin, and are fitted to the through holes 16H. It is sandwiched through an adhesive sheet 17R molded in a letter shape, heated and pressed. Thereby, both 13 and 16 are adhere | attached through the contact bonding layer 17, and the core substrate main body 10 shown in FIG. 4 can be created.

  In order to create the core substrate body 10 having the through hole 11 having the receiving portion 12 as in the present embodiment, the receiving portion core substrate body 13 in which the vicinity of the inner periphery of the through hole 13H becomes the receiving portion 12 in advance The through-hole 11 having the receiving portion 12 is publicly known by manufacturing separately from the large-diameter portion other than the receiving portion 12, that is, the wall core substrate body 16 constituting most of the through-hole 11 and then bonding them together. By this method, it can be formed with easy and accurate dimensions. Therefore, the core substrate body 10 can be formed at a low cost.

  Next, a process of forming the core through-hole conductor 33 by incorporating the capacitor 20 in the core substrate body 10 will be described. First, as shown in FIG. 6A, the above-described capacitor 20 is disposed in the through hole 11 of the core substrate body 10 with the capacitor lower surface 20B facing down. Then, as described above, the contact surface 20C of the capacitor 20 contacts the inward surface 12S of the receiving portion 12, and the receiving portion 12, more specifically, the inner peripheral edge 12H and the notch portion 20P are fitted. Thus, positioning in the vertical direction and the planar direction in the through hole 11 of the capacitor 20 can be performed.

  Thereafter, as shown in FIG. 6B, in addition to the inside of the through-hole 11, epoxy resin is applied on the core substrate main body upper surface 10A and the capacitor upper surface 20A, on the core substrate main body lower surface 10B and the capacitor lower surface 20B (lower in the drawing). Filling resin 32 as a main component is injected, applied, and cured. Thereby, the capacitor 20 is fixed with the filling resin 32 (32A) in the through hole 11 while being in contact with and fitted to the receiving portion 12, and is embedded in the core substrate body 10, and is subjected to heat, vibration, or the like. In addition, problems such as misalignment between the core substrate body 10 and the capacitor 20 are prevented.

  Further, as shown in FIG. 6C, the filling resin layers 32B and 32C on the core substrate main body upper surface 10A and the capacitor upper surface 20A are polished to a flat surface to expose the upper surface connection pad 21, and the upper surface connection pad. 21 and the filling resin layers 32B and 32C left on the capacitor upper surface 20A and the core substrate body upper surface 10A are substantially flush with each other. Similarly, the filling resin layers 32D and 32E on the core substrate main body lower surface 10B and the capacitor lower surface 20B are polished to a flat surface to expose the lower surface connection pad 22, and the lower surface connection pad 22, the capacitor lower surface 20B, and the core. The filling resin layers 32D and 32E left on the lower surface 10B of the substrate body are leveled with each other. In the core board with a built-in capacitor thus formed, the through hole 11 is formed in the core board body 10 and the generation of the step due to the built-in capacitor 20 is absorbed, and the resin insulating layer 41 to be formed later is absorbed. , 51, etc. and the wiring layers 45, 55, etc., are not distorted by steps, and problems such as disconnection and short circuit are not caused. Further, since the influence of the step on the flip chip pad 101 (or the flip chip bump 102) and the LGA pad 103 is eliminated, the coplanarity of the flip chip pad 101 and the LGA pad 103 can be improved.

Further, as shown in FIG. 7, at the periphery of the through hole 11 of the core substrate body 10, between the core substrate body upper surface 10A and the core substrate body lower surface 10B, and further, the upper surface 32CU of the filling resin layer 32C and the filling resin A core through-hole hole 30H penetrating between the lower surface 32ED of the layer 32E is formed by a drill. In the case where it is desired to reduce the hole diameter and the interval, it is preferable to perform drilling with a laser (CO ₂ , YAG, etc.).

  Next, a core through-hole conductor 33 made of Cu is formed in and around the core through-hole hole 30H by a known through-hole conductor forming method. Note that connection wirings 34 and 35 extending from the core through-hole conductor 33 and connecting to the wiring layers 45 and 55 are also formed on the filling resin layer upper surface 32CU and the filling resin layer lower surface 32ED. Further, the upper surface connection pad 21 that is flush with the filling resin layer 32B and the lower surface connection pad 22 that is flush with the filling resin layer 32D are also increased in thickness by Cu plating or above the filling resin layer 32B. The resin layer 32D protrudes downward. In this manner, a capacitor built-in core substrate (hereinafter also simply referred to as a core substrate) 30 is formed.

  In addition to the core substrate body 10, the core substrate 30 includes a capacitor 20 in the through hole 11. However, the core substrate upper surface 30A (filled resin layer upper surface 32CU) and the core substrate 30B (filled resin layer lower surface 32ED) have a core through-hole conductor 33 penetrating between them at a predetermined portion, or the upper surface connection terminal 21 and the lower surface. The connection terminals 22 and the connection wirings 34 and 35 are formed, and the core substrate upper surface 30A and the core substrate lower surface 30B are flattened. Therefore, it can be used in the same manner as a core substrate used for a normal wiring board without a built-in capacitor.

  A specific method for manufacturing the core through-hole conductor 33 is, for example, as follows. That is, first, after the through-hole hole 30H is drilled in the core substrate body 10 (see FIG. 6C), electroless Cu plating is applied to the entire surface, and the inside of the through-hole 30H, the filling resin layer upper surface 32CU, and the filling resin An electroless Cu plating layer is formed on the layer lower surface 32ED. Thereafter, a dry film is pasted on the upper surface 32CU of the filled resin layer and the lower surface 32ED of the filled resin layer (lower in the figure), exposed and developed to open electrolytic plating forming portions such as the periphery of the core through-hole hole. Further, an electroless Cu plating layer is used as a common electrode to conduct an electrolytic Cu plating, and after removing the dry film, an unnecessary electroless Cu plating layer is removed by soft etching to remove the core through-hole conductor 33 and the connection wiring. 34, 35, etc. are formed. The upper surface connection pad 21 and the lower surface connection pad 22 are also subjected to electroless Cu plating and electrolytic Cu plating.

  In addition, in this embodiment, the core through-hole conductor 33 is formed in a substantially cylindrical shape formed on the inner periphery and the peripheral edge of the core through-hole hole 30H, but the inside is filled with a filling resin, and the upper and lower sides thereof are plated layers. You may make it obstruct | occlude. In this way, since the wiring layers 45 and 55 and the core through-hole conductor 33 can be directly connected without using the connection wirings 34 and 35, the intervals between the core through-hole conductors 33 are formed with high density. Can do.

  In this state, that is, as will be described later, before the resin insulating layer and the wiring layer are formed on the core substrate 30 in which the capacitor 20 is embedded, it is preferable to inspect the characteristics of the capacitor 20 incorporated. In the state of being built in the core substrate 30, the presence or absence of a short circuit, the capacitance value, the insulation resistance value between the pair of electrode groups 25 </ b> E and 25 </ b> F, the upper surface connection pads 21 and the lower surface through-hole conductors 12 Various inspections such as continuity or insulation with the electrode groups 25E and 25F are performed, and the core substrate 30 in which the defective capacitor 20 is built is discarded. As a result, it becomes clear that the capacitor 20 has a defect after forming a resin insulating layer and a wiring layer that require man-hours as will be described later, and the entire wiring board 100 with high added value has to be discarded. Sex can be reduced.

Thereafter, the core substrate 30 is used to form a resin insulating layer and a wiring layer using a known resin insulating layer forming technique and wiring layer forming technique, and the wiring board 100 may be formed.
In the present embodiment, the following processing is performed before forming the resin insulating layer. That is, as shown in FIG. 8A, in addition to the inside of the core through-hole conductor 33, the filling resin layers 32B and 32C, the upper surface connection pads 21 and the connection wirings 34, and the filling resin layers 32D and 32E. A flattening resin 36, 37, 38 mainly composed of an epoxy resin is filled and applied below the lower surface, the lower surface connection pad 22, and the connection wiring 35, and then cured. Alternatively, first, the core through-hole conductor 3
3 may be filled with the planarizing resin 36 and cured, and then planarized resins 37 and 38 may be applied and cured.

  Further, as shown in FIG. 8B, the upper or lower surfaces of the planarizing resins 37 and 38 are polished to be flattened. At the same time, the upper surface connection pad 21, the core through-hole conductor 33 and the connection wiring 34 are exposed substantially flush with the planarizing resin layer 37. Further, the lower surface connection pad 22, the core through-hole conductor 33, and the connection wiring 35 are exposed to be substantially flush with the planarizing resin layer 38. As a result, the upper surface connection pad 21, the lower surface connection pad 22, the core through-hole conductor 33, the connection wirings 34, 35, and the like are formed so as to protrude from the core substrate upper surface 30A or the core substrate lower surface 30B. It is possible to eliminate the influence of the resin insulating layers 41 and 51 and the wiring layers 45 and 55 and the like. Therefore, it is possible to prevent disconnection or short circuit of the wiring layer 45 or the like, or to improve the coplanarity of the flip chip pad 101 or the LGA pad 103.

Thereafter, a photosensitive film mainly composed of an epoxy resin is attached to the upper surface 37U of the planarizing resin layer 37 and the lower surface 38D of the planarizing resin layer 38. Further, exposure and development are performed to form via holes 41VH and 51VH in which the upper surface connection pad 21, the lower surface connection pad 22, the connection wirings 34 and 35, etc. are exposed on the bottom surface, and the photosensitive film is cured to obtain FIG. 9A. As shown in FIG. 2, resin insulation layers 41 and 51 are formed. Note that the via holes 41VH and 51VH may be drilled using a laser (CO ₂ , YAG, etc.) after the resin insulating layers 41 and 51 are formed of a resin having no photosensitivity.

  Furthermore, electroless Cu plating is applied, a dry film is pasted, exposed and developed, and only an electrolytic plating layer forming portion is opened. An electroless Cu plating layer is formed in the opening using the electroless Cu plating layer as a common electrode. After the removal, an unnecessary electroless Cu plating layer is removed by soft etching. As a result, as shown in FIG. 9B, via portions 45V and 55V that penetrate through the resin insulating layers 41 and 51 into the via holes 41VH and 51VH, respectively, and connect to the upper surface connection pad 21, the lower surface connection pad 22, and the like, respectively. The wiring layers 45 and 55 are formed so as to be insulated from each other. The wiring layers 45 and 55 are arranged between the resin insulating layers 41 and 42 or between the resin insulating layers 51 and 52 when the resin insulating layers 42 and 52 are further formed thereon.

  Thereafter, the resin insulating layers 42 and 52, the wiring layers 46 and 56, the flip chip pad 101, the resin insulating layers (solder resist layers) 43 and 53 are sequentially formed in the same manner, and further the flip exposed from the resin insulating layer 43. A solder paste is applied to the chip pad 101 and reflowed to form a flip chip bump 102 made of solder. In this way, the wiring board 100 shown in FIG. 1 is completed. Note that a Ni—Au plating layer may be formed on the surface of the LGA pad 103 to prevent oxidation.

  In the present embodiment, after the capacitor 20 is built in the through hole 11 of the core substrate body 10 and fixed with the filling resin 32, the upper or lower surfaces of the filling resin layers 32B, 32C, 32D, and 32E are polished and leveled. Further, even after the core through-hole conductor 33 and the like were formed, the upper surface or the lower surface of the planarizing resin layers 37 and 38 was polished and leveled. For this reason, the level difference caused by incorporating the capacitor 20 in the through hole 11 is eliminated, and further, the level difference caused by the protrusion of the core through-hole conductor 33, the upper surface connection pad 21, etc. is also eliminated. It is also possible to improve the disconnection or short-circuiting, and the coplanarity of the flip chip pad 101, the flip chip bump 102, and the LGA pad 103.

In the present embodiment, as described above, the resin insulating layers 41, 42, 43, 51, 52, 53 are formed by the photolithography technique using the photosensitive resin film, and the wiring layer 4
5,55 were formed by the so-called semi-additive process. However, the resin insulating layer 41 and the like may be formed by other methods such as applying a resin paste, and the wiring layer 45 and the like may be formed by a subtractive method, a full additive method, and other methods. That is, the resin insulating layer 41 and the wiring layer 45 and the like may be formed by any known method.

(Embodiment 2)
Next, a wiring board 200 according to the second embodiment will be described with reference to FIG. In the wiring substrate 100 of the first embodiment, the receiving portion 12 formed in the through hole 11 of the core substrate body 10 incorporating the capacitor 20 is formed at the lower end portion of the through hole 11 in the drawing. On the other hand, in the wiring board 200 of this embodiment, the capacitor receiving portion 212 is formed at the upper end portion in the figure of the capacitor built-in through hole 211 of the core substrate body 210 in which the capacitor 220 is built. Different. Further, a contact surface 220C and a notch 220P are formed on the upper surface 220A side of the capacitor 220, the inward surface (lower surface in the figure) 212S of the receiving portion 212 and the contact surface 220C are in contact with each other, and the receiving portion 212 is cut. The difference is that the notch 220P is fitted. Furthermore, although it differs in that the connection wiring 234 extends to the outward surface (upper surface in the drawing) 212T of the receiving portion 212 in the core substrate main body upper surface 210A, the other points are the same, so the different portions are the center. Explanation will be given, and explanation of similar parts will be omitted or simplified.

  The wiring substrate 200 has a large number of flip chip pads 101 and flip chip bumps 102 for connection with the IC chip 1 indicated by broken lines formed on the upper surface 200A of the wiring substrate. On the other hand, many LGA pads 103 are formed on the lower surface 200B of the wiring board. Furthermore, the wiring board 200 penetrates the resin insulation layer between the core board body 210 containing the capacitor 220, the resin insulation layers 41, 42, 43, 51, 52, 53 stacked above and below them. Each wiring layer 60, 70, 80, 90 is formed.

  Among these, the core substrate main body 210 has a substantially square plate shape in plan view, is made of a glass-epoxy resin composite material, and has a capacitor built-in through-hole 211 having a substantially square shape in plan view that passes through the top and bottom of the core substrate body 210. At the upper end of the through hole 211 in the figure, a capacitor receiving part 212 is formed that protrudes radially inward of the through hole 211 and whose inner peripheral edge 212H is substantially square. A capacitor 220 is built in the through hole 211. In addition, a large number of core through-hole conductors 233 that penetrate between the core substrate main body upper surface 210A and the core substrate main body lower surface 210B are formed on the peripheral edge of the core substrate main body 210. In addition, a connection wiring 234 extending from the core through-hole conductor 233 to the upper surface 212T of the receiving portion 212 is formed on the core substrate main body upper surface 210A. On the other hand, a connection wiring 235 extending from the core through-hole conductor 233 is formed on the core substrate main body red surface 210B.

The capacitor 220 has the same material and structure as those of the capacitor 20 described in the first embodiment. However, the capacitor 220 is just upside down, that is, the contact surface 220C and the notch 220P are on the capacitor upper surface 220A side. This is a formed multilayer ceramic capacitor (see FIGS. 2A, 2B, and 2C). That is, the periphery of the capacitor upper surface 220A is a stepped notch 220P, which is lowered by one step to form the contact surface 220C. Similar to the capacitor 20, the capacitor upper surface 220 </ b> A and the capacitor lower surface 220 </ b> B are provided with a large number of upper surface connection pads 221 and lower surface connection pads 222, respectively, and the capacitor upper surface 220 </ b> A and the capacitor lower surface 220 </ b> B are provided by these pads 221 and 222. In the figure, it can be connected upward or downward in the figure.
Thereby, the capacitor 220 built in the core substrate body 210 can be connected by the upper surface connection pad 221 in the upper part of the drawing and by the lower surface connection pad 222 in the lower part of the drawing. Further, the capacitor 220 is fixed in the through hole 211 by a filling resin 232 made of an epoxy resin, and is integrated with the core substrate body 210.

  Further, as in the first embodiment, three upper resin insulating layers 41, 42, and 43 mainly composed of an epoxy resin are provided above the core substrate main body upper surface 210A and the capacitor upper surface 220A. On the other hand, the lower resin insulation layers 51, 52, and 53 are also provided below the core substrate main body lower surface 210B and the capacitor lower surface 220B. Further, between the upper resin insulating layers 41 and 42 and between the upper resin wiring layers 42 and 43, wiring layers 45 and 46 made of Cu plating are formed so as to penetrate the upper resin insulating layers 41 and 42, respectively. . Similarly, wiring layers 55 and 56 made of Cu plating are formed between the lower resin insulating layers 51 and 52 and between the lower resin wiring layers 52 and 53, respectively, through the lower resin insulating layers 51 and 52. ing.

  Among these, the wiring layers 45 and 46 respectively connecting the flip chip pad 101 and the upper surface connection pad 221 corresponding thereto constitute the upper capacitor connection wiring 60, and the flip chip pad 101 and the corresponding core through hole conductor 33. The wiring layers 45 and 46, respectively, constitute an upper core connection wiring 80. On the other hand, the wiring layers 55 and 56 respectively connecting the lower surface connection pad 222 of the capacitor 20 and the corresponding LGA pad 103 constitute the lower capacitor connection wiring 70, and the core through-hole conductor 33 and the corresponding LGA pad 103. The wiring layers 55 and 56 that connect to each other constitute a lower core connection wiring 90.

Thereby, the IC chip 1 connected to the flip chip bump 102 is connected to the pair of electrodes of the capacitor 220, respectively. Further, the LGA pad 103 is connected to a pair of electrodes of the capacitor 220, respectively.
Therefore, the power supply potential and the ground potential supplied from the motherboard connected to the LGA pad 103 are the lower capacitor connection wiring 70, the capacitor 220, the upper capacitor connection wiring 60, the flip chip pad 101, and the flip chip bump from the LGA pad 103. Through 102, the IC chip 1 can be supplied. Further, noise superimposed on the power supply potential and the ground potential can be removed by the capacitor 220.

  In addition, since the capacitor 220 is built in the core substrate body 210, it can be disposed very close to the IC chip 1, so that the length of the upper capacitor connection wiring 60 can be shortened. Therefore, the noise removal capability by the capacitor 220 can be further enhanced. In particular, in the present embodiment, since the capacitor 220 is arranged directly under the IC chip 1 and therefore directly under the flip chip pad 101, the length of the upper capacitor connection wiring 60 can be extremely shortened. Accordingly, since the distance between the IC chip 1 and the capacitor 220 can be made extremely short, noise is hardly superimposed between them, and this is particularly effective for noise removal.

  A large number of upper capacitor connection wirings 60 are formed in parallel. Similarly, a large number of lower capacitor connection wirings 70 are also formed. For this reason, the resistance and inductance of the upper capacitor connection wiring 60 and the lower capacitor connection wiring 70 are reduced as a whole, and this is also advantageous for noise removal.

On the other hand, the wiring connecting the IC chip 1 and the mother board without connecting to the capacitor 220 such as a signal line is connected from the flip chip pad 101 to the core through-hole conductor 33 through the upper core connection wiring 80 and the connection wiring 234, The lower core connection wiring 90 is connected to the LGA pad 103 through the substrate body 210. This structure is the same as that of a normal build-up wiring board using a core board on which through-hole conductors are formed.
As described above, the wiring board 200 of the present embodiment also incorporates the capacitor 220 in the immediate vicinity of the IC chip 1 to effectively remove noise, and the signal line and the like can have the same structure as before. it can.
In addition, in the present embodiment, the connection wiring 234 may extend to the outward surface (upper surface in the drawing) 212T of the receiving portion 212. When such connection wiring 234 is formed, it becomes possible to connect to the upper core connection wiring 80 even in the vicinity of the upper surface connection pad 221, and the degree of freedom of wiring can be further improved.

  In this wiring board 200, the capacitor 220 and the core board body 210 similar to the capacitor 20 and the wiring board body 10 of the first embodiment are manufactured, the capacitor 220 is built in the core board body 210, and turned upside down. Since it can be manufactured by forming the resin insulating layer 41 and the like, the wiring layer 45 and the like as in the first embodiment, detailed description thereof will be omitted.

In the above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to the above embodiments, and it is needless to say that the present invention can be appropriately modified and applied without departing from the gist thereof.
For example, in the above embodiment, a glass-epoxy resin composite material is used as the material of the core substrate body 10, more specifically, the core substrate body 13 for receiving portion and the core substrate body 16 for wall portion. May be selected in consideration of heat resistance, mechanical strength, flexibility, ease of processing, and the like. Therefore, for example, glass fiber-resin composite material of glass fiber such as glass woven fabric and glass nonwoven fabric and resin such as epoxy resin, polyimide resin, BT resin, and composite material of organic fiber and resin such as polyamide fiber, continuous A resin-resin composite material in which a fluororesin having a three-dimensional network structure such as PTFE having pores is impregnated with a resin such as an epoxy resin can be used.

In addition, the resin insulating layer 41 or the like is mainly composed of an epoxy resin, but may be appropriately selected in consideration of heat resistance, pattern formability, and the like. For example, polyimide resin, BT resin, PPE resin, Examples thereof include a resin-resin composite material obtained by impregnating a resin such as an epoxy resin into a fluororesin having a three-dimensional network structure such as PTFE having continuous pores.
Similarly, the wiring layer 45 and the like are formed by electroless Cu plating and electrolytic Cu plating, but may be formed by other materials, for example, Ni, Ni-Au, and the like. The wiring layer 45 or the like may be formed by a technique such as applying a functional resin.

  In the above embodiment, for connection to the IC chip 1, a large number of flip chip pads 101 and flip chip bumps 102 are provided on the wiring substrate upper surfaces 100 </ b> A and 200 </ b> A. However, as an IC connection terminal, an appropriate form may be selected according to the terminal formed on the IC chip to be connected. In addition to a flip chip bump formed, only a flip chip pad, or a wire Examples include a bonding pad and a TAB connection pad.

In the above-described embodiment, one through hole is provided in the approximate center of the core substrate body. However, it is not necessary to form in the approximate center, and a plurality of through holes are provided as necessary to incorporate a capacitor. You may do it. Conversely, in order to deal with a plurality of power supply potentials, a plurality of capacitors may be built in one through hole.
Further, as the capacitor 20, a multilayer ceramic capacitor in which a dielectric layer 24 and an electrode layer 25 are stacked substantially parallel to the capacitor upper surface 20A and the capacitor lower surface 20B is shown. However, the built-in capacitor only needs to have the upper surface connection pad 21 and the lower surface connection pad 22 formed on the capacitor upper surface 20A and the capacitor lower surface 20B. For example, the dielectric layer and the electrode layer are substantially orthogonal to the capacitor upper surface. The stacking direction and internal structure of the capacitors can be changed as appropriate, such as being stacked in the direction. In the first embodiment, the via conductors 26, 27, and 28 formed in the capacitor are all formed at positions overlapping with other via conductors in the vertical direction (FIG. 2C). It is not necessary to limit the positions of the other via conductors above or below, and the arrangement or number of the via conductors 26 can be selected as appropriate.

Further, in the above embodiment, a high dielectric ceramic mainly composed of BaTiO ₃ is used for the dielectric layer 24, but the material of the dielectric layer is not limited to this, and for example, PbTiO ₃ , PbZrO ₃ , TiO _2. , SrTiO ₃ , CaTiO ₃ , MgTiO ₃ , KNbO ₃ , NaTiO ₃ , KTaO ₃ , RbTaO ₃ , (Na _1/2 Bi _1/2 ) TiO ₃ , Pb (Mg _1/2 W _1/2 ) O ₃ , ( K _1/2 Bi _1/2 ) TiO _{3 and the} like, and may be appropriately selected according to the required capacitance of the capacitor.
Further, although Pd is used for the electrode layer 25, the via conductor 26, and the like, it may be selected in consideration of compatibility with the material of the dielectric layer, for example, Pt, Ag, Ag-Pt, Ag- Pd, Cu, Au, Ni etc. are mentioned.
Furthermore, a capacitor is obtained by combining a dielectric layer mainly composed of a high dielectric ceramic, an electrode layer made of Ag-Pd, etc., and a via conductor or wiring layer made of a resin layer, Cu plating, Ni plating or the like. Can also be used.

  Further, in the above embodiment, after the capacitor 20 is built in the through-hole 11, the through-hole 11 is filled with the filling resin 32 (32A), the capacitor upper surface 20A, the core substrate main body upper surface 10A, and the capacitor lower surface. Filled resin layers 32B, 32C, 32D, and 32E were also formed on 20B and on the core substrate main body lower surface 10B (downward in the figure) (see FIG. 6). However, it is sufficient that the capacitor 20 can be fixed in the through-hole 11 with at least the filling resin 32 (32A). Therefore, the filling resin 32 may be injected only into the through hole 11.

  Alternatively, in addition to the filling resin 32 (32A), only the filling resin layers 32B and 32D on the capacitor upper surface 20A and the capacitor lower surface 20B may be formed. That is, the dimensions of the through hole 11 (receiving portion 12) and the capacitor 20 are adjusted, and the capacitor upper surface 20A is lower than the core substrate main body upper surface 10A (lower in the figure) in a state where the capacitor 20 is positioned in the through hole 11. In addition, the upper surface connection pad 21 is higher than the upper surface 10A of the core substrate body (upper in the drawing). In addition, the capacitor lower surface 20B is higher than the core substrate main body lower surface 10B (upper in the drawing), and the lower surface connection pad 22 is lower than the core substrate main body lower surface 10B (upper in the drawing). Next, in addition to injecting the filling resin 32 into the through hole 11, filling resin layers 32B and 32D are also formed on the capacitor upper surface 20A and the capacitor lower surface 20B, respectively. Thereafter, the upper surface connection pad 21 is exposed on the upper surface of the filling resin layer 32B, the upper surface is flush with the core substrate body upper surface 10A, and the lower surface connection pad 22 is exposed on the upper surface of the filling resin layer 32D. However, the lower surface may be leveled so as to be flush with the core substrate main body lower surface 10B. Even in this case, the step formed due to the presence of the through hole 11 and the built-in capacitor 20 can be eliminated, and further, when the upper resin insulating layer 41 or the like, the wiring layer 45 or the like is formed in the upper layer, the wiring layer 45 or the like is disconnected. Or a short circuit, or a decrease in coplanarity of the flip chip pad 101 or the like.

  In the above embodiment, the core through-hole conductor 33 is formed in the core substrate body 10 after the capacitor 20 is built in. However, the core through that penetrates between the core substrate body upper surface 10A and the core substrate body lower surface 10B in advance is formed. It is also possible to form a hole conductor and then incorporate the capacitor 20 in the through hole 11. That is, a through-hole penetrating between the core substrate main body upper surface 10A and the core substrate main body lower surface 10B after bonding the receiving portion core substrate main body 13 and the wall core substrate main body 16 (see FIGS. 4 and 5). And a core through-hole conductor is formed by a known method. Thereafter, the capacitor 20 is built in the through hole 11 in the same manner as described above. In this way, after incorporating the capacitor 20, it is possible to avoid the risk of causing defects such as cracks in the capacitor 20 or the filling resin 32 due to vibration or impact generated when the core through hole 30H is formed. it can.

Further, in the above embodiment, after the core through-hole conductor 33 and the connection conductors 34 and 35 are formed, the planarizing resins 36, 37, and 38 are formed so that the top and bottom of the core substrate 30 are flattened. However, the resin insulating layers 41 and 51 may be formed without using the planarizing resin, that is, from the state shown in FIG. 7, after the core through-hole conductor 33 is filled with resin. In this way, the wiring board can be formed at a lower cost.

Further, in the above-described embodiment, the capacitor receiving portions 12 and 212 are formed in the through holes 11 and 211, respectively, and the capacitors 20 and 220 in which the contact portions 20C and 220C and the cutout portions 20P and 220P are formed are received by the receiving portions. It abuts on the part 12 etc. and is fitted.
However, the capacitor 20 and the like can be positioned in the vertical direction in the figure only by contacting the receiving portion 12 and the like. For example, a wiring board 300 shown in Modification 1 in FIG. The wiring board 300 will be described. Unlike the capacitor 20 of the first embodiment, the built-in capacitor 320 is not formed with a notch, and is slightly thinner than the capacitor 20. The thickness of the lower surface connection pad 322 formed on the lower surface 320B is increased. On the other hand, the core substrate body 10 and others are substantially the same as the wiring substrate 100 of the first embodiment. In this wiring board 300, the inward surface 12S of the receiving portion 12 and the capacitor lower surface (contact surface) 320B are in contact with each other, whereby the capacitor 320 is positioned in the vertical direction in the figure. As a result, it is possible to easily prevent poor connection with the upper capacitor connection wiring 60 (wiring layer 45) and the lower capacitor connection wiring 70 (wiring layer 55) due to the vertical displacement of the capacitor 320, and to reliably connect with these. it can. Moreover, in the wiring board 300, the substantially rectangular parallelepiped capacitor 320 which does not form a notch part can be used, and since the manufacture of the capacitor 320 becomes easy and cheap, the wiring board 300 can also be made cheap. Note that the capacitor 320 may be positioned in the planar direction (left and right in the figure) using an appropriate jig and tool, and the capacitor 320 may be fixed in the through hole 11 with the filling resin 332.

  Furthermore, for example, the wiring board 400 shown in Modification 2 in FIG. 12 may be configured such that the receiving portion 12 or the like is not formed. In this wiring substrate 400, the diameter (planar dimension) of the through hole 411 having a substantially square shape in plan view formed between the upper surface 410A and the lower surface 410B of the core substrate body 410 does not change from the upper end to the lower end, and the receiving portion is Not formed. Further, the capacitor 420 incorporated in the through hole 411 has substantially the same thickness as that of the core substrate body 410, and unlike the capacitor 20 of the first embodiment, the capacitor 420 has a substantially rectangular parallelepiped shape in which notches are not formed. It is said that. In this wiring board 400, since the receiving part is not formed in the core substrate body 410, it is not necessary to bond the receiving part core substrate body 13 and the wall core substrate body 16 together as described in the first embodiment. It is sufficient to form the through hole 411 in the core substrate body 410 by a known method. In addition, the capacitor 420 can be a substantially rectangular parallelepiped having no notch, so that the capacitor 420 can be manufactured easily and inexpensively. Therefore, the wiring board 400 can be made more inexpensive. Note that the positioning of the capacitor 420 in the vertical direction and the planar direction (left and right direction in the drawing) may be performed using a tool as appropriate, and the capacitor 420 may be fixed in the through hole 411 with the filling resin 432.

Furthermore, in Embodiment 1, the shape of the receiving portion 12 of the core substrate body 10 is substantially constant over the entire circumference of the through hole 11 when viewed from the top of the core substrate body upper surface 10A as shown in FIG. Although it has a substantially square shape with a width, other shapes may be used.
For example, as in the core substrate body 510 shown in FIG. 13A, capacitor receiving portions 512A, 512B, 512C, and 512D that protrude from the four corners of the substantially square through hole 11 in a substantially “<” shape. 2 which protrudes along two opposing sides (in this example, two sides on the left and right sides) of the substantially square through-hole 11 like a core substrate body 520 shown in FIG. 13B. One having the strip-shaped capacitor receiving portions 522A and 522B formed therein may be mentioned. Further, like the core substrate body 530 shown in FIG. 13 (c), capacitor receiving portions 532A, 532B, 532C, and 532D protruding in a substantially trapezoidal shape are formed on the four sides of the substantially square through hole 11, respectively. And so on. These capacitor receiving parts 512, 522, 532
When the capacitor 20 is built in, the inward surfaces 512S, 522S, and 532S of the capacitor also come into contact with the contact surface 20C of the capacitor 20, and the capacitor receiving portions 512, 522, and 532, that is, the inner peripheral edges 512H, 522H, and 532H Since it fits into the notch 20P, positioning in the up-down direction and the planar direction in the through hole 11 of the capacitor 20 can be performed.

Further, in the first embodiment, the notch 20P is provided in a square shape on the periphery of the capacitor lower surface 20B (see FIG. 2B), but the notch is a capacitor receiving portion (for example, the receiving portion in the first embodiment). 12 (see FIG. 4)), other shapes may be used.
For example, a capacitor 540 shown in FIG. 14A is an example of a capacitor that fits into the receiving portion 522 of the core substrate body 520 (see FIG. 13B). In this capacitor 540, a notch 540P is provided in a stepped manner only in the portion along two opposing sides of the periphery of the capacitor lower surface 540B having a square shape in plan view, and a contact surface 540C is formed. Thereby, in the through hole 11 of the core substrate body 520, the contact surface 540C of the capacitor 540 and the inward surface 522S of the receiving portion 522 contact each other, and the inner peripheral edge 522H and the cutout portion 540P are fitted. . Even in this way, positioning in the axial direction and the radial direction in the through hole 11 of the capacitor 540 can be facilitated.

  Further, the capacitor may be provided with a protruding portion that protrudes from the lower surface of the capacitor instead of the notch portion, and may be fitted to the capacitor receiving portion. For example, a capacitor 550 shown in FIG. 14B is an example of a capacitor that fits into the receiving portion 512 of the core substrate body 510 (see FIG. 13A). In this capacitor 550, substantially rectangular convex portions 550TA, 550TB, 550TC, and 550TD are provided in the vicinity of the central portion of each side of the periphery of the capacitor lower surface 550B that is square in plan view. As a result, the capacitor lower surface (contact surface) 550B of the capacitor 550 and the inward surface 512S of the receiving portion 512 are in contact with each other in the through hole 11 of the core substrate body 510, and the inner peripheral edge 512H and the convex portions 550TA, etc. And fit. Even in this way, positioning in the axial direction and the radial direction in the through hole 11 of the capacitor 550 can be facilitated.

Similarly, a capacitor 560 shown in FIG. 14C is an example of a capacitor that fits into the receiving portion 532 of the core substrate body 530 (see FIG. 13C). In this capacitor 560, substantially house-shaped convex portions 560TA, 560TB, 560TC, and 560TD are provided in the vicinity of each corner portion of the periphery of the capacitor lower surface 560B that is square in a plan view. As a result, the capacitor lower surface (contact surface) 560B of the capacitor 560 and the inward surface 532S of the receiving portion 532 come into contact with each other in the through hole 11 of the core substrate body 530, and the inner peripheral edge 512H and each convex portion 560TA etc. are fitted. Even in this way, positioning in the axial direction and the radial direction in the through hole 11 of the capacitor 560 can be facilitated.
In addition, the shape of the receiving portion of the capacitor and the core substrate body is not limited to the above examples, and may be formed in a shape that contacts and fits with each other, such as those in which both the notch portion and the convex portion are formed. That's fine.

  As can be easily understood from the above description, if the capacitor receiving portion and the capacitor are shaped so that the inward surface of the receiving portion and the contact surface of the capacitor are in contact with each other, the upper and lower sides of the capacitor in the through hole Directional positioning can be performed. Still further, if the capacitor receiving portion and the capacitor are shaped so that the receiving portion (the inner peripheral edge of the receiving portion) and the notch of the capacitor are fitted to each other, the capacitor is positioned in the through hole in the planar direction. be able to.

According to the first embodiment, a capacitor receiving portion is formed at a lower end portion of a capacitor built-in through hole formed in the core substrate body, and a wiring that incorporates a capacitor that comes into contact with and fits into the through hole in the through hole It is sectional drawing of a board | substrate. (A) of the capacitor | condenser incorporated in the wiring board concerning Embodiment 1 is a top view, (b) is the perspective view seen from the lower surface side, (c) is sectional explanatory drawing for demonstrating the internal structure of a capacitor | condenser, (d) FIG. 4 is a circuit diagram showing a relationship between a capacitor, an LGA pad, and a flip chip pad. It is explanatory drawing explaining the manufacturing method of the capacitor | condenser of FIG. In the wiring board concerning Embodiment 1, (a) top view and (b) partial expanded sectional view of a core substrate body which has a penetration hole for embedding a capacitor. It is explanatory drawing explaining the manufacturing method of the core substrate main body of FIG. FIG. 5 is an explanatory diagram of a manufacturing method of a capacitor built-in core substrate in which the capacitor of FIG. 2 is built in the through hole of the core substrate body of FIG. 4. It is a partial expanded sectional view of a core board with a built-in capacitor. It is explanatory drawing explaining the process of further planarizing the upper and lower surfaces of the capacitor built-in core substrate of FIG. FIG. 9 is an explanatory diagram illustrating a process of forming a resin insulating layer and wiring layers on the upper and lower sides of the flattened capacitor built-in core substrate of FIG. 8. According to the second embodiment, a capacitor receiving portion is formed at the upper end portion of the capacitor built-in through hole formed in the core substrate body, and a wiring that incorporates a capacitor that comes into contact with and fits in the receiving portion in the through hole. It is sectional drawing of a board | substrate. Sectional drawing of the wiring board which includes the capacitor | condenser receiving part in the lower end part of the through-hole for capacitor | condenser built in the core board | substrate body concerning the modification 1, and incorporates the capacitor | condenser which contacts this receiving part in this through-hole It is. FIG. 11 is a cross-sectional view of a wiring board according to Modification 2 in which a capacitor is built in a capacitor built-in through hole formed in a core substrate body. It is a top view which shows the other form of the capacitor | condenser receiving part of a core board body. It is a perspective view which shows the other form of the notch part and convex part of a capacitor | condenser. It is explanatory drawing explaining the mode of the capacitor | condenser connection wiring in the conventional wiring board which mounted the capacitor on the upper surface and the lower surface.

Explanation of symbols

100, 200, 300, 400 (Built-in capacitor) Wiring board 100A, 200A, 300A, 400A Wiring board upper surface 100B, 200B, 300B, 400B Wiring board lower surface 101 Flip chip pad 102 Flip chip bump 103 LGA pad (lower surface connection terminal)
10, 210, 410 Core substrate body 10A, 210A, 410A Core substrate body upper surface 10B, 210B, 410B Core substrate body lower surface 11, 211, 411 Capacitor built-in through hole 12, 212 Capacitor receiving portion 20, 220, 320, 420 Capacitor 20A, 220A, 320A, 420A Capacitor upper surface 20B, 220B, 320B, 420B Capacitor lower surface 21, 221, 321, 421 Upper surface connection pad 22, 222, 322, 422 Lower surface connection pad 24 Dielectric layer 25 Electrode layers 25E, 25F (pair) Electrode group 30 Core substrates 32, 232, 332, 432 Filling resin 32B, 32C, 32D, 32E Filling resin layer 33, 233 Core through-hole conductors 41, 42, 43, 51, 52, 53 Resin insulating layers 45, 46 , 55, 56 Wiring layer 6 0 Upper capacitor connection wiring 70 Lower capacitor connection wiring 80 Upper core connection wiring 90 Lower core connection wiring

Claims (5)

A wiring board having a wiring board upper surface and a wiring board lower surface, and having a plurality of IC connection terminals for connecting to an IC chip on the wiring board upper surface and a plurality of lower surface connection terminals on the lower surface of the wiring board, and having a built-in capacitor. Because
Core substrate top surface,
The bottom surface of the core substrate body,
A capacitor built-in through-hole penetrating between the upper surface of the core substrate body and the lower surface of the core substrate body;
And a plurality of core through-hole conductors formed between the upper surface of the core substrate body and the lower surface of the core substrate body,
A core substrate body comprising:
Capacitor top surface,
Capacitor bottom,
A pair of electrodes or electrode groups insulated from each other;
A plurality of upper surface connection pads formed on the upper surface of the capacitor and respectively conducting with any one of the electrodes or electrode groups of the pair of electrodes or electrode groups, each of the pair of electrodes or electrode groups including the plurality of electrodes; A plurality of upper surface connection pads in electrical communication with at least one of the upper surface connection pads;
And a plurality of lower surface connection pads formed on the lower surface of the capacitor and respectively conducting with any one of the electrodes or electrode groups of the pair of electrodes or electrode groups, both of the pair of electrodes or electrode groups being the above A plurality of bottom surface connection pads that are electrically connected to at least one of the plurality of bottom surface connection pads;
With
Built-in and fixed in the capacitor built-in through hole of the core substrate body, and the capacitor,
One or more upper resin insulation layers laminated above the core substrate main body upper surface and the capacitor upper surface;
One or more lower resin insulation layers stacked below the lower surface of the core substrate body and the lower surface of the capacitor;
A plurality of upper capacitor connection wirings that respectively connect the plurality of IC connection terminals on the upper surface of the wiring board and the plurality of upper surface connection pads of the capacitor corresponding thereto through the upper resin insulating layer or through the layers;
A plurality of lower capacitor connection wirings that respectively connect the plurality of lower surface connection pads of the capacitor and the plurality of lower surface connection terminals on the lower surface of the wiring board corresponding thereto through the lower resin insulating layer or through the layers;
A plurality of upper cores that respectively connect the plurality of IC connection terminals on the upper surface of the wiring board and the corresponding core through-hole conductors on the upper surface of the core substrate body through the upper resin insulating layer or through the layers. Connection wiring,
A plurality of lower core connection wirings that respectively connect the core through-hole conductors on the lower surface of the core substrate body and the corresponding lower surface connection terminals on the lower surface of the wiring substrate through the lower resin insulating layer or through the layers. When,
Equipped with a,
At least a part of the plurality of IC connection terminals is located above the capacitor and is connected to an upper surface connection pad of the capacitor through an upper capacitor connection wiring . The wiring board according to claim 1,
The core substrate body includes a capacitor receiving portion that protrudes radially inward at either end of the capacitor built-in through-hole,
The wiring board, wherein the capacitor is in contact with an inward surface of the capacitor receiving portion. The wiring board according to claim 2,
The capacitor is formed with at least one of a notch and a protrusion on the periphery of the surface on the side of the capacitor upper surface and the capacitor lower surface that comes into contact with the capacitor receiving portion,
The wiring board, wherein the capacitor is fitted into the capacitor receiving portion by at least one of the cutout portion and the convex portion. The wiring board according to claim 1,
The core substrate body is a wiring substrate in which the dimension in the planar direction of the capacitor built-in through hole does not change from the upper end to the lower end. The wiring board according to claim 4,
The capacitor has a thickness that is substantially the same as the thickness of the core substrate body.

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