1293236 九、發明說明： 【發明所屬之技術領域】 本發明係有關於疊壓式電路基板（iaminated eireuit substrate)之製造技術，特別係有關於一種嵌埋有電子元件 之基板製造方法。 【先前技術】 在電子組裝技術中，常見各式電子元件係表面接合 φ (SMT)於一基板或一印刷電路板之上，例如被動元件。該 電子元件通常外露於基板或印刷電路板之接合表面，然其 電性傳遞至基板之路徑甚長，例如藉由錫膏、導腳、銲線 等達到電性互連。已知的一種作法係將嵌入式被動元件製 作於一基板上，其係在基板形成槽穴、電容膜、電阻膜等 構件，再將電容或電阻材料填入其槽穴，以在基板内部形 成被動元件，由於在基板内所形成之被動元件為非標準化 規格，因此有無法先行測試之風險，僅能在基板製成後再 修進行測試，才可確定嵌入式被動元件是否為良好，且基板 的厚度誤差變化亦會影響篏入式被動元件之品質。相關的 習知技術已揭露於本國專利證號第231〇2〇號「内嵌被動 元件之半導體封裝基板及其製作方法」。 美國專利公告2005/0〗22698號所揭示之技術為，將已 製備之被動70件與晶片嵌埋於一模組板（m〇dde 之 孔穴内，並以增層（build-up)方式形成一介電填充物質 (dielectric filling material)，以覆蓋被動元件與晶片。被 動元件/晶片與該模組板之線路層之電性連接方式則利用 1293236 微孔結構（microvias)連接，通常微孔結構之形成須藉由雷 射鐵孔技術方可達成。然而當介電物質覆蓋該些被動元件 之電極端與肖晶片之銲墊之冑，要製作能位在正確位置之 微孔有其困難度。此外，該些被動元件之電極端與該晶片 1銲墊位在不同之高度而非共平面，所需形成之微孔深度 白不相同，右形成之微孔深度太淺則無法顯露出該些被動 元件之電極Μ與該晶片之銲墊，或是微孔之深度太深則會 損傷該些被動元件與該晶片。 【發明内容】 本發明之主要目的係在於提供一種嵌埋有電子元件 之基板製造方法及其基板構造，首先，提供一具有圖案化 金屬層與谷置孔之核心板以及提供一電子元件，該電子 兀件之至少一電極端係可設有一凸塊，之後，將該電子元 件放置於該核心板之該容置孔中，一介電樹脂係形成於該 核心板與該電子元件上，該介電樹脂係顯露該凸塊，一圖 • f化金屬層形成於該介電樹脂上，並藉由該凸塊電性連接 至該電子元件之對應電極端，以提昇組裝性、互連可靠度 (interconnection reiiability)與電性效能，並且增加後續封 裝密度以及降低串音效應（cross-talk effect)。 本發明之次一目的係在於提供一種嵌埋有電子元件 之基板製造方法及其基板構造，其中在該電極端上之該凸 塊係高於該核心板之該圖案化金屬層，並藉由一平坦化步 驟使該凸塊顯露於該核心板之一平坦面，以利該圖案化金 屬層之形成與電性連接。 .1293236 本發明之再一目的係在於提供一種喪埋有電子元件 之基板製造方法及其基板構造，其中形成於該核心板與該 電子元件上介電樹脂係以疊壓（laniinati〇n)方式形成，以低 成本形成該介電樹脂，使該電子元件之上下表面係被該介 電树月曰所包覆’以達到完整嵌埋、外觀一致之功效。此外， 該核心板之該容置孔係可為貫通孔，以使容置孔容易形成 並降低容置孔之製作成本。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of an iaminated eireuit substrate, and more particularly to a method of manufacturing a substrate in which an electronic component is embedded. [Prior Art] In electronic assembly technology, various types of electronic components are commonly surface-bonded φ (SMT) on a substrate or a printed circuit board, such as a passive component. The electronic component is usually exposed on the bonding surface of the substrate or the printed circuit board, but the electrical path to the substrate is very long, for example, by solder paste, lead pins, bonding wires, and the like. A known method is to fabricate an embedded passive component on a substrate, which is formed on a substrate to form a cavity, a capacitor film, a resistive film, etc., and then fill a capacitor or a resistive material into the cavity to form inside the substrate. Passive components, because the passive components formed in the substrate are non-standardized specifications, there is a risk that they cannot be tested first. Only after the substrate is fabricated, the test can be performed to determine whether the embedded passive components are good and the substrate Variations in the thickness error also affect the quality of the intrusive passive components. Related art has been disclosed in the National Patent No. 231 〇 2 「 "Semiconductor package substrate with embedded passive components and its fabrication method". The technique disclosed in U.S. Patent Publication No. 2005/0, No. 22,698, discloses that the prepared passive 70 pieces and the wafer are embedded in a module board (m〇dde hole) and formed in a build-up manner. a dielectric filling material to cover the passive component and the wafer. The electrical connection between the passive component/wafer and the circuit layer of the module board is connected by 1293236 microvias, usually microporous structure The formation must be achieved by the laser iron hole technology. However, when the dielectric material covers the electrode end of the passive component and the pad of the Xiao wafer, it is difficult to make the micropore in the correct position. In addition, the electrode ends of the passive components are at different heights from the wafer 1 but not the coplanar, and the depth of the micropores to be formed is different from white, and the depth of the micropores formed on the right is too shallow to reveal the The electrode of the passive component and the pad of the wafer, or the depth of the micropore is too deep, which damages the passive component and the wafer. SUMMARY OF THE INVENTION The main object of the present invention is to provide an embedded electronic The substrate manufacturing method and the substrate structure thereof, firstly, providing a core plate having a patterned metal layer and a valley hole and providing an electronic component, wherein at least one electrode end of the electronic component can be provided with a bump, and then The electronic component is placed in the receiving hole of the core board, a dielectric resin is formed on the core board and the electronic component, and the dielectric resin reveals the bump, and a metal layer is formed. On the dielectric resin, and electrically connected to the corresponding electrode end of the electronic component by the bump to improve assembly, interconnection reiiability and electrical performance, and increase subsequent packaging density and reduce The second object of the present invention is to provide a method for fabricating a substrate embedded with electronic components and a substrate structure thereof, wherein the bump on the electrode end is higher than the core plate The patterned metal layer is exposed to a flat surface of the core plate by a planarization step to facilitate formation and electrical connection of the patterned metal layer. 1293236 A further object of the present invention is to provide a substrate manufacturing method for embedding electronic components and a substrate structure thereof, wherein a dielectric resin formed on the core plate and the electronic component is formed in a lamination manner. The dielectric resin is formed at a low cost, so that the upper surface of the electronic component is covered by the dielectric tree rafter to achieve complete embedding and uniform appearance. In addition, the accommodating hole of the core plate It can be a through hole to make the receiving hole easy to form and reduce the manufacturing cost of the receiving hole.
本發明之再一目的係在於提供一種嵌埋有電子元件 之基板製造方法及其基板構造，其中嵌埋於該基板内部之 該電子70件係為表面接合型被動元件（SMD type passive component)，特別是選用 〇2(H、〇4〇2、〇6〇3、〇8〇5、ι〇〇5、 1206之規格品被動元件，因此不需要在基板内部自行製作 被動元件導致品質不一致的問題。 本發明之另一目的係在於提供一種嵌埋有電子元件 之基板製造方法及其基板構造，其中，該電極端之一側面 係被覆有-絕緣膜’以利在該電極端上電鍍形成該凸塊。 本發明之另一目的係在於提供一種嵌埋有電子元件 之基板製造方法，一電子元件係放置於一覆銅荡板 cladlaminated，CCL)内，再以疊壓方式形成—介電樹脂， 以覆蓋該核心板與該電子元件，#彳 ^便得該電子疋件為嵌埋型 態0 本發明之另一目的係在於提供一種嵌埋有電子元件 之基板製造方法，其中該雷早士姓， Τ該電子兀件之至少-電極端上係設 置有一凸塊，且在疊壓形成介電樹脂之步驟中，卩一上壓 7 1)93236 板壓附該介電樹脂於該核心板與該電子元件上，且該上壓 板係具有至少一讓位孔，其係對準於該凸塊，並使該凸塊 顯露於該介電樹脂，以利一圖案化金屬層之連接。 依據本發明，一種嵌埋有電子元件之基板製造方法主 要包含以下步驟：提供一電子元件，其係具有複數個電極 端，其中至少一電極端係可設置有一凸塊；提供一核心 板，其係具有一圖案化金屬層以及一容置孔；設置該電子 Φ 兀件於該容置孔中，並形成一介電樹脂於該核心板與該電 子疋件上，以覆蓋該圖案化金屬層而顯露該凸塊；較佳 地，可進行一平坦化該介電樹脂之步驟，以確保該凸塊顯 露於該介電樹脂；之後，濺鍍一圖案化金屬層於該介電樹 月曰上，並藉由顯露之該凸塊電性連接至對應電極端。 【實施方式】 本發明之第一具體實施例係揭示一種嵌埋有電子元 件之基板製造方法。首先，如第1Α圖所示，提供一電子 兀件ίο，其係具有複數個電極端丨丨。該電子元件係可 為預先製備之被動元件或是半導體晶片。在本實施例中， 該電子兀件10係為表面接合型被動元件（SMD type passive component)，可選自於 〇2〇1、〇4〇2、〇6〇3、〇8〇5、 1005、1206之規格品被動元件。所提供之電子元件1〇係 具有有大量取得、低成本且標準化規格之優點，而不需要 在基板内自行製作。如第1B圖所示，在本實施例中，該 些電極端11之至少一電極端係可設置有一凸塊12。該凸 塊12係為電鍍开> 成之鋼凸塊（Cu b㈣p)或金凸塊（Au 8 1293236 bump)，該凸塊12係可形成於該些電極端u之上表面、 下表面或是上、下表面皆形成有該凸塊12。當該電子元件 1〇以電鍍形成該凸塊12時’係可在該些電極端丨丨之側面 先打被覆有一絕緣膜13，以限制該凸塊12之電鍍形成方 向。 如第2A圖所示，提供一核心板2〇。在本實施例中， 該核心板20係為一覆銅箔板（c〇ppej： “以 • CCL)，該核心板20係包含一核心層21與至少一銅箔。例 如，該核心板20係可為雙層鋼箔之架構，其上、下表面 分別貼附有一第一銅箔22與一第二銅箔23 ^之後，請參 閱第2B圖，對該核心板20進行一顯影蝕刻工程（或稱黃 光製程）’使得該第一銅箔22成形為一具有線路結構之第 一圖案化金屬層24或/且該第二銅箔23成形為一具有線路 結構之第一圖案化金屬層2 5，以供訊號傳遞。當該第一銅 箔22或該第二銅箔23係作為一接地層或一電源層時，則 春 不需要進行顯影蝕刻。之後，請參閱第2C圖，進行一挖 槽（routing)步驟，以使該核心板20形成有一容置孔26。 在本實施例中’該容置孔26係為貫通孔，其係可利用一 機械鑽孔工具之鑽頭30鑽穿該核心板2〇以形成該容置孔 26 〇 如第2D圖所示’汉置該電子元件1 〇於該核心板 之該容置孔26中，並形成一介電樹脂50於該核心板2〇 與該電子元件10上，以至少覆蓋該第一圖案化金屬層24, 且該介電樹脂50係顯露該些該些電極端u或/及該凸塊 1293236 12。較佳地，該介電樹脂50係以疊壓（lamination)方式形 成，以降低該介電樹脂5 0之製作成本且使該介電樹脂5 0 可容易地大面積形成於該核心板20與該電子元件1 〇上。 在疊壓步驟中，可以一預先塗覆有該介電樹脂50之上壓 板41與一預先塗覆有該介電樹脂50之下壓板42上下擠 壓該已設置有該電子元件10之該核心板20，以使該介電 樹脂5 0形成於該核心板20與該電子元件1 〇上，較佳地， 在該上壓板41與該介電樹脂50之間以及在該下壓板42 與該介電樹脂50之間可分別形成一離型膜（release film)(圖未繪出），以利在疊壓步騍之後，該上壓板41與該 下壓板42可輕易地脫離該介電樹脂50。此外，該上壓板 41係可具有複數個讓位孔41 a，在疊壓步驟時該些讓位孔 41 a係對準於該凸塊12，以利疊壓步驟後顯露出該凸塊i 2 或/及該些該些電極端11。在疊壓步驟之後，該介電樹脂 50係至少覆蓋該核心板20之第一圖案化金屬層24。在本 實施例中，該介電樹脂50另覆蓋該核心板2〇之該第二圖 案化金屬層25以及該電子元件1〇之上、下表面。此外， 該電子元件10之厚度可大於該核心板20之厚度，在疊壓 步驟之後，該凸塊12係高於該核心板20之該第一圖案化 金屬層24。 較佳地，請參閱第2E圖，可進行一平垣化該介電樹 脂50之步驟，其係可藉由機械研磨或化學機械研磨 (CMP)，以確定該凸塊12或/及該些電極端u顯露於該介 電樹脂50,在本實施例中，經平坦化之該介電樹脂5q係 1293236 具有一平坦表面5i，該凸塊12或/及該些電極端u係顯 露於該介電樹脂50之該平坦表面5卜此外，在平坦化步 驟之後，將有利於濺鍍工程之進行。 如第2F圖所示，在本實施例中，可形成至少一鍍通 孔 60(Plated Through Hole，PTH)，該鍍通孔 6〇 係貫穿該 核心板20與該介電樹脂50，以電性導通不同層之金屬線 路。請參閱第2G圖，通常該鍍通孔6〇係為鑽孔形成之貫 通孔且其孔壁係鍍有金屬層。 如第2G圖所示，濺鍍一圖案化金屬層71於該介電樹 脂50上，該圖案化金屬層71係藉由該凸塊12電性連接 至對應於該些凸塊12下方之該電極端u。在本實施例中， 關於該圖案化金屬層71之線路圖案形成方式係可先形成 一光阻72於該介電樹脂5〇之該平坦表面51，經曝光顯影 形成圖案之後，再以濺鍍方式形成該圖案化金屬層71於 該光阻72之鏤空區内，之後再移除該光阻72。另一方弋 則可先全面激鑛一金屬層於該平坦表面51，經顯影與餘^ 步驟以形成該圖案化金屬層71。另，在本實施例中，當需 要製作具有四層線路層之基板時，則可在該核心板之 下方形成另一圖案化金屬層71，。 接著，如第2H圖所示，可形成一電鍍層73於該此圖 案化金屬層71、71，上，以增加線路厚度。之後， 第 21 圖所示’可形成一銲罩層80(solder mask)於該電錢居 與該介電樹脂50上。該銲罩層80係設有開口以顯露該電 鍍層73。接著，可形成一鎳金鍍層90於該電鍍層73 之顯 π 1293236 露部位，以製得一嵌埋有該電子元件丨〇之基板。 因此，依據本發明之嵌埋有電子元件之基板製造方 法，利用該電子ΜΠ)之至少—電極端u設置有該凸塊 12,以利在形成該介電樹月旨5〇之後與該圖案化金屬層^ 電性連接，而達到該被嵌埋之該電子元件1〇與該圖案化 金屬層71間之電性連接。此外，所提供之該電子元件1 〇 與核心板20均可大量且規袼化及低成本取得。並且平坦 • 化該介電樹脂50之步驟係可以確保該凸塊12或/及該些電 極端11連接該圖案化金屬層71，以使該圖案化金屬層71 電性連接至該電子元件10，因此可以提昇組裝性、互連可 靠度（interconnection reliability)與電性效能、增加後續封 裝密度以及降低串音效應（cr〇ss_talk effect)。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 • 圍。 【圖式簡單說明】 第1A圖：依據本發明之第一具體實施例，所提供之一電 子元件之截面示意圖。 第1B圖·依據本發明之第一具體實施例，該電子元件於 3又置有凸塊後之截面示意圖0 第2A圖：依據本發明之第一具體實施例，所提供之一核 心板之截面示意圖。 第2B圖：依據本發明之第一具體實施例，該核心板於形 12 .Ϊ293236 成圖案化金屬層後之截面示意圖。 2C圖：依赭士找 蘇本發明之第一具體實施例，該核心板於形 成容置孔時之戴面示意圖。 第2D圖：伊μ 士 、骤本發明之第一具體實施例，該核心板於容 置有該電子元件並於疊壓時之截面示意圖。 Ε圖，依據本發明之第一具體實施例，該嵌埋有電子 元件之核心板於平坦化一介電樹脂容置後之截 參 面不意圖。 第2F圖：依據本發明之第一具體實施例，該嵌埋有電子 元件之核心板於形成艘通孔後之截面示意圖。 第2G圖：依據本發明之第一具體實施例，該嵌埋有電子 元件之核心板於形成一圖案化金屬層後之截面 不意圖。 第2H圖·依據本發明之第-*"具體實施例，該篏埋有電子 元件之核心板於形成一電鍍層後之截面示意 • 圖。 第21圖：依據本發明之第一具體實施例，該嵌埋有電子元 件之核心板於形成一銲罩層與一鎳金鍍層後之 截面示意圖。 【主要元件符號說明】 10 電子元件 11 電極端 12 凸塊 13 絕緣Μ 20 核心板 21 核心層 22 第一鋼箔 23 第二銅箔 24 第一薗案化金屬層 13 1293236 25 第二圖案化金屬層 26 容置孔 30 鑽頭 41 上壓板 41a 讓位孔 42 下壓板 50 介電樹脂 51 平坦表面 60 鍍通孔 71 圖案化金屬層 72 光阻 7Γ 圖案化金屬層 73 電鍍層 80 銲罩層 90 鎳金鍍層 14A further object of the present invention is to provide a method for fabricating a substrate embedded with an electronic component and a substrate structure thereof, wherein the electron 70 embedded in the substrate is a SMD type passive component. In particular, the passive components of 〇2 (H, 〇4〇2, 〇6〇3, 〇8〇5, ι〇〇5, 1206 are selected, so there is no need to make passive components inside the substrate to cause inconsistent quality. Another object of the present invention is to provide a method for manufacturing a substrate embedded with an electronic component and a substrate structure thereof, wherein one side of the electrode end is covered with an insulating film to facilitate plating on the electrode end. Another object of the present invention is to provide a method for manufacturing a substrate embedded with an electronic component, wherein an electronic component is placed in a clad laminated, CCL), and then laminated to form a dielectric resin. In order to cover the core board and the electronic component, the electronic component is embedded. The other object of the present invention is to provide a substrate embedded with electronic components. The method of manufacturing, wherein the Lei Xianshi surname, at least the electrode end of the electronic component is provided with a bump, and in the step of laminating the dielectric resin, the upper pressing 7 1) 93236 plate is attached The dielectric resin is on the core board and the electronic component, and the upper pressure plate has at least one retaining hole aligned with the bump, and the bump is exposed to the dielectric resin to facilitate The connection of the patterned metal layers. According to the present invention, a substrate manufacturing method for embedding an electronic component mainly comprises the steps of: providing an electronic component having a plurality of electrode terminals, wherein at least one of the electrode terminals is provided with a bump; and a core plate is provided. Having a patterned metal layer and a receiving hole; the electron Φ is disposed in the receiving hole, and a dielectric resin is formed on the core plate and the electronic component to cover the patterned metal layer And exposing the bump; preferably, a step of planarizing the dielectric resin may be performed to ensure that the bump is exposed to the dielectric resin; and then, a patterned metal layer is sputtered on the dielectric tree And is electrically connected to the corresponding electrode end by the exposed bump. [Embodiment] A first embodiment of the present invention discloses a substrate manufacturing method in which an electronic component is embedded. First, as shown in Fig. 1, an electronic component ίο is provided which has a plurality of electrode terminals. The electronic component can be a passive component or a semiconductor wafer prepared in advance. In this embodiment, the electronic component 10 is a SMD type passive component, and may be selected from the group consisting of 〇2〇1, 〇4〇2, 〇6〇3, 〇8〇5, 1005. 1,1206 specifications passive components. The electronic components provided are advantageous in that they have a large number of acquisitions, low cost, and standardized specifications, and do not need to be fabricated in the substrate. As shown in FIG. 1B, in the embodiment, at least one electrode end of the electrode terminals 11 may be provided with a bump 12. The bump 12 is a plated steel bump (Cu b (four) p) or a gold bump (Au 8 1293236 bump), and the bump 12 can be formed on the upper surface or the lower surface of the electrode ends u or The bumps 12 are formed on both the upper and lower surfaces. When the electronic component 1 is formed by electroplating to form the bump 12, an insulating film 13 may be first coated on the side of the electrode terminal to limit the plating formation direction of the bump 12. As shown in Fig. 2A, a core board 2 is provided. In this embodiment, the core board 20 is a copper clad board (c〇ppej: "CCL"), and the core board 20 includes a core layer 21 and at least one copper foil. For example, the core board 20 The structure may be a double-layer steel foil. After the first copper foil 22 and the second copper foil 23 are respectively attached to the upper and lower surfaces, please refer to FIG. 2B to perform a development etching process on the core board 20. (or called a yellow light process) 'make the first copper foil 22 into a first patterned metal layer 24 having a line structure or / and the second copper foil 23 is shaped as a first patterned metal having a line structure The layer 2 5 is for signal transmission. When the first copper foil 22 or the second copper foil 23 is used as a ground layer or a power supply layer, the development etching is not required in spring. After that, please refer to FIG. 2C. A routing step is performed to form the accommodating hole 26 in the core plate 20. In the embodiment, the accommodating hole 26 is a through hole, which is a drill bit 30 which can utilize a mechanical drilling tool. Drilling through the core plate 2 to form the receiving hole 26, as shown in FIG. 2D, the electronic component 1 is placed And a dielectric resin 50 is formed on the core plate 2 and the electronic component 10 to cover at least the first patterned metal layer 24, and the dielectric resin is disposed in the receiving hole 26 of the core plate. The 50 series exposes the electrode terminals u or/and the bumps 1293236 12. Preferably, the dielectric resin 50 is formed by lamination to reduce the manufacturing cost of the dielectric resin 50 and The dielectric resin 50 can be easily formed on the core board 20 and the electronic component 1 on a large area. In the laminating step, the press plate 41 and a pre-coating layer of the dielectric resin 50 can be pre-coated. The core plate 20 on which the electronic component 10 is disposed is pressed up and down by the pressing plate 42 under the dielectric resin 50, so that the dielectric resin 50 is formed on the core plate 20 and the electronic component 1 Preferably, a release film (not shown) is formed between the upper platen 41 and the dielectric resin 50 and between the lower platen 42 and the dielectric resin 50, respectively. After the lamination step, the upper platen 41 and the lower platen 42 can be easily separated from the dielectric resin 50. The upper pressing plate 41 can have a plurality of retaining holes 41 a. The retaining holes 41 a are aligned with the protruding blocks 12 during the laminating step to expose the bumps i 2 or And the electrode terminals 11. After the lamination step, the dielectric resin 50 covers at least the first patterned metal layer 24 of the core plate 20. In the embodiment, the dielectric resin 50 further covers the The second patterned metal layer 25 of the core board 2 and the upper and lower surfaces of the electronic component 1 . Further, the thickness of the electronic component 10 may be greater than the thickness of the core board 20, after the stacking step, the convex The block 12 is higher than the first patterned metal layer 24 of the core board 20. Preferably, referring to FIG. 2E, a step of planarizing the dielectric resin 50 may be performed by mechanical grinding or chemical mechanical polishing (CMP) to determine the bump 12 or/and the electricity. The terminal u is exposed to the dielectric resin 50. In the embodiment, the planarized dielectric resin 5q 1293236 has a flat surface 5i, and the bump 12 or/and the electrode terminals u are exposed to the dielectric layer The flat surface 5 of the electro-resin 50, in addition, will facilitate the sputtering process after the planarization step. As shown in FIG. 2F, in the embodiment, at least one plated through hole (PTH) is formed, and the plated through hole 6 is penetrated through the core plate 20 and the dielectric resin 50 to be electrically Conducting metal lines of different layers. Referring to Fig. 2G, the plated through hole 6 is usually a through hole formed by drilling and the hole wall is plated with a metal layer. As shown in FIG. 2G, a patterned metal layer 71 is sputtered on the dielectric resin 50, and the patterned metal layer 71 is electrically connected to the underside of the bumps 12 by the bumps 12 Electrode end u. In this embodiment, the circuit pattern of the patterned metal layer 71 can be formed by first forming a photoresist 72 on the flat surface 51 of the dielectric resin 5, after forming and patterning by exposure and development, and then sputtering. The patterned metal layer 71 is formed in the hollow region of the photoresist 72, and then the photoresist 72 is removed. The other side may first fully excite a metal layer on the flat surface 51, and develop and form a patterned metal layer 71. Further, in the present embodiment, when it is required to fabricate a substrate having four wiring layers, another patterned metal layer 71 may be formed under the core plate. Next, as shown in Fig. 2H, a plating layer 73 may be formed on the patterned metal layers 71, 71 to increase the thickness of the wiring. Thereafter, a solder mask 80 may be formed on the electric resin to be placed on the dielectric resin 50. The solder mask layer 80 is provided with an opening to expose the plating layer 73. Then, a nickel gold plating layer 90 is formed on the exposed portion of the plating layer 73 to form a substrate in which the electronic component is embedded. Therefore, according to the method for fabricating an electronic component-embedded substrate of the present invention, at least the electrode terminal u is provided with the bump 12 so as to facilitate the formation of the dielectric tree after the formation of the dielectric tree The metal layer is electrically connected to achieve electrical connection between the embedded electronic component 1 and the patterned metal layer 71. In addition, the electronic component 1 〇 and the core board 20 provided can be obtained in a large amount and at a low cost. And the step of planarizing the dielectric resin 50 ensures that the bumps 12 or/and the electrode terminals 11 are connected to the patterned metal layer 71 to electrically connect the patterned metal layer 71 to the electronic component 10. Therefore, assembly, interconnection reliability and electrical performance, increased subsequent package density, and reduced crosstalk effect (cr〇ss_talk effect) can be improved. The scope of the present invention is defined by the scope of the appended claims. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention belong to the protection of the present invention. • Wai. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic cross-sectional view showing an electronic component according to a first embodiment of the present invention. 1B is a cross-sectional view of the electronic component after the bump is placed on the third embodiment according to the first embodiment of the present invention. FIG. 2A is a view showing a core board according to the first embodiment of the present invention. Schematic diagram of the section. 2B is a cross-sectional view showing the core plate in the shape of a patterned metal layer in accordance with a first embodiment of the present invention. 2C: According to the first embodiment of the invention, the core plate is a schematic view of the wearing surface when the hole is formed. 2D is a schematic cross-sectional view of the core board in which the electronic component is housed and laminated. In the first embodiment of the present invention, the core plate in which the electronic component is embedded is not intended to be planarized after the dielectric resin is housed. Fig. 2F is a cross-sectional view showing the core plate in which the electronic component is embedded after forming the through hole according to the first embodiment of the present invention. Fig. 2G is a cross-sectional view of the core plate in which the electronic component is embedded after forming a patterned metal layer according to the first embodiment of the present invention. Fig. 2H is a cross-sectional view of the core plate in which the electronic component is embedded after forming a plating layer in accordance with the present invention. Figure 21 is a cross-sectional view showing the core plate in which the electronic component is embedded after forming a solder mask layer and a nickel gold plating layer according to the first embodiment of the present invention. [Main component symbol description] 10 Electronic component 11 Electrode terminal 12 Bump 13 Insulation Μ 20 Core plate 21 Core layer 22 First steel foil 23 Second copper foil 24 First patterned metal layer 13 1293236 25 Second patterned metal Layer 26 accommodating hole 30 bit 41 upper platen 41a bit hole 42 lower plate 50 dielectric resin 51 flat surface 60 plated through hole 71 patterned metal layer 72 photoresist 7 图案 patterned metal layer 73 plating layer 80 solder mask layer 90 nickel Gold plating 14