JP5589314B2 - Manufacturing method of electronic component module - Google Patents
Manufacturing method of electronic component module Download PDFInfo
- Publication number
- JP5589314B2 JP5589314B2 JP2009150716A JP2009150716A JP5589314B2 JP 5589314 B2 JP5589314 B2 JP 5589314B2 JP 2009150716 A JP2009150716 A JP 2009150716A JP 2009150716 A JP2009150716 A JP 2009150716A JP 5589314 B2 JP5589314 B2 JP 5589314B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- flexible substrate
- hole
- connection terminal
- component module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims description 86
- 238000010438 heat treatment Methods 0.000 claims description 17
- 238000003384 imaging method Methods 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 17
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 229920005989 resin Polymers 0.000 description 11
- 239000011347 resin Substances 0.000 description 11
- 239000010419 fine particle Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002082 metal nanoparticle Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Wire Bonding (AREA)
Description
本発明は、表面実装用の電子部品をフレキシブル基板に搭載した電子部品モジュールの製造方法に関する。 The present invention relates to a method for manufacturing the electronic component module mounted with electronic components for surface mounting on the flexible substrate.
フレキシブルディスプレーやＲＦＩＤ(radio frequency identification)タグなどの新しい用途においては、絶縁基板（プリント配線基板）上に配線パターンを印刷し、この配線パターン上に表面実装用の電子部品を直接実装して電子部品モジュールを作製する試みがなされている。 In new applications such as flexible displays and RFID (radio frequency identification) tags, a wiring pattern is printed on an insulating substrate (printed wiring board), and electronic components for surface mounting are directly mounted on the wiring pattern. Attempts have been made to make modules.
印刷による配線パターンは、導電性粒子を含んだ接着材料を塗布することにより形成されるが、一般に導電粒子はＡｇ（銀）であり、電子部品をはんだ付けにより接続する場合、はんだ中へのＡｇの拡散により過度の金属間化合物を形成することで接続部の寿命が低下したり、拡散が著しい場合は配線パターンが消失したりするなどの問題がある。 The wiring pattern by printing is formed by applying an adhesive material containing conductive particles. Generally, the conductive particles are Ag (silver). When electronic parts are connected by soldering, Ag into the solder is used. By forming an excessive intermetallic compound by diffusion of the metal, there is a problem that the life of the connection portion is reduced, or when the diffusion is significant, the wiring pattern is lost.
また、フレキシブルディスプレーでは、絶縁基板上に有機半導体回路を形成し、有機半導体回路からの配線を印刷により形成するが、電子部品のはんだ接続で一般に用いられるリフローによる一括加熱では、はんだ融点以上の温度までフレキシブルディスプレー全体を加熱するため、有機半導体を破損させてしまう。 In flexible displays, an organic semiconductor circuit is formed on an insulating substrate, and wiring from the organic semiconductor circuit is formed by printing. However, with batch heating by reflow generally used for soldering electronic components, the temperature is higher than the solder melting point. Since the entire flexible display is heated, the organic semiconductor is damaged.
さらに、異方性導電接着剤による電子部品の接続方法もあるが、接続に適する厚みや硬度を有する配線パターンを印刷により形成することは難しい。 Furthermore, although there is a method for connecting electronic parts using an anisotropic conductive adhesive, it is difficult to form a wiring pattern having a thickness and hardness suitable for connection by printing.
このため、複数の貫通孔が穿設された絶縁基板と、接続電極を貫通孔に挿入又は当接させて絶縁基板の一主面に固定された表面実装用の電子部品と、絶縁基板の他主面に、その一部が表面実装用電子部品の接続端子と電気的に接触するよう形成された金属微粒子による配線パターンを形成し、金属微粒子による配線パターン上に金属めっき層を形成する技術が既に知られている（例えば、特許文献１参照。）。 Therefore, an insulating substrate having a plurality of through holes, a surface-mounting electronic component that is fixed to one main surface of the insulating substrate by inserting or abutting the connection electrode into the through hole, and other insulating substrates. There is a technology for forming a wiring pattern with metal fine particles formed on the main surface so that a part of them is in electrical contact with the connection terminals of the surface mount electronic component, and forming a metal plating layer on the wiring pattern with metal fine particles. It is already known (for example, refer to Patent Document 1).
しかし、特許文献１に開示された電子部品の接続方法では、たとえば１２０μｍ厚の基板を用いて、１２０μｍピッチの電子部品を実装する場合、貫通孔の幅は８０μｍ程度となり、絶縁基板の厚さと貫通孔の径との比（アスペクト比）が１以上となるため、スキージ等による印刷の場合、導電性ペーストが貫通孔内に十分に入り込まず、電子部品の接続端子との接続ができないなどの不具合が発生する。 However, in the electronic component connection method disclosed in Patent Document 1, when mounting a 120 μm pitch electronic component using, for example, a 120 μm thick substrate, the width of the through hole is about 80 μm, and the thickness of the insulating substrate and the penetration Since the ratio (aspect ratio) with the hole diameter is 1 or more, when printing with a squeegee, etc., the conductive paste does not sufficiently enter the through-holes and cannot be connected to the connection terminals of electronic components. Will occur.
また、インクジェット装置等による印刷でも、同様にアスペクト比が高くなることで充填不足が生じる。さらに、電子部品の接続端子間距離が短くなると、接続端子の幅が狭くなり、接続端子と絶縁基板の貫通孔との位置合わせが難しくなるという問題があった。 Further, even in printing by an ink jet apparatus or the like, insufficient filling occurs due to a similarly high aspect ratio. Further, when the distance between the connection terminals of the electronic component is shortened, there is a problem that the width of the connection terminal is narrowed and it is difficult to align the connection terminal and the through hole of the insulating substrate.
図９は、従来の電子部品モジュールの断面図である。
従来の電子回路モジュールでは、図９に示すように貫通孔１４の径がフレキシブル基板１１の厚さに対して十分でないときに、塗布された導電ペースト（金属微粒子）１５ａが接続端子１２の面まで十分に埋まらずに回路が導通しないという問題が生じる。
また、貫通孔１４を形成したフレキシブル基板１１と電子部品１３とを当接する際、狭い端子間距離（ピッチ）では、接続端子１２の面積が小さくなるため、位置ずれにより導電性ペースト１５が接続端子１２と接触せずに回路が導通しないという問題が生じる。
FIG. 9 is a cross-sectional view of a conventional electronic component module.
In the conventional electronic circuit module, as shown in FIG. 9, when the diameter of the
Further, when the
そこで、本発明の目的は、電子部品の接続端子と配線パターンとが十分に接続される電子部品モジュールの製造方法を提供することにある。 An object of the present invention is to provide a method of manufacturing an electronic component module in which the connection terminal of the electronic component and the wiring pattern is well connected.
上記課題を解決するため、請求項１記載の発明は、フレキシブル基板の一方の主面に表面実装用の電子部品の接続端子側を当接させた後、加熱・加圧することで前記電子部品を前記フレキシブル基板内に埋め込み、前記フレキシブル基板の他方の主面から前記接続端子まで貫通孔を形成し、前記接続端子から貫通孔を経て前記フレキシブル基板の他方の主面に導電性ペーストを塗布することで配線パターンを形成する電子部品モジュールの製造方法であって、前記フレキシブル基板に前記電子部品を埋め込んだ後、前記貫通孔を形成する際に、画像処理によって前記貫通孔の位置を補正すると共に、前記電子部品として固体撮像素子を用い、前記フレキシブル基板として絶縁体が透明なフレキシブル基板を用い、前記フレキシブル基板の前記電子部品の受光面側に光学部品を一体的に形成することを特徴とする。 In order to solve the above-mentioned problems, the invention according to claim 1 is characterized in that after the contact terminal side of the electronic component for surface mounting is brought into contact with one main surface of the flexible substrate, the electronic component is heated and pressurized. Embedded in the flexible substrate, forming a through hole from the other main surface of the flexible substrate to the connection terminal, and applying a conductive paste from the connection terminal to the other main surface of the flexible substrate through the through hole. in a method for manufacturing an electronic component module that forms a wiring pattern, after embedding the electronic component on the flexible substrate, when forming the through hole, thereby correcting the position of the through hole by the image processing , Using a solid-state imaging device as the electronic component, and using a flexible substrate with a transparent insulator as the flexible substrate, the flexible substrate Characterized by integrally forming an optical component on the light-receiving surface side of the electronic component.
本発明によれば、フレキシブル基板内に埋め込むことで電子部品の接続端子面とフレキシブル基板の回路面との間の厚さが薄くなり、貫通孔のアスペクト比を導電性ペーストの充填に適した値にすることができ、貫通孔の形成は電子部品を埋め込んだ後に実施するため、電子部品の接続端子の位置に合わせて貫通孔を形成することができるので、電子部品の接続端子と配線パターンとが十分に接続される。 According to the present invention, the thickness between the connection terminal surface of the electronic component and the circuit surface of the flexible substrate is reduced by embedding in the flexible substrate, and the aspect ratio of the through hole is a value suitable for filling the conductive paste. Since the through hole is formed after embedding the electronic component, the through hole can be formed in accordance with the position of the connection terminal of the electronic component. is Ru is well connected.
＜特 徴＞
本発明は、フレキシブル基板に狭ピッチの電子部品を接続するに際し、フレキシブル基板の回路が形成される面と反対側の面に電子部品を当接させ、加熱・加圧することで電子部品をフレキシブル基板内に埋め込み、フレキシブル基板に貫通孔を形成し、導電性ペーストを塗布（印刷）することを特徴とする。
<Features>
When connecting an electronic component with a narrow pitch to a flexible substrate, the present invention brings the electronic component into contact with the surface of the flexible substrate opposite to the surface on which the circuit is formed, and heats and presses the electronic component into the flexible substrate. It is embedded in, and a through-hole is formed in a flexible substrate, and a conductive paste is applied (printed).
次に図を参照して本発明の実施の形態について説明する。
＜電子部品モジュールの製造方法１＞
図１（ａ）〜（ｄ）は、本発明に係る電子部品モジュールの製造方法の一実施の形態を示す工程図である。
図１(a)において、フレキシブルな樹脂シートの少なくとも一方の主面に銅箔からなる配線パターンを貼り付けたフレキシブル基板１１の一方の主面（図１（ａ）の下側の面）１１ｂに表面実装用の電子部品（例えば集積回路、抵抗、コンデンサ等が挙げられる。）１３の接続端子１２側を当接させた後、加熱・加圧装置１０ａで加熱・加圧することで電子部品１３をフレキシブル基板１１内に埋め込む。すなわち、フレキシブル基板１１の回路形成面（配線パターン形成面）とは反対側の面（図１（ａ）の下側の面）１１ｂに、電子部品１３を、接続端子１２がフレキシブル基板１１に対向するように配置する。
尚、加熱・加圧装置１０ａは、図示しない昇降手段により昇降自在な加熱・加圧ヘッド１０−１ａと、加熱・加圧ヘッド１０−１ａの真下に配置され、被加熱・加圧体を載置するステージ１０−２ａと、を有している。
Next, an embodiment of the present invention will be described with reference to the drawings.
<Electronic component module manufacturing method 1>
1A to 1D are process diagrams showing an embodiment of a method for manufacturing an electronic component module according to the present invention.
In FIG. 1 (a), on one main surface (lower surface in FIG. 1 (a)) 11b of a
The heating / pressurizing
図１（ｂ）において、加熱・加圧装置１０ａで、フレキシブル基板１１を加熱・加圧しながら電子部品１３を、電子部品１３の接続端子１２と反対側の面とフレキシブル基板１１の樹脂シートの一方の主面１１ｂとが同一平面となるように埋め込む。
In FIG. 1 (b), the heating / pressurizing
図１（ｃ）において、加熱・加圧装置１０ａから外した電子部品１３の接続端子１２の位置の樹脂シートに対してレーザで貫通孔１４を形成する。
In FIG.1 (c), the through-
図１（ｄ）において、導電性ペースト１５を貫通孔１４内に充填（塗布もしくは印刷）する。
In FIG. 1 (d), the
ここで、フレキシブル基板１１の樹脂シートとしては、シート状の熱可塑性樹脂（ポリカーボネートなど）や、完全硬化前のシート状の熱硬化性樹脂（エポキシ樹脂など）が挙げられる。
導電性ペースト１５は、カーボン、銀、銅などの導電性を有する微粒子や金属ナノ粒子を、粘性を有する樹脂からなるバインダに混ぜたペーストである。導電性ペースト１５には加熱により硬化する熱硬化式、自然乾燥により硬化する蒸乾式、紫外線照射により硬化する紫外線硬化式がある。
導電性ペースト１５の塗布（印刷）方法は、インクジェットやマスク印刷により行われる。また、導電性ペースト１５を貫通孔１４に塗布した後、めっき処理により導電層を積層してもよい。
Here, examples of the resin sheet of the
The
The method for applying (printing) the
＜電子部品モジュールの製造方法２＞
図２（ａ）〜（ｄ）は、本発明に係る電子部品モジュールの製造方法の他の実施の形態を示す工程図である。
図２（ａ）〜（ｄ）に示した実施の形態の図１（ａ）〜（ｄ）に示した実施の形態との相違点は、目的のアスペクト比にするため、電子部品１３をフレキシブル基板１１内に完全に埋め込まないようにした点である。
この場合、加熱・加圧装置１０ｂのステージ１０−２ｂにフレキシブル基板１１の厚さに対して所望する値（電子部品１３の厚さ＋所望残基板厚−フレキシブル基板１１厚）だけ電子部品１１が収容できる空間（凹部）を設ける必要がある。
<Electronic component module manufacturing method 2>
2A to 2D are process diagrams showing another embodiment of a method for manufacturing an electronic component module according to the present invention.
The difference between the embodiment shown in FIGS. 2 (a) to 2 (d) and the embodiment shown in FIGS. 1 (a) to 1 (d) is that the
In this case, the
図２（ａ）〜（ｄ）に示した工程図に基づく製造方法自体は図１（ａ）〜（ｄ）と同様のため、説明は省略する。 The manufacturing method itself based on the process charts shown in FIGS. 2A to 2D is the same as that in FIGS.
図３は、電子部品と接続したフレキシブル基板に貫通孔を形成する装置についての説明図である。
フレキシブル基板に貫通孔を形成する装置は、例えばＸ−Ｙロボット２１に貫通孔形成用のレーザ装置及び撮影装置２０を搭載している。
撮影装置としてのカメラは、対象とするフレキシブル基板の絶縁シートの材質によって異なる。絶縁シートが透明性の高い材質であれば可視光用のカメラでよく、光透過性のない基板であれば装置下面に図示しないＸ線源を配置し、Ｘ線撮影が可能な撮像装置を用いるようにしてもよい。
FIG. 3 is an explanatory diagram of an apparatus for forming a through hole in a flexible substrate connected to an electronic component.
As an apparatus for forming a through hole in a flexible substrate, for example, a laser device for forming a through hole and an
A camera as a photographing apparatus differs depending on the material of the insulating sheet of the target flexible substrate. If the insulating sheet is made of a highly transparent material, a visible light camera may be used. If the insulating sheet is not a light transmissive substrate, an X-ray source (not shown) is disposed on the lower surface of the apparatus, and an imaging apparatus capable of X-ray imaging is used. You may do it.
＜フレキシブル基板への貫通孔の形成について＞
図４（ａ）、（ｂ）は、本発明に係る電子部品モジュールの電子部品と接続したフレキシブル基板に貫通孔を形成するための説明図である。
図３に示した装置に、電子部品１３を埋め込んだフレキシブル基板１１を電子部品１３が搭載された面とは反対側の面を上面として配置し、撮像装置により電子部品１３の端子位置を撮像し、画像処理により接続端子１２の位置を計測する。
計測された接続端子１２の位置情報に基づきレーザ装置で貫通孔１４を形成する（図４（ａ））。
<About the formation of the through hole in the flexible substrate>
4A and 4B are explanatory views for forming a through hole in a flexible substrate connected to the electronic component of the electronic component module according to the present invention.
In the apparatus shown in FIG. 3, the
A through
さらに、電子部品１３の接続端子１２の位置測定結果を元に、後述する導電性ペースト１５による配線およびフレキシブルディスプレー等の回路形成の位置合わせ用のアライメントマーク１７を形成する（図４（ｂ））。
Furthermore, based on the position measurement result of the
＜電子部品モジュール１＞
次に、本発明に係る電子部品モジュールの一例について述べる。
図５（ａ）は、フレキシブル基板における電子部品と反対側の面からの透視図であり、図５（ｂ）は、電子部品が接続されたフレキシブル基板の断面図である。
フレキシブル基板１１に貫通孔１４を形成した後、アライメントマーク１７を基準として図示しない電子回路を形成する。
電子回路からの配線パターン１８と電子部品１３の接続端子１２とは、アライメントマーク１７を基準として印刷（インクジェットやマスク印刷）により導電性ペースト１５で接続される。導電性ペースト１５は図５（ｂ）に示すように貫通孔１４にも充填される。
<Electronic component module 1>
Next, an example of the electronic component module according to the present invention will be described.
FIG. 5A is a perspective view from the surface of the flexible substrate opposite to the electronic component, and FIG. 5B is a cross-sectional view of the flexible substrate to which the electronic component is connected.
After the through
The
尚、貫通孔１４を導電性ペースト１５により埋めた後に、貫通孔１４上の導電性ペースト１５に重なるように、めっき処理で配線パターンを形成してもよい。
このような電子部品モジュールにおいても、電子部品の接続端子と配線パターンとが十分に接続される。
In addition, after filling the through
Even in such an electronic component module, the connection terminals of the electronic component and the wiring pattern are sufficiently connected.
＜電子部品モジュール２＞
次に、本発明に係る電子部品モジュールの他の一例について述べる。
図６（ａ）は、フレキシブル基板における電子部品と反対側の面から見た透視図であり、図６（ｂ）は、電子部品が接続されたフレキシブル基板の断面図である。
電子回路からの配線パターン１８と貫通孔１４との位置ずれを補正するために導電性ペースト１５を屈曲させている。
<Electronic component module 2>
Next, another example of the electronic component module according to the present invention will be described.
FIG. 6A is a perspective view of the flexible substrate viewed from the surface opposite to the electronic component, and FIG. 6B is a cross-sectional view of the flexible substrate to which the electronic component is connected.
In order to correct misalignment between the
電子部品１３の個数が複数となる場合、個々の電子部品１３の位置は部品埋め込みの精度範囲で個々にずれる。貫通孔１４と電子回路の配線位置とをカメラ等で撮影して計測した後、計測データに基づき、印刷（インクジェット等）の描画用データを作成し、作成されたデータに基づき導電性ペースト１５を塗布・充填させる。
このような電子部品モジュールにおいても、電子部品の接続端子と配線パターンとが十分に接続される。
When the number of
Even in such an electronic component module, the connection terminals of the electronic component and the wiring pattern are sufficiently connected.
＜電子部品モジュール３＞
次に、本発明に係る電子部品モジュールの他の一例について述べる。
図７は、本発明に係る電子部品モジュールの断面図の一例である。
同図に示す電子部品モジュールは、加熱・加圧によりフレキシブル基板１１に埋め込んだ電子部品１３の背面（露出面）から、樹脂１９で電子部品１３を被覆したものである。
このように樹脂１９で被覆することにより、電子部品１３の背面がフレキシブル基板１１から表出せず、取扱い等による電子部品１３の破損を防止することができる。
<Electronic component module 3>
Next, another example of the electronic component module according to the present invention will be described.
FIG. 7 is an example of a cross-sectional view of an electronic component module according to the present invention.
The electronic component module shown in the figure is obtained by coating the
By covering with the
＜電子部品モジュールの製造方法３＞
図８（ａ）〜（ｃ）は、本発明に係る電子部品モジュールの製造方法の他の実施の形態を示す工程図である。
図８（ａ）〜（ｃ）に示した実施の形態の図１（ａ）〜（ｄ）に示した実施の形態との相違点は、フレキシブル基板への電子部品の埋め込みの際に光学部品を同時に形成する点である。
<Electronic component module manufacturing method 3>
8A to 8C are process diagrams showing another embodiment of the method for manufacturing an electronic component module according to the present invention.
The difference between the embodiment shown in FIGS. 8A to 8C and the embodiment shown in FIGS. 1A to 1D is that an optical component is embedded when an electronic component is embedded in a flexible substrate. It is the point which forms simultaneously.
図８（ａ）において、フレキシブル基板１１における電子部品１１を埋め込む面とは反対面側の面に対し、加熱・加圧装置１０ｃに、光学部品としてのレンズ１１ａの形状を持たせた加熱・加圧ヘッド１０−１ｃを用いる。
図８（ｂ）において、加熱・加圧装置１０ｃで、フレキシブル基板１１を加熱・加圧しながら電子部品１１をフレキシブル基板１１の樹脂シートに埋め込む。埋め込みと同時に加熱・加圧ヘッド１０−１ｃのレンズ型内にフレキシブル基板１１の樹脂が流れ込み、レンズ１１ａが形成される。
図８（ｃ）において、貫通孔１４及び導電性ペースト１５を塗布（印刷）することにより、電子部品モジュールが得られる。これにより、固体撮像素子等の電子部品１１の受光面上にレンズ１１ａやフィルタ（偏光フィルタ等の形状により機能が発現されるもの）を樹脂で形成することが可能となる。
In FIG. 8A, the heating /
In FIG. 8B, the
In FIG.8 (c), an electronic component module is obtained by apply | coating (printing) the through-
以上において、本実施の形態によれば、フレキシブル基板の回路が形成される面と反対側の面に電子部品を当接させ、加熱・加圧することで電子部品をフレキシブル基板内に埋め込み、フレキシブル基板に貫通孔を形成し、導電性ペーストを塗布（印刷）することで電子部品モジュールが得られる。
また、電子部品をフレキシブル基板内に埋め込むことで電子部品の端子面とフレキシブル基板の回路面との間の厚さが薄くなり、貫通孔のアスペクト比を導電性ペーストの充填に適した値にすることができる。例えば、１２０μｍ厚の基板を用いて１２０μｍピッチの部品を実装する場合、貫通孔の幅は８０μｍ程度となるが、電子部品を埋め込み、残り厚を４０μｍとすることで、基板残り厚と貫通孔径との比は０．５となり、充填不具合を起こす１．０以下とすることができる。また貫通孔の形成は電子部品を埋め込んだ後に行うため、電子部品の接続端子の位置に合わせて貫通孔を形成することができあけられるので電子部品の接続端子と配線パターンとが十分に接続される。
As described above, according to the present embodiment, the electronic component is brought into contact with the surface opposite to the surface on which the circuit of the flexible substrate is formed, and the electronic component is embedded in the flexible substrate by heating and pressurizing. An electronic component module can be obtained by forming a through-hole and applying (printing) a conductive paste.
Moreover, by embedding the electronic component in the flexible substrate, the thickness between the terminal surface of the electronic component and the circuit surface of the flexible substrate is reduced, and the aspect ratio of the through hole is set to a value suitable for filling with the conductive paste. be able to. For example, when mounting a 120 μm pitch component using a 120 μm thick substrate, the width of the through hole is about 80 μm, but by embedding the electronic component and setting the remaining thickness to 40 μm, the remaining substrate thickness and the through hole diameter The ratio is 0.5, and can be 1.0 or less which causes a filling failure. Since the through hole is formed after the electronic component is embedded, the through hole can be formed in accordance with the position of the connection terminal of the electronic component, so that the connection terminal of the electronic component and the wiring pattern are sufficiently connected. The
＜効 果＞
接続端子間距離（ピッチ）が狭い電子部品であっても、フレキシブル基板の貫通孔に確実に導電性ペースト（金属微粒子）を塗布し、電子部品の接続端子に接続することができる。
フレキシブル基板に接続端子間距離（ピッチ）が狭い電子部品を、接続端子と絶縁基板の貫通孔の位置を高い精度であわせ、貫通孔内に確実に導電性ペースト（金属微粒子）を塗布することができる。
貫通孔と接続端子との位置合わせの精度を向上させることができる。
<Effect>
Even in an electronic component having a short distance (pitch) between connection terminals, it is possible to reliably apply a conductive paste (metal fine particles) to the through hole of the flexible substrate and connect it to the connection terminal of the electronic component.
Electronic components with a small distance (pitch) between connecting terminals on a flexible substrate, and the position of the through holes in the connecting terminals and insulating substrate are aligned with high accuracy, and conductive paste (metal fine particles) can be reliably applied in the through holes. it can.
The accuracy of alignment between the through hole and the connection terminal can be improved.
なお、上述した実施の形態は、本発明の好適な実施の形態の一例を示すものであり、本発明はそれに限定されることなく、その要旨を逸脱しない範囲内において、種々変形実施が可能である。 The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.
＜その他＞
特許文献１に記載の発明には、絶縁基板上の回路パターンに、直接表面実装用電子部品を接続した電子部品モジュールにおける上述した問題を解決すべくなされたもので、半田などの熱融解型接続部材を使用することなく、貫通スルーホールによる層間接続も同時に達成できる信頼性の高い電極接続を達成できる電子部品モジュールおよびその製造方法を提供することを目的としている。また、特許文献１に記載の発明は、複数の貫通孔が穿設された絶縁基板と、接続電極を貫通孔に挿入又は当接させて絶縁基板の一主面に固定された表面実装用電子部品と、絶縁基板の他主面に、その一部が表面実装用電子部品の接続電極と電気的に接触するよう形成された金属微粒子による回路パターンと、金属微粒子による回路パターン上に形成された金属めっき層とを有する電子部品モジュール及びその製造方法が開示されている。
<Others>
The invention described in Patent Document 1 is intended to solve the above-described problem in the electronic component module in which the surface mounting electronic component is directly connected to the circuit pattern on the insulating substrate. It is an object of the present invention to provide an electronic component module that can achieve highly reliable electrode connection that can simultaneously achieve interlayer connection through through-holes without using a member, and a method for manufacturing the same. The invention described in Patent Document 1 includes an insulating substrate having a plurality of through-holes and surface-mounting electrons fixed to one main surface of the insulating substrate by inserting or abutting connection electrodes into the through-holes. On the other main surface of the component and the insulating substrate, a part thereof is formed on the circuit pattern made of metal fine particles formed so as to be in electrical contact with the connection electrode of the surface mount electronic component, and on the circuit pattern made of metal fine particles An electronic component module having a metal plating layer and a manufacturing method thereof are disclosed.
特許文献１に記載の発明と本願発明とは絶縁基板に貫通孔を形成し、電子部品を背面に当接して接着させ、導電金属微粒子を塗布（印刷）する点では一見類似している。
しかし、特許文献１に記載の発明は、位置合わせが難しくなる点、絶縁基板の厚さと貫通孔の径の比（アスペクト比）が高くなるため、貫通孔内に金属微粒子が塗布されない不具合が発生するという問題は解消できていない点で本願発明とは相違する。
The invention described in Patent Document 1 and the present invention are similar at first glance in that a through hole is formed in an insulating substrate, an electronic component is brought into contact with and adhered to the back surface, and conductive metal fine particles are applied (printed).
However, the invention described in Patent Document 1 is difficult to align, and the ratio of the thickness of the insulating substrate to the diameter of the through hole (aspect ratio) increases, so that there is a problem that metal fine particles are not applied in the through hole. This is different from the present invention in that the problem of making it is not solved.
本発明は、フレキシブル基板を用いた電子機器に利用することができる。 The present invention can be used for an electronic device using a flexible substrate.
１０ａ、１０ｂ、１０ｃ 加熱・加圧装置
１０−１ａ、１０−１ｂ、１０−１ｃ 加熱・加圧ヘッド
１０−２ａ、１０−２ｂ、１０−２ｃ ステージ
１１ フレキシブル基板
１１ａ レンズ
１２ 接続端子
１３ 電子部品
１４ 貫通孔
１５ 導電性ペースト
１７ アライメントマーク
１８ 配線パターン
２０ レーザ及び撮影装置
２１ Ｘ−Ｙロボット
10a, 10b, 10c Heating / pressurizing device 10-1a, 10-1b, 10-1c Heating / pressurizing head 10-2a, 10-2b, 10-
Claims (1)
前記フレキシブル基板の他方の主面から前記接続端子まで貫通孔を形成し、
前記接続端子から貫通孔を経て前記フレキシブル基板の他方の主面に導電性ペーストを塗布することで配線パターンを形成する電子部品モジュールの製造方法であって、
前記フレキシブル基板に前記電子部品を埋め込んだ後、前記貫通孔を形成する際に、画像処理によって前記貫通孔の位置を補正すると共に、前記電子部品として固体撮像素子を用い、前記フレキシブル基板として絶縁体が透明なフレキシブル基板を用い、前記フレキシブル基板の前記電子部品の受光面側に光学部品を一体的に形成することを特徴とする電子部品モジュールの製造方法。 After contacting the connection terminal side of the electronic component for surface mounting to one main surface of the flexible substrate, the electronic component is embedded in the flexible substrate by heating and pressing,
A through hole is formed from the other main surface of the flexible substrate to the connection terminal,
A manufacturing method of a child component module collector that form a wiring pattern by applying a conductive paste on the other main surface of the flexible substrate via the through-hole from the connection terminal,
When the through hole is formed after the electronic component is embedded in the flexible substrate, the position of the through hole is corrected by image processing, a solid-state imaging device is used as the electronic component, and an insulator is used as the flexible substrate. A method for producing an electronic component module, comprising: using a transparent flexible substrate, and integrally forming an optical component on a light receiving surface side of the electronic component of the flexible substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009150716A JP5589314B2 (en) | 2009-06-25 | 2009-06-25 | Manufacturing method of electronic component module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009150716A JP5589314B2 (en) | 2009-06-25 | 2009-06-25 | Manufacturing method of electronic component module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2011009408A JP2011009408A (en) | 2011-01-13 |
| JP5589314B2 true JP5589314B2 (en) | 2014-09-17 |
Family
ID=43565731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009150716A Expired - Fee Related JP5589314B2 (en) | 2009-06-25 | 2009-06-25 | Manufacturing method of electronic component module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5589314B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3300105B1 (en) * | 2016-09-26 | 2022-07-13 | Infineon Technologies AG | Semiconductor power module and method for manufacturing the same |
| JP7247557B2 (en) | 2018-11-30 | 2023-03-29 | 株式会社リコー | CIRCUIT BOARD, CIRCUIT BOARD MANUFACTURING METHOD, IMAGING DEVICE |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5690568A (en) * | 1979-12-21 | 1981-07-22 | Fuji Photo Film Co Ltd | Semiconductor device for photoelectric transducer |
| JPS56103483A (en) * | 1980-01-21 | 1981-08-18 | Fuji Photo Film Co Ltd | Manufacture of semiconductor device for photoelectric conversion |
| JPS61220346A (en) * | 1985-03-26 | 1986-09-30 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH06821Y2 (en) * | 1987-12-25 | 1994-01-05 | シチズン時計株式会社 | Semiconductor device mounting structure |
| JP2000173947A (en) * | 1998-12-07 | 2000-06-23 | Tokai Rika Co Ltd | Plastic package |
| JP4271590B2 (en) * | 2004-01-20 | 2009-06-03 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP4342353B2 (en) * | 2004-03-17 | 2009-10-14 | 三洋電機株式会社 | Circuit device and manufacturing method thereof |
| JP2005310954A (en) * | 2004-04-20 | 2005-11-04 | Nec Corp | Semiconductor package and its manufacturing method |
| WO2009050829A1 (en) * | 2007-10-18 | 2009-04-23 | Ibiden Co., Ltd. | Wiring board and its manufacturing method |
-
2009
- 2009-06-25 JP JP2009150716A patent/JP5589314B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2011009408A (en) | 2011-01-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100276193B1 (en) | Printed circuit board, ic card and fabricating method thereof | |
| US7229293B2 (en) | Connecting structure of circuit board and method for manufacturing the same | |
| US10667387B2 (en) | Accurate positioning and alignment of a component during processes such as reflow soldering | |
| EP0530840A1 (en) | Electric circuit board module and method for producing electric circuit board module | |
| EP2374335B1 (en) | Method and apparatus for manufacturing a flexible electronic product | |
| WO2016190424A1 (en) | Anisotropic conductive film and connection structure | |
| JP6032637B2 (en) | Component mounting board manufacturing system and manufacturing method | |
| US8393076B2 (en) | Electrical connection of components | |
| CN110140433B (en) | Electronic module and method for manufacturing electronic module | |
| JP4158714B2 (en) | Method for manufacturing electronic component mounted substrate | |
| JP5589314B2 (en) | Manufacturing method of electronic component module | |
| JP6033878B2 (en) | Manufacturing method of component-embedded substrate | |
| KR101396668B1 (en) | Wiring board | |
| CN208971870U (en) | The equipment and its template scaling powder being added on the pad of component load-bearing part | |
| JP3254361B2 (en) | Manufacturing method of flexible printed wiring board | |
| JP4247634B2 (en) | Manufacturing method of electronic component mounting body, manufacturing method of electro-optical device | |
| JP2007157907A (en) | Flexible printed wiring board | |
| JP2005101506A (en) | Electronic component package, method of manufacturing the same, electrooptic device and method of manufacturing the same | |
| JP6016017B2 (en) | Manufacturing method of printed wiring board with adhesive sheet and manufacturing method of bonded printed wiring board using the same | |
| JP4954778B2 (en) | Three-dimensional electronic circuit device and connecting member | |
| KR101139694B1 (en) | A method for forming solder bumps | |
| KR101032086B1 (en) | A template for forming solder bump and a method for manufacturing thereof | |
| KR101062451B1 (en) | Template for solder bump formation and manufacturing method thereof | |
| KR100935973B1 (en) | Method for manufacturing non-shrinkage ceramic substrate | |
| JP5926898B2 (en) | Wiring board manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120412 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130118 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130205 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130401 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140121 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140224 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140701 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140714 |
|
| R151 | Written notification of patent or utility model registration |
Ref document number: 5589314 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
| LAPS | Cancellation because of no payment of annual fees |