KR20080084555A - 접합 웨이퍼의 제조 방법 - Google Patents
접합 웨이퍼의 제조 방법 Download PDFInfo
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- KR20080084555A KR20080084555A KR1020070128749A KR20070128749A KR20080084555A KR 20080084555 A KR20080084555 A KR 20080084555A KR 1020070128749 A KR1020070128749 A KR 1020070128749A KR 20070128749 A KR20070128749 A KR 20070128749A KR 20080084555 A KR20080084555 A KR 20080084555A
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- oxide film
- wafer
- manufacturing
- bonded
- ozone
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Abstract
Description
Claims (9)
- 접합 웨이퍼의 제조 방법으로서,2장의 실리콘 웨이퍼를 오존 세정하여, 상기 실리콘 웨이퍼의 표면에 막두께 2.2nm 이하의 산화막을 형성하고,형성한 산화막을 통하여 상기 2장의 실리콘 웨이퍼를 접합시켜, 접합 웨이퍼를 얻는 것을 포함하는, 상기 제조 방법.
- 제1항에 있어서,접합 웨이퍼는, 접합 계면에 국소적인 산화물을 갖지 않는 제조 방법.
- 제1항 또는 제2항에 있어서,오존 세정에는, 오존 농도가 1∼50ppm의 범위에 있는 오존수를 이용하는 제조 방법.
- 제1항 또는 제2항에 있어서,오존 세정 전에, 실리콘 웨이퍼 표면의 자연 산화막을 제거하고, 그 후에 오존 세정을 행하는 제조 방법.
- 제1항 또는 제2항에 있어서,산화막 형성 후, 접합 전에 플라즈마 처리를 행하고, 그 후, 접합을 행하는 제조 방법.
- 제5항에 있어서,플라즈마 처리는, 질소, 산소, 아르곤, 희석 수소 또는 그들의 혼합 가스에 의한 플라즈마 처리인 제조 방법.
- 제1항 또는 제2항에 있어서,실리콘 웨이퍼의 접합은, 1000℃ 이상의 온도에서의 열처리에 의해 행하는 제조 방법.
- 제1항 또는 제2항에 있어서,접합시킨 웨이퍼를 박막화하는 공정을 추가로 포함하는 제조 방법.
- 제8항에 있어서,박막화하는 공정은, 연삭 및 연마의 공정, 또는 이온 주입 박리의 공정인 제조 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JPJP-P-2007-00064482 | 2007-03-14 | ||
JP2007064482A JP5433927B2 (ja) | 2007-03-14 | 2007-03-14 | 貼り合わせウェーハの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20080084555A true KR20080084555A (ko) | 2008-09-19 |
KR100935397B1 KR100935397B1 (ko) | 2010-01-06 |
Family
ID=39529749
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070128749A KR100935397B1 (ko) | 2007-03-14 | 2007-12-12 | 접합 웨이퍼의 제조 방법 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8802540B2 (ko) |
EP (1) | EP1970949B1 (ko) |
JP (1) | JP5433927B2 (ko) |
KR (1) | KR100935397B1 (ko) |
CN (1) | CN101266917B (ko) |
SG (1) | SG146517A1 (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5664592B2 (ja) * | 2012-04-26 | 2015-02-04 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
CN111962155B (zh) * | 2020-08-06 | 2022-05-10 | 济南量子技术研究院 | 一种介质层辅助的厚片周期极化铁电晶体制备方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0719739B2 (ja) * | 1990-09-10 | 1995-03-06 | 信越半導体株式会社 | 接合ウェーハの製造方法 |
JP3542376B2 (ja) | 1994-04-08 | 2004-07-14 | キヤノン株式会社 | 半導体基板の製造方法 |
US5603779A (en) * | 1995-05-17 | 1997-02-18 | Harris Corporation | Bonded wafer and method of fabrication thereof |
JP3611142B2 (ja) * | 1995-08-29 | 2005-01-19 | 三菱住友シリコン株式会社 | 張り合わせウェーハおよびその製造方法 |
DE19780446T1 (de) * | 1996-04-26 | 1998-10-01 | Sumitomo Sitix Corp | Bindungsverfahren für eine Silizium-Halbleiterplatte |
JP3422225B2 (ja) | 1997-07-08 | 2003-06-30 | 三菱住友シリコン株式会社 | 貼り合わせ半導体基板及びその製造方法 |
US6319331B1 (en) * | 1997-12-01 | 2001-11-20 | Mitsubishi Denki Kabushiki Kaisha | Method for processing semiconductor substrate |
JPH11233476A (ja) * | 1997-12-01 | 1999-08-27 | Mitsubishi Electric Corp | 半導体基板の処理方法 |
FR2775119B1 (fr) * | 1998-02-19 | 2000-04-07 | France Telecom | Procede pour limiter l'interdiffusion dans un dispositif semi-conducteur a grille composite si/si 1-x ge x, o inferieur a x inferieur ou egal a 1. |
JP3385972B2 (ja) * | 1998-07-10 | 2003-03-10 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法および貼り合わせウェーハ |
US6230720B1 (en) * | 1999-08-16 | 2001-05-15 | Memc Electronic Materials, Inc. | Single-operation method of cleaning semiconductors after final polishing |
US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US6492283B2 (en) * | 2000-02-22 | 2002-12-10 | Asm Microchemistry Oy | Method of forming ultrathin oxide layer |
TWI333236B (en) * | 2002-12-02 | 2010-11-11 | Tadahiro Ohmi | Semiconductor device and method of manufacturing the same |
US7018909B2 (en) * | 2003-02-28 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Forming structures that include a relaxed or pseudo-relaxed layer on a substrate |
US7071077B2 (en) * | 2003-03-26 | 2006-07-04 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Method for preparing a bonding surface of a semiconductor layer of a wafer |
JP4285244B2 (ja) * | 2004-01-08 | 2009-06-24 | 株式会社Sumco | Soiウェーハの作製方法 |
JP2006080314A (ja) * | 2004-09-09 | 2006-03-23 | Canon Inc | 結合基板の製造方法 |
US8138061B2 (en) * | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
JP2006278893A (ja) * | 2005-03-30 | 2006-10-12 | Toshiba Ceramics Co Ltd | 貼り合わせウェーハの製造方法 |
JP4655797B2 (ja) * | 2005-07-19 | 2011-03-23 | 信越半導体株式会社 | 直接接合ウエーハの製造方法 |
JP2007149723A (ja) * | 2005-11-24 | 2007-06-14 | Sumco Corp | 貼り合わせウェーハの製造方法 |
JP4940737B2 (ja) * | 2006-04-11 | 2012-05-30 | 株式会社Sumco | 少数キャリア拡散長測定方法およびシリコンウェーハの製造方法 |
-
2007
- 2007-03-14 JP JP2007064482A patent/JP5433927B2/ja active Active
- 2007-12-12 KR KR1020070128749A patent/KR100935397B1/ko active IP Right Grant
- 2007-12-13 SG SG200718646-3A patent/SG146517A1/en unknown
- 2007-12-13 US US11/955,765 patent/US8802540B2/en active Active
- 2007-12-14 CN CN2007101957655A patent/CN101266917B/zh active Active
- 2007-12-18 EP EP07024471.0A patent/EP1970949B1/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN101266917A (zh) | 2008-09-17 |
EP1970949A3 (en) | 2011-06-22 |
JP2008227207A (ja) | 2008-09-25 |
US8802540B2 (en) | 2014-08-12 |
EP1970949B1 (en) | 2017-03-22 |
EP1970949A2 (en) | 2008-09-17 |
KR100935397B1 (ko) | 2010-01-06 |
SG146517A1 (en) | 2008-10-30 |
US20080227271A1 (en) | 2008-09-18 |
CN101266917B (zh) | 2010-09-08 |
JP5433927B2 (ja) | 2014-03-05 |
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